VISHAY SIHF840AS

IRF840AS, IRF840AL, SiHF840AS, SiHF840AL
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Low Gate Charge Qg Results in Simple Drive
Requirement
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
• Fully
Characterized
Capacitance
and
Avalanche Voltage and Current
• Effective Coss Specified
500
RDS(on) (Ω)
VGS = 10 V
0.85
Qg (Max.) (nC)
38
Qgs (nC)
9.0
Qgd (nC)
18
Configuration
Single
APPLICATIONS
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
• High Speed Power Switching
G
G
COMPLIANT
• Lead (Pb)-free Available
D
D2PAK
(TO-263)
I2PAK
(TO-262)
Available
RoHS*
D
TYPICAL SMPS TOPOLOGIES
S
• Two Transistor Forward
• Half Bridge
• Full Bridge
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
D2PAK (TO-263)
D2PAK (TO-263)
D2PAK (TO-263)
I2PAK (TO-262)
IRF840ASPbF
IRF840ASTRLPbFa
IRF840ASTRRPbFa
IRF840ALPbF
SiHF840AS-E3
SiHF840ASTL-E3a
SiHF840ASTR-E3a
SiHF840AL-E3
IRF840AS
IRF840ASTRLa
IRF840ASTRRa
IRF840AL
SiHF840AS
SiHF840ASTLa
SiHF840ASTRa
SiHF840AL
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
500
Gate-Source Voltage
VGS
± 30
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
IDM
Linear Derating Factor
Single Pulse Avalanche
Energyb
UNIT
V
8.0
5.1
A
32
1.0
W/°C
mJ
EAS
510
Repetitive Avalanche Currenta
IAR
8.0
A
Repetitive Avalanche Energya
EAR
13
mJ
Maximum Power Dissipation
TC = 25 °C
TA = 25 °C
Peak Diode Recovery dV/dtc, e
Operating Junction and Storage Temperature Range
Soldering Temperature
for 10 s
PD
125
3.1
dV/dt
5.0
TJ, Tstg
- 55 to + 150
300d
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 16 mH, RG = 25 Ω, IAS = 8.0 A (see fig. 12).
c. ISD ≤ 8.0 A, dI/dt ≤ 100 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. Uses IRF840A/SiH840A data and test conditions.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91066
S-81412-Rev. A, 07-Jul-08
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IRF840AS, IRF840AL, SiHF840AS, SiHF840AL
Vishay Siliconix
THERMAL RESISTANCE RATINGS
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
(PCB Mount)a
PARAMETER
RthJA
-
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
-
1.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0 V, ID = 250 µA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mAd
-
0.58
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
-
-
0.85
Ω
VDS = 50 V, ID = 4.8 A
3.7
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
-
1018
-
-
155
-
8.0
-
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = 4.8 Ab
VGS = 10 V
µA
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Coss
Output Capacitance
Effective Output Capacitance
Total Gate Charge
Coss
-
VDS = 1.0 V, f = 1.0 MHz
VGS = 0 V
Coss eff.
VDS = 400 V, f = 1.0 MHz
42
VDS = 0 V to 480 Vc, d
56
Qg
ID = 8.0 A, VDS = 400 V,
see fig. 6 and 13b, d
-
-
38
pF
Gate-Source Charge
Qgs
-
-
9.0
Gate-Drain Charge
Qgd
-
-
18
Turn-On Delay Time
td(on)
-
11
-
tr
-
23
-
-
26
-
-
19
-
-
-
8.0
S
-
-
32
Vb
-
-
2.0
V
-
422
633
ns
-
2.0
3.0
µC
Rise Time
Turn-Off Delay Time
Fall Time
td(off)
VGS = 10 V
1490
VDD = 250 V, ID = 8.0 A,
RG = 9.1 Ω, RD = 31 Ω, see fig. 10b, d
tf
nC
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 8.0 A, VGS = 0
TJ = 25 °C, IF = 8.0 A, dI/dt = 100 A/µsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
d. Uses IRF840A/SiHF840A data and test conditions
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Document Number: 91066
S-81412-Rev. A, 07-Jul-08
IRF840AS, IRF840AL, SiHF840AS, SiHF840AL
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
100
10
1
4.5V
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
100
TJ = 150 ° C
10
TJ = 25 ° C
1
0.1
4.0
Fig. 1 - Typical Output Characteristics
3.0
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.5V
1
20µs PULSE WIDTH
TJ = 150 °C
10
VDS , Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91066
S-81412-Rev. A, 07-Jul-08
100
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
10
1
6.0
7.0
8.0
9.0
Fig. 3 - Typical Transfer Characteristics
TOP
0.1
0.1
5.0
VGS , Gate-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
100
V DS = 50V
20µs PULSE WIDTH
8.0
ID = 7.4A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRF840AS, IRF840AL, SiHF840AS, SiHF840AL
Vishay Siliconix
C, Ca pac ita nc e(pF )
ISD , Reverse Drain Current (A)
100
TJ = 150 ° C
10
TJ = 25 ° C
1
0.1
0.2
V GS = 0 V
0.5
0.8
1.1
1.4
VSD ,Source-to-Drain Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
100
8.0 A
ID = 7.4
VDS = 400V
VDS = 250V
VDS = 100V
16
OPERATION IN THIS AREA LIMITED
BY RDS(on)
10us
I D , Drain Current (A)
VGS , Gate-to-Source Voltage (V)
20
Fig. 7 - Typical Source-Drain Diode Forward Voltage
12
8
10
100us
1ms
1
10ms
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
10
20
30
40
Q G , Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
10
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91066
S-81412-Rev. A, 07-Jul-08
IRF840AS, IRF840AL, SiHF840AS, SiHF840AL
Vishay Siliconix
RD
VDS
8.0
VGS
D.U.T.
I D , Drain Current (A)
RG
6.0
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
4.0
Fig. 10a - Switching Time Test Circuit
2.0
VDS
90 %
0.0
25
50
75
100
TC , Case Temperature
125
150
10 %
VGS
( °C)
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.1
P DM
0.10
t1
0.05
t2
0.02
0.01
0.01
0.00001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
SINGLE PULSE
(THERMAL RESPONSE)
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 91066
S-81412-Rev. A, 07-Jul-08
www.vishay.com
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IRF840AS, IRF840AL, SiHF840AS, SiHF840AL
Vishay Siliconix
Driver
L
VDS
D.U.T.
RG
+
A
- VDD
IAS
20 V
tp
V D S a v , A valan che V oltag e ( V )
15 V
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
VDS
tp
Fig. 12d - Typical Drain-to-Source Voltage vs.
Avalanche Current
IAS
Fig. 12b - Unclamped Inductive Waveforms
QG
10 V
QGS
EAS , Single Pulse Avalanche Energy (mJ)
1200
TOP
1000
BOTTOM
ID
3.6A
5.1A
8.0A
QGD
VG
Charge
800
Fig. 13a - Basic Gate Charge Waveform
600
Current regulator
Same type as D.U.T.
400
50 kΩ
12 V
0.2 µF
200
0.3 µF
+
D.U.T.
-
VDS
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
VGS
3 mA
IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
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Document Number: 91066
S-81412-Rev. A, 07-Jul-08
IRF840AS, IRF840AL, SiHF840AS, SiHF840AL
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91066.
Document Number: 91066
S-81412-Rev. A, 07-Jul-08
www.vishay.com
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
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Document Number: 91000
Revision: 18-Jul-08
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