NCN2612 6-Differential Channel 1:2 Switch for PCIe 2.0 and Display Port 1.1 The NCN2612 is a 6−Channel differential SPDT switch designed to route PCI Express Gen2 and/or DisplayPort 1.1a signals. Due to the ultra−low ON−state capacitance (4.1 pF typ) and resistance (7 typ), these switches have a signal bit rate (BR) of 5 Gbps, ideal for high frequency data signals. This switch pinout is designed to be used in ATX form factor desktop PCs and is available in a space−saving WQFN package. The NCN2612 uses 80% less quiescent power than other comprable PCIe switches. http://onsemi.com MARKING DIAGRAM 1 NCN2612 AWLYYWWG Features • • • • • • • • • WQFN56 CASE 510AK VDD Power Supply from 3 V to 3.6 V Low Supply Current 250 A typ 6 Differential Channels 2:1 MUX/DEMUX Compatible with Display Port 1.1a & PCIe 2.0 Data Rate: Supports 5 Gbps Low Ron Resistance: 7 typ Low Con Capacitance: 4.1 pF Space Saving Small WQFN−56 Package This is a Pb−Free Device A WL YY WW G ORDERING INFORMATION Typical Applications • Notebook Computers • Desktop Computers • Server/Storage Networks © Semiconductor Components Industries, LLC, 2011 February, 2011 − Rev. 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Device Package Shipping† NCN2612MTTWG WQFN56 (Pb−Free) 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 Publication Order Number: NCN2612/D NCN2612 IN_0+ D0+ IN_0− D0− IN_1+ D1+ IN_1− D1− IN_2+ D2+ IN_2− D2− IN_3+ D3+ IN_3− D3− Tx0+ Tx0− Tx1+ Tx1− Tx2+ Tx2− Tx3+ Tx3− OUT+ AUX+ OUT− AUX− X+ HPD1 X− HPD2 Rx0+ Rx0− Rx1+ Rx1− SEL Logic Control LE Figure 1. NCN2612 Block Diagram TRUTH TABLE (SEL Control) Function TRUTH TABLE (Latch Control) SEL LE PCI_Express Gen2 Path is Active (Tx, Rx) L 0 Respond to Changes on SEL Digital Video Port is Active (Dx, HPDx, AUX) H 1 Latched http://onsemi.com 2 Internal Mux Select 49 GND 50 VDD 51 Tx1− 52 Tx1+ 53 Tx0− 54 Tx0+ 55 VDD 56 GND NCN2612 GND 1 48 GND IN_0+ 2 47 Tx2+ IN_0− 3 46 Tx2− IN_1+ 4 45 Tx3+ IN_1− 5 44 Tx3− VDD 6 43 D0+ IN_2+ 7 42 D0− IN_2− 8 41 D1+ IN_3+ 9 40 D1− Exposed Pad on Underside (solder to external Gnd) IN_3− 10 GND 11 OUT+ 12 39 D2+ 38 D2− 37 D3+ OUT− 13 36 D3− X+ 14 35 GND X− 15 34 VDD 16 33 Rx0+ VDD 17 32 Rx0− 18 31 Rx1+ LE 19 30 Rx1− 29 GND Figure 2. Pinout (Top View) http://onsemi.com 3 GND 28 VDD 27 AUX+ 26 AUX− 25 HPD1 24 20 HPD2 23 GND VDD 22 SEL GND 21 GND NCN2612 PIN FUNCTION AND DESCRIPTION Pin Name 6, 17, 22, 27, 34,50, 55 VDD DC Supply, 3.3 V $10% Description 1, 11, 16, 20, 21, 28, 29, 35, 48, 49, 56 GND Power Ground. Exposed Pad − 2 IN_0+ Differential input from GMCH PCIE outputs. IN_0+ makes a differential pair with IN_0−. 3 IN_0− Differential input from GMCH PCIE outputs. IN_0− makes a differential pair with IN_0+. 4 IN_1+ Differential input from GMCH PCIE outputs. IN_1+ makes a differential pair with IN_1−. 5 IN_1− Differential input from GMCH PCIE outputs. IN_1− makes a differential pair with IN_1+. 7 IN_2+ Differential input from GMCH PCIE outputs. IN_2+ makes a differential pair with IN_2−. 8 IN_2− Differential input from GMCH PCIE outputs. IN_2− makes a differential pair with IN_2+. 9 IN_3+ Differential input from GMCH PCIE outputs. IN_3+ makes a differential pair with IN_3−. 10 IN_3− Differential input from GMCH PCIE outputs. IN_3− makes a differential pair with IN_3+. 12 OUT+ Pass−through output from AUX+ input when SEL = 1. Pass−through output from Rx0+ input when SEL = 0. 13 OUT− Pass−through output from AUX− input when SEL = 1. Pass−through output from Rx0− input when SEL = 0. 14 X+ X+ is an analog pass−through output corresponding to Rx1+. 15 X− X− is an analog pass−through output corresponding to the Rx1− input. The path from Rx1− to X− must be matched with the path from Rx1+ to X+. X+ and X− form a differential pair when the pass−through mux mode is selected. 18 SEL The exposed pad on the backside of package is internally connected to Gnd. Externally the exposed pad should also be user−connected to GND. SEL controls the mux through a flow−through latch. SEL = 0 for PCIE Mode; SEL = 1 for DP Mode 19 LE 43, 42 D0+, D0− The latch gate is controlled by LE. Analog pass−through output#1 corresponding to IN_0+ and IN_0−, when SEL = 1. 41, 40 D1+, D1− Analog pass−through output#1 corresponding to IN_1+ and IN_1−, when SEL = 1. 39, 38 D2+, D2− Analog pass−through output#1 corresponding to IN_2+ and IN_2−, when SEL = 1. 37, 36 D3+, D3− Analog pass−through output#1 corresponding to IN_3+ and IN_3−, when SEL = 1. 54, 53 Tx0+, Tx0− Analog pass−through output#2 corresponding to IN_0+ and IN_0− when SEL = 0. 52, 51 Tx1+, Tx1− Analog pass−through output#2 corresponding to IN_1+ and IN_1− when SEL = 0. 47, 46 Tx2+, Tx2− Analog pass−through output#2 corresponding to IN_2+ and IN_2− when SEL = 0. 45, 44 Tx3+, Tx3− Analog pass−through output#2 corresponding to IN_3+ and IN_3− when SEL = 0. 26 AUX+ Differential input from HDMI/DP connector. AUX+ makes a differential pair with AUX−. AUX+ is passed through to the OUT+ pin when SEL = 1. 25 AUX− Differential input from HDMI/DP connector. AUX− makes a differential pair with AUX+. AUX− is passed through to the OUT− pin when SEL = 1. 24 HPD1 Positive low frequency HPD input handshake protocol signal. 23 HPD2 Negative low frequency HPD input handshake protocol signal (normally not connected). 33 Rx0+ Differential input from PCIE connector or device. Rx0+ makes a differential pair with Rx0−. Rx0+ is passed through to the OUT+ pin when SEL = 0. 32 Rx0− Differential input from PCIE connector or device. Rx0− makes a differential pair with Rx0+. Rx0− is passed through to the OUT− pin when SEL = 0. 31 Rx1+ Differential input from PCIE connector or device. Rx1+ makes a differential pair with Rx1−. Rx1+ is passed through to the X+ pin when SEL = 0. 30 Rx1− Differential input from PCIE connector or device. Rx1− makes a differential pair with Rx1+. Rx1− is passed through to the X− pin on the path that matches the Rx1+ to X+ pin. http://onsemi.com 4 NCN2612 MAXIMUM RATINGS Parameter Symbol Rating Unit VDD −0.5 v VDD v 5.3 V VI & VO −0.7 vVI v VDD + 0.3 V VSEL −0.5 vVI v VDD + 0.3 V Continuous Current Through One Switch Channel IIO $120 mA Maximum Junction Temperature (Note 1) TJ 150 °C Power Supply Voltages Input/Output Voltage Range of the Switch Selection Pin Voltages Operating Ambient Temperature TA −40 to +85 °C Storage Temperature Range Tstg −65 to +150 °C Thermal Resistance, Junction−to−Air (Note 2) RJA 37 °C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. 2. This parameter is based on EIA/JEDEC 51−7 with a 4−layer PCB, 80mm x 80mm, two 1oz Cu material internal planes and top planes of 2oz Cu material. http://onsemi.com 5 NCN2612 ELECTRICAL CHARACTERISTICS (VDD = +3.3V $10%, TA = −40°C to +85°C and TJ up to 125°C, unless otherwise noted. All Typical values are at VDD = +3.3 V, TA = +25°C, unless otherwise noted) Symbol Characteristics Conditions Min Typ Max Unit 3.0 3.3 3.6 V 250 500 A VDD V POWER SUPPLY VDD Supply Voltage Range IDD Power Supply Current VDD = 3.6 V, VIN = GND or VDD DATA SWITCH PERFORMANCE (for both PCIe and Display Port applications, unless otherwise noted) VIN Data Input/Output Voltage Range −0.1 RON On Resistance (Tx, Rx) VDD = 3 V, 0 V v VIN v VDD, IIN = 40 mA 7 13 RON On Resistance (Dx,HPDx,AUX) VDD = 3 V, 0 V v VIN v VDD, IIN = 40 mA 7.5 13 RON(flat) On Resistance Flatness VDD = 3 V, 0 V v VIN v VDD, IIN = 40 mA 0.1 1.24 RON On Resistance Matching (Tx, Rx) VDD = 3 V, VIN = 0 V, IIN = 40 mA 0.35 RON On Resistance Matching (Dx,HPDx,AUX) VDD = 3 V, VIN = 0 V, IIN = 40 mA 0.35 CON On Capacitance f = 1 MHz, Switch On, Open Output 4.1 pF COFF Off Capacitance f = 1 MHz, Switch Off 2.6 pF ION On Leakage Current (IN_/ X_/OUT_) VDD = +3.6 V, VIN_ = VX_ = VOUT_ = 0 V, +1.2 V; VD_ or VTX_ or VHPD_ or VRX_ or VAUX_ = unconnected −1 +1 A IOFF Off Leakage Current (D_/ TX_/ HPD_ / RX_/ AUX_) VDD = +3.6 V, VIN_ = VX_ = VOUT_ = 0 V, +1.2 V; VD_ or VTX_, VHPD_ / AUX_ or VRX_ = 1.2 V, 0 V −1 +1 A CONTROL LOGIC CHARACTERISTICS (SEL and LE pins) VIL Off voltage input 0 0.8 V VIH High voltage input 2 VDD V IIN Off voltage input −1 +1 A CIN High voltage input VIN = 0 V or VDD f = 1 MHz 1 pF Signal Data Rate RS = RL = 100 differential 5 Gbps Differential Insertion Loss RS = RL = 50 , F = 2.7 GHz −4 dB RS = RL = 50 , F = 5 GHz −7 RS = RL = 50 , F = 7.5 GHz −13 RS = RL = 50 , F = 100 MHz −41 RS = RL = 50 , F = 1.35 GHz −19 RS = RL = 50 , F = 3 GHz −16 RS = RL = 50 , F = 2.5 GHz −27 RS = RL = 50 , F = 5 GHz −20 RS = RL = 50 , F = 7.5 GHz −10 DYNAMIC CHARACTERISTICS BR ILOSS VISO Xtalk Differential Off Isolation Differential Crosstalk http://onsemi.com 6 dB dB NCN2612 SWITCHING CHARACTERISTICS (VDD = +3.3 V, TA = 25°C, unless otherwise specified) Symbol Characteristics Conditions TSK1 Bit−to−bit skew within same differential channel RS = 50 , RL = 200 , CL = 4 pF Min Typ 7 Max Unit ps TSK2 Channel−to−channel skew RS = 50 , RL = 200 , CL = 4 pF 55 ps SELECTION PINS SWITCHING CHARACTERISTICS (VDD = +3.3 V, TA = 25°C, unless otherwise specified) Symbol Characteristics Conditions TSELON SEL to Switch turn ON time TSELOFF Min Typ Max Unit VDX_A or VDX_B = +1.0 V, RL = 50 , VHPD_ X or VAUX_X = +1.0 V, RL = 50 , LE = VDD, CL = 100 pf 8 20 ns SEL to Switch turn OFF time VDX_A or VDX_B = +1.0 V, RL = 50 , VHPD_ X or VAUX_X = +1.0 V, RL = 50 , LE = VDD, CL = 100pf 5 10 ns TSET LE setup time SEL to LE VDX_A or VDX_B = +1.0 V, RL = 50 , VHPD_ X or VAUX_X = +1.0 V, RL = 50 , LE = VDD, CL = 100 pf 1 ns THOLD LE hold time LE to SEL VDX_A or VDX_B = +1.0 V, RL = 50 , VHPD_ X or VAUX_X = +1.0 V, RL = 50 , LE = VDD, CL = 100 pf 1 ns NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 7 NCN2612 +3.3V VDD 0V 50 50 50 50 50 50 SEL LE VDD +3.3V 0.1 F IN_+ X+ OUT+ NCN2612 IN_− X− OUT− D+ D− HPD2 AUX+ AUX− GND PORT 1 VIN+ 50 PORT 2 VIN− 50 PORT 3 VOUT+ TX+ RX1+ RX0+ HPD1 PORT 1 VOUT− TX− RX1− RX0− VDD 0V 50 50 50 50 50 50 50 50 SEL LE VDD ǒ Ǔ IN_− X− OUT− D− TX+ RX1+ RX0+ HPD1 HPD2 AUX+ AUX− Differential Off Isolation + 20log Figure 3. Differential Insertion Loss/Differential Return Loss 50 50 50 50 50 Network Analyzer PORT 1 VIN+ 50 PORT 2 VIN− 50 PORT 3 VOUT+ 50 PORT 1 VOUT− 50 Ǔ V OUT) * V OUT* V IN) * V IN* Figure 4. Differential Off−Isolation +3.3V 50 TX− RX1− RX0− ǒ V OUT) * V OUT* V IN) * V IN* 0V or VDD 0V IN_+ X+ OUT+ NCN2612 D+ GND Differential Insertion Loss + 20log 0.1 F Network Analyzer VDD SEL LE 0.1 F IN_+ X+ OUT+ NCN2612 D+/D− HPD1/HPD2 AUX+/AUX− TX+/TX− RX1+/RX1− RX0+/RX0− GND IN_− X− OUT− IN_+ X+ OUT+ IN_− X− OUT− Differential Crosstalk + 20log Network Analyzer PORT 1 VIN+ 50 PORT 2 VIN− 50 PORT 3 VOUT+ 50 PORT 1 VOUT− 50 ǒ Ǔ V OUT) * V OUT* V IN) * V IN* Figure 5. Differential Crosstalk Measurements are standardized against shorts at IC terminals. Differential OFF−Isolation is measured between IN_ and “OFF” D or TX, X and “OFF” HPD or RX1, OUT and “OFF” AUX or RX0 terminal on each switch under Figure 3. Differential ON−Isolation is measured between IN_ and “ON” D or TX, X and “ON” HPD or RX1, OUT and “ON” AUX or RX0 terminal on each switch under Figure 4. Differential Crosstalk is measured between any two pairs. http://onsemi.com 8 NCN2612 PACKAGE DIMENSIONS WQFN56 5x11, 0.5P CASE 510AK−01 ISSUE A ÉÉÉ ÉÉÉ ÉÉÉ A B D PIN ONE LOCATION L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L1 DETAIL A ALTERNATE CONSTRUCTIONS ÉÉ ÉÉ E EXPOSED Cu DIM A A1 A3 b D D2 E E2 e K L L1 MOLD CMPD DETAIL B 0.15 C ALTERNATE CONSTRUCTION TOP VIEW 0.15 C DETAIL B (A3) 0.10 C 0.08 C SIDE VIEW NOTE 4 A RECOMMENDED SOLDERING FOOTPRINT* A1 C 5.30 SEATING PLANE D2 56X 56X 0.63 2.50 0.10 C A B DETAIL A MILLIMETERS MIN MAX 0.70 0.80 −−− 0.05 0.20 REF 0.20 0.30 5.00 BSC 2.30 2.50 11.00 BSC 8.30 8.50 0.50 BSC 0.20 MIN 0.30 0.50 −−− 0.15 L 1 0.10 C A B 11.30 8.50 E2 PKG OUTLINE 1 K 0.50 PITCH 56 e 56X e/2 BOTTOM VIEW b 0.10 C A B 0.05 C NOTE 3 56X 0.35 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 9 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCN2612/D