FDS5692Z N-Channel UltraFET Trench® MOSFET 50V, 5.8A, 24mΩ Features General Description Max rDS(on) = 24mΩ at VGS = 10V, ID = 5.8A Max rDS(on) = 33mΩ at VGS = 4.5V, ID = 5.6A ESD protection diode (note 3) Applications Low Qgd Fast switching speed This N-Channel UltraFET device has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on) and fast switching speed. DC/DC converter D D D D SO-8 S S S G MOSFET Maximum Ratings Symbol 5 4 6 3 7 2 8 1 TA=25oC unless otherwise noted Ratings Units VDS Drain-Source Voltage Parameter 50 V VGS Gate-Source Voltage ± 20 V ID Drain Current – Continuous 5.8 A EAS Single Pulse Avalanche Energy PD UltraFET Dissipation for Single Operation (Note 1a) – Pulsed TJ, TSTG 40 72 mJ (Note 1a) 2.5 W (Note 1b) 1.2 (Note 1c) 1.1 Operating and Storage Junction Temperature Range –55 to 150 °C °C/W Thermal Characteristics RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 50 RθJA Thermal Resistance, Junction-to-Ambient (Note 1c) 125 RθJC Thermal Resistance, Junction-to-Case (Note 1) 25 Package Marking and Ordering Information Device Marking Device Package Reel Size Tape width Quantity FDS5692Z FDS5692Z SO-8 13” 12mm 2500units ©2006 Fairchild Semiconductor Corporation FDS5692Z Rev C(W) www.fairchildsemi.com FDS5692Z N-Channel UltraFET Trench® MOSFET February 2006 Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Min Typ Max Units Drain-Source Avalanche Ratings EAS IAS Drain-Source Avalanche Energy (Single Pulse) Drain-Source Avalanche Current VDD = 50 V, ID= 12 A, L=1mH 72 12 mJ A Off Characteristics BVDSS ΔBVDSS ΔTJ ID = 250 μA 50 V Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient ID = 250 μA, Referenced to 25°C IDSS Zero Gate Voltage Drain Current VDS = 40 V VGS = 0 V 1 μA IGSS Gate–Body Leakage VGS = ± 20V, VDS = 0 V ± 10 μA 3 V On Characteristics VGS(th) ΔVGS(th) ΔTJ rDS(on) VGS = 0 V, 48 mV/°C (Note 4) Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance VDS = VGS, ID = 250 μA ID = 250 μA, Referenced to 25°C 1 1.6 –6 mV/°C ID = 5.8 A VGS = 10 V, ID = 5.6 A VGS = 4.5 V, VGS = 10 V, ID = 5.8A, TJ = 125°C 20 26 32 VDS = 25 V, f = 1.0 MHz 1025 pF 150 pF 50 pF 24 33 41 mΩ Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Gate Resistance Qg(TOT) Total Gate Charge, VGS = 10V Qg(TOT) Total Gate Charge, VGS = 5V Qgs Gate–Source Gate Charge 2.8 nC Qgd Gate–Drain Gate Charge 3.0 nC Switching Characteristics td(on) Turn–On Delay Time V GS = 0 V, f = 1.0 MHz VDS = 25V, 18 25 Ω nC 10 14 nC 0.79 ID = 5.8A (Note 4) VDD = 25 V, VGS = 10 V, ID = 5.8A, RGEN = 6 Ω 9 18 ns ns tr Rise Time 5 10 td(off) Turn–Off Delay Time 27 43 ns tf Fall Time 6 12 ns FDS5692Z Rev C(W) www.fairchildsemi.com FDS5692Z N-Channel UltraFET Trench® MOSFET Electrical Characteristics Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Min Typ Max Units IS = 5.8 A 0.79 1.25 V IS = 2.9 A 0.75 1.0 V Drain–Source Diode Characteristics VSD Drain–Source Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IF = 6A, dIF/dt = 100A/μs 24 ns 16 nC Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 50°C/W when 2 mounted on a 1in pad of 2 oz copper b) 105°C/W when 2 mounted on a .04 in pad of 2 oz copper c) 125°C/W when mounted on a minimum pad. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0% 3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. FDS5692Z Rev C(W) www.fairchildsemi.com FDS5692Z N-Channel UltraFET Trench® MOSFET Electrical Characteristics 40 2.4 ID, DRAIN CURRENT (A) VGS = 3.0V 4.0V NORMALIZED DRAIN-SOURCE ON-RESISTANCE 4.5V VGS = 10V 32 6.0V 3.5.V 24 16 3.0V 8 2.2 2 1.8 3.5V 1.6 4.0V 4.5V 1.4 5.0V 6.0V 1.2 10V 1 2.5V 0 0.8 0 1 2 3 VDS, DRAIN-SOURCE VOLTAGE (V) 0 4 Figure 1. On-Region Characteristics. 30 40 0.09 ID = 5.8A VGS = 5V ID = 2.9A rDS(on), ON-RESISTANCE (OHM) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 -50 0.07 0.05 o TA = 125 C 0.03 o TA = 25 C 0.01 -25 0 25 50 75 100 125 150 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) o TJ, JUNCTION TEMPERATURE ( C) Figure 3. On-Resistance Variation with Temperature. 10 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 o VDS = 5V IS, REVERSE DRAIN CURRENT (A) 40 ID, DRAIN CURRENT (A) 20 ID, DRAIN CURRENT (A) Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 2 NORMALIZED DRAIN-SOURCE ON-RESISTANCE 10 o TA = -55 C 125 C 30 o 25 C 20 10 VGS = 0V 10 TA = 125oC 1 25oC 0.1 -55oC 0.01 0.001 0.0001 0 0 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. FDS5692Z Rev C(W) 5 0 0.2 0.4 0.6 0.8 1 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. www.fairchildsemi.com FDS5692Z N-Channel UltraFET Trench® MOSFET Typical Characteristics 1500 f = 1MHz VGS = 0 V ID = 5.8A 8 1200 CAPACITANCE (pF) VGS, GATE-SOURCE VOLTAGE (V) 10 VDS = 20V 30V 6 25V 4 2 900 Ciss 600 Coss 300 Crss 0 0 0 4 8 12 16 20 0 5 Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics. 15 20 25 30 Figure 8. Capacitance Characteristics. 40 P(pk), PEAK TRANSIENT POWER (W) 100 100µs RDS(ON) LIMIT ID, DRAIN CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 1ms 10ms 100ms 10 1s 10s 1 DC VGS = 10V SINGLE PULSE o RθJA = 125 C/W 0.1 TA = 25oC 0.01 0.01 0.1 1 10 VDS, DRAIN-SOURCE VOLTAGE (V) 100 SINGLE PULSE RθJA = 125°C/W TA = 25°C 30 20 10 0 0.001 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE Figure 9. Maximum Safe Operating Area. 0.01 0.1 1 t1, TIME (sec) 10 100 Figure 10. Single Pulse Maximum UltraFET Dissipation. 1 D = 0.5 RθJA(t) = r(t) * RθJA RθJA = 125 °C/W 0.2 0.1 0.1 0.05 P(pk) 0.02 0.01 t1 0.01 t2 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 t1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design. FDS5692Z Rev C(W) www.fairchildsemi.com FDS5692Z N-Channel UltraFET Trench® MOSFET Typical Characteristics TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST® ActiveArray™ FASTr™ Bottomless™ FPS™ Build it Now™ FRFET™ CoolFET™ GlobalOptoisolator™ CROSSVOLT™ GTO™ DOME™ HiSeC™ EcoSPARK™ I2C™ E2CMOS™ i-Lo™ EnSigna™ ImpliedDisconnect™ FACT™ IntelliMAX™ FACT Quiet Series™ Across the board. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I18