TI SN74BCT2423A

SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
D
D
D
D
Multiplexed Real-Time and Latched Data
Byte Control for Byte-Write Applications
Useful in NuBust Interface Applications
Useful in Memory Interleave Applications
D
D
BiCMOS Design Substantially Reduces
Standby Current
Dependable Texas Instruments Quality and
Reliability
A0
A1
A2
A3
A4
A5
A6
A7
GND
A8
A9
A10
A11
A12
A13
A14
A15
SN74BCT2423A . . . FN PACKAGE
(TOP VIEW)
10
9 8
7
6
5 4
3 2 1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
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15
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51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AENM
ALE
VCC
VCC
AB15
AB14
AB13
AB12
GND
AB11
AB10
AB 9
AB 8
GND
ABENM
ABLEB
BENM
B0
B1
B2
B3
B4
B5
B6
B7
GND
B8
B9
B10
B11
B12
B13
B14
B15
AENL
ABLEA
ABENL
GND
AB 7
AB 6
AB 5
AB 4
GND
AB 3
AB 2
AB 1
AB 0
VCC
A / BSEL
BLE
BENL
NuBus is a trademark of Texas Instruments Incorporated.
Copyright  1990, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
A0
A1
A2
A3
A4
A5
A6
A7
GND
A8
A9
A10
A11
A12
A13
A14
A15
SN74BCT2424A . . . FN PACKAGE
(TOP VIEW)
10
9 8
7
6
5 4
3 2 1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
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51
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50
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49
22
48
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47
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46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AENM
ALE
VCC
VCC
AB15
AB14
AB13
AB12
GND
AB11
AB10
AB 9
AB 8
GND
ABENM
ABLEB
BENM
B0
B1
B2
B3
B4
B5
B6
B7
GND
B8
B9
B10
B11
B12
B13
B14
B15
AENL
ABLEA
ABENL
GND
AB 7
AB 6
AB 5
AB 4
GND
AB 3
AB 2
AB 1
AB 0
VCC
A / BSEL
BLE
BENL
description
The ’BCT2423A and ’BCT2424A are general-purpose 16-bit bidirectional transceivers with data storage latches
and byte control circuitry arranged for use in applications where two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing
of address and data information in microprocessor- or bus-interface applications. These devices are also useful
in memory-interleaving applications. The ’BCT2423A and ’BCT2424A offer inverted and noninverted data
paths, respectively.
The ’BCT2423A and ’BCT2424A were designed using Texas Instruments BiCMOS process, which features
bipolar drive characteristics, but also greatly reduces the standby power of the device when disabled. This is
valuable when the device is not performing an address or data transfer.
Three 16-bit I/O ports, A15 –A0, B15 –B0, and AB15 –AB0 are available for address and/or data transfer. The
AENM, AENL, BENM, BENL, ABENM, and ABENL inputs control the bus transceiver functions. These control
signals also allow byte-control of the most significant byte and least significant byte for each bus.
Address and/or data information can be stored using the internal storage latches. The ALE, BLE, ABLEA, and
ABLEB inputs are active low, and are used to control data storage. When the latch enable input is low, the latch
is transparent. When the latch enable input goes high, the data present at the inputs is latched, and remains
latched until the latch enable input is returned low.
Data on the ’A’ bus and ’B’ bus are multiplexed onto the ’AB’ bus via the A /BSEL control line. When A /BSEL
is low, A15 –A0 is mapped to the AB15 –AB0 outputs. When A /BSEL is high, B15 –B0 is mapped to the
AB15–AB0 outputs.
The SN74BCT2423A and SN74BCT2424A are characterized for operation from 0°C to 70°C.
2
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SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
logic symbol for the ’BCT2423A†
Φ
LATCHED MUX / DMUX
’BCT2423A
ALE
AENL
AENM
A0
59
10
60
9
ALE
AENL
AENM
0
ABLEA
ABLEB
ABENL
ABENM
0
11
45
12
46
22
ABLEA
ABLEB
ABENL
ABENM
AB0
AL
A7
A8
2
66
7
8
ABL
3
4
19
17
AB3
AB4
AM
A 15
A / BSEL
B0
61
24
27
15
ASEL
BSEL
0
7
8
14
48
AB7
AB8
BL
B7
B8
34
36
ABM
7
8
BM
B 15
BLE
BENL
BENM
43
25
26
44
11
12
13
51
53
AB11
AB12
56
AB 15
15
BLE
BENL
BENM
† These logic symbols are in accordance with ANSI/IEEE Std 91-1984.
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3
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
logic symbol for the ’BCT2424A†
Φ
LATCHED MUX / DMUX
’BCT2424A
ALE
AENL
AENM
A0
59
10
60
9
ALE
AENL
AENM
0
ABLEA
ABLEB
ABENL
ABENM
0
11
45
12
46
22
ABLEA
ABLEB
ABENL
ABENM
AB0
AL
A7
A8
2
66
7
8
ABL
3
4
19
17
AB3
AB4
AM
A 15
A / BSEL
B0
61
24
27
15
ASEL
BSEL
0
7
8
BL
B7
B8
34
36
ABM
7
8
13
BM
B 15
BLE
BENL
BENM
43
25
26
44
15
BLE
BENL
BENM
† These logic symbols are in accordance with ANSI/IEEE Std 91-1984.
4
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11
12
• DALLAS, TEXAS 75265
14
48
51
53
56
AB7
AB8
AB11
AB12
AB 15
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
logic diagram for ’BCT2423A (positive logic)
AENL
C1
ABLEA
8
8
A7–A0
16 X
16
D1
8
8
A 15 – A 8
AENM
ALE
16
C1
ABENL
16 X
16
D1
G1
MUX
AB 7 – AB 0
A / BSEL
8
16
BLE
C1
1
8
16 X
16
16
AB15 – AB8
1
D1
ABENM
BENL
C1
B7–B0
8
8
16
ABLEB
16 X
D1
B 15 – B 8
8
8
BENM
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5
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
logic diagram for ’BCT2424A (positive logic)
AENL
C1
A7–A0
ABLEA
8
8
16 X
16
D1
8
8
A 15 – A 8
AENM
ALE
16
C1
16 X
ABENL
16
D1
G1
MUX
AB 7 – AB 0
A / BSEL
8
16
C1
BLE
1
8
16 X
16
16
AB15 – AB 8
1
D1
ABENM
BENL
C1
B7–B0
8
8
16
16 X
D1
B 15 – B 8
8
8
BENM
6
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ABLEB
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
Terminal Functions
TERMINAL PINS
DESCRIPTION
A 15 – A 0
A bus. This 16-bit I/O port allows for transmission of data and/or address information to or from the AB bus.
Information transfer between the A bus and the AB bus is inverting for the ’BCT2423A and noninverting for the
’BCT2424A.
AB 15 – AB 0
(’BCT 2423A)
AB 15 – AB 0
(’BCT 2424A)
AB Bus. This 16-bit i/o port allows for multiplexed transmission of data and/or address information to or from the A
and B buses. Information transfer between the A, B, and AB buses is inverting for the ’BCT2423A and noninverting
for the ’BCT2424A.
ABENL
AB Bus Output Enable, Least Significant Byte. This active-low input is used to enable the AB7 – AB0 outputs. When
this input is high, the AB7 – AB0 outputs are in the high-impedance state allowing for data input.
ABENM
AB Bus Latch Enable, Most Significant Byte. This active-low input is used to enable the AB15–AB8 outputs. When
this input is high, the AB15 –AB8 outputs are in the high-impedance state allowing for data input.
ABLEA
AB Bus Latch Enable to A Bus. This active-low input is used to control the latch that holds data received from the
AB bus (AB15 –AB0) to be transferred to the A bus (A15 –A0). When ABLEA is low, the latch is transparent. When
ABLEA transitions to the high level, the data present at the AB15 – AB0 inputs is latched, and it remains latched while
ABLEA is high.
ABLEB
AB Bus Latch Enable to B Bus. This active-low input is used to control the latch that holds data received from the
AB bus (AB15 –AB0) to be transferred to the B bus (B15–B0). When ABLEB is low, the latch is transparent. When
ABLEB transitions to the high level, the data present at the AB15 – AB0 inputs is latched, and it remains latched while
ABLEB is high.
A / BSEL
A / B Select Control. This input controls the A / B multiplexer. When the input is low, the A15 – A0 is selected as input
to the AB15 – AB0 outputs. When the input is high, B15 – B0 is selected as input to the AB15 – AB0 outputs.
AENL
A Bus Output Enable, Least Significant Byte. This active-low input is used to enable the A7 – A0 outputs. When this
input is high, the A7 – A0 outputs are in the high-impedance state allowing for data input.
AENM
A Bus Output Enable, Most Significant Byte. This active-low input is used to enable the A15 – A8 outputs. When this
input is high, the A15 – A8 outputs are in the high-impedance state allowing for data input.
ALE
A Bus Latch Enable. This active-low input is used to control the latch that holds data received from the A bus
(A15 – A0). When ALE is low, that latch is transparent. When ALE transitions to the high level, the data present at
the A15 – A0 inputs is latched and remains latched while ALE is high.
B 15 – B 0
B Bus. This 16-bit I/O port allows for transmission of data and/or address information to or from the AB bus.
Information transfer between the B bus and the AB bus is inverting for the ’BCT2423A and noninverting for the
’BCT2424A.
BENL
B Bus Output Enable, Least Significant Byte. This active-low input is used to enable the B7 – B0 outputs. When this
input is high, the B7 – B0 outputs are in the high-impedance state allowing for data input.
BENM
B Bus Output Enable, Most Significant Byte. This active-low input is used to enable the B15 – B8 outputs. When this
input is high, the B15 – B8 outputs are in the high-impedance state allowing for data input.
BLE
B Bus Latch Enable. This active-low input is used to control the latch that holds data received from the B bus
(B15 – B0). When BLE is low, that latch is transparent. When BLE transitions to the high level, that data present at
the B15 – B0 inputs is latched and remains latched while BLE is high.
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7
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
Function Tables
DIRECTION A OR B TO AB
OUTPUTS
INPUTS
Ax
Bx
H
L
’BCT2423A
AB 15–8
’BCT2424A
ALE
BLE
A/ BSEL
ABENM
ABENL
AB 7–0
AB 15–8
AB 7–0
X
L
X
L
L
L
L
X
L
X
L
L
L
H
L
X
X
H
X
L
L
L
X
H
X
L
H
L
L
AB0
L
AB0
H
X
L
X
L
H
L
L
H
L
X
X
X
H
H
L
L
AB0
AB0
X
X
X
X
X
L
L
Active
Active
Active
Active
X
X
X
X
X
L
H
Active
Z
Active
Z
X
X
X
X
X
H
L
Z
Active
Z
Active
X
X
X
X
X
H
H
Z
Z
Z
Z
H
DIRECTION AB TO A OR B
INPUTS
OUTPUTS
ABLEA
ABLEB
AENL†
AENM†
H
L
L
L
ABx
ABx
BENL†
BENM†
Ax
Bx
Ax
Bx
L
L
L
H
H
’BCT2423A
’BCT2424A
L
L
L
L
L
H
H
L
L
H
L
H
L
L
L
H
L
L
H
L
L
H
B0
B0
L
B0
B0
H
H
L
L
L
A0
H
H
L
L
L
A0
A0
L
L
H
A0
L
X
H
H
L
L
X
X
X
L
L
A0
Active
B0
Active
A0
Active
B0
Active
X
X
X
L
H
Active
Z
Active
Z
X
X
X
H
L
Z
Active
Z
Active
X
X
X
H
H
Z
Z
Z
Z
H = high level, L = low level, X = irrelevant, Z = high impedance.
A0, B0, AB0, AB0 = no change since the controlling latch enable went high
† The least significant bytes (A7-A0 and B7-B0) and the most significant bytes (A15-A8 and B15-B8) can be independently enabled and
disabled, as was illustrated for the AB and AB bytes in the upper function table.
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SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
absolute maximum ratings over operating free-air temperature range(unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (all inputs and I / O ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65° to 150° C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VCC
VIH
Supply voltage
VIL
Low-level input voltage
IOH
High level output current
High-level
Ax, Bx outputs
ABx or ABx outputs
–15
IOL
Low level output current
Low-level
Ax, Bx outputs
ABx or ABx outputs
24
tw
Pulse duration
tsu
th
Setup time
Data before xLEx ↑
Hold time
Data after xLEx ↑
TA
Operating free-air temperature
High-level input voltage
2
V
0.8
–15
48
ABLEA, ABLEB high or low
12.5
ALE, BLE high or low
12.5
V
mA
mA
ns
10
ns
2
ns
0
70
°C
electrical characteristics over recommended operating free-air temperature range
PARAMETER
VIK
TEST CONDITIONS
TYP†
MAX
UNIT
–1.2
V
VCC = 4.75 V,
VCC = 4.75 V,
II = –18 mA
IOH = – 400 mA
VCC = 4.75 V,
VCC = 4.75 V,
IOH = – 3 mA
IOH = –15 mA
AX, Bx outputs
VCC = 4.75 V,
VCC = 4.75 V,
IOL = 12 mA
IOL = 24 mA
0.25
0.4
0.35
0.5
AX, Bx outputs
VCC = 4.75 V,
VCC = 4.75 V,
IOL = 24 mA
IOL = 48 mA
0.25
0.4
0.35
0.5
VCC = 5.25 V,
VI = 5.5 V
100
mA
20
–100
mA
–200
mA
–225
mA
VOH
VOL
II
IIH‡
VCC = 5.25 V,
VI = 2.7 V
IIL‡
IOS§
VCC = 5.25 V,
VCC = 5.25 V,
VI = 0.4 V
V0 = 0
VCC = 5.25 V,
VIH = 3 V,
VIL = 0.5 V,
Outputs open
ICC
MIN
Enabled
Disabled
VCC – 1.5
2.8
3.6
V
2
– 60
110
170
20
40
V
mA
† All typical values are at VCC = 5 V, TA = 25 °C.
‡ For I/O ports, the parameter IIH and IIL include the offstate output current.
§ Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
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SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
tpd
tpd
ABx, ABx
ABx, ABx
tpd
tpd
TYP†
MAX
Ax
8
12
ns
Bx
8
12
ns
Ax
ABx, ABx
9
12
ns
Bx
ABx, ABx
9
12
ns
tpd
tpd
ALE ↓
ABx, ABx
10
13
ns
BLE ↓
ABx, ABx
10
13
ns
tpd
tpd
ABLEA ↓
Ax
8
12
ns
ABLEB ↓
Bx
8
12
ns
tpd
A / BSEL
ABx, ABx
8
12
ns
ten
AENM,
AENL
Ax
10
13
ns
ten
BENM,
BENL
Bx
10
13
ns
ten
ABENM,
ABENL
ABx, ABx
10
13
ns
tdis
AENM,
AENL
Ax
5
10
ns
tdis
BENM,
BENL
Bx
5
10
ns
tdis
ABENM,
ABENL
ABx, ABx
5
10
ns
PARAMETER
TEST CONDITIONS ‡
VCC = 4.75 V to 5.25 V,
CL = 50 pF,
R1 = 500 Ω, R2 = 500 Ω,
TA = MIN to MAX
† All typical values are at VCC = 5 V, TA = 25 °C.
‡ See Parameter Measurement Information for load circuit and voltage waveforms.
10
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MIN
UNIT
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
PARAMETER MEASUREMENT INFORMATION
7V
SWITCH POSITION TABLE
RL = R 1 = R 2
TEST
S1
tPLH
tPHL
tPZH
tPZL
Open
Open
Open
Closed
From Output
Under Test
tPHZ
tPLZ
Open
Closed
CL
(see Note A)
S1
R1
Test
Point
R2
LOAD CIRCUIT
3.5 V
High-Level
Pulse
3.5 V
Timing
Input
1.3 V
1.3 V
0.3 V
0.3 V
tw
th
tsu
1.3 V
3.5 V
3.5 V
Data
Input
Low-Level
Input
1.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
3.5 V
1.3 V
Input
1.3 V
Output Control
(Low-level
Enabling)
0.3 V
tPLZ
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
Out-of-Phase
Output
1.3 V
0.3 V
tPZL
tPHL
tPLH
1.3 V
1.3 V
VOL
1.3 V
VOL
tPZH
VOH
1.3 V
≈ 3.5 V
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPHZ
0.3 V
VOH
1.3 V
0.3 V
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLED TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Wafeform 1 is for an output with internal conditions such that the output is low except when disabled by the current control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1
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11
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
APPLICATION INFORMATION
ALE ’ACT 4503
MA 0 – MA 9
ACR
AS
(see Note A)
R/W
M / IO
ACW
CS
A 3 – A 12
RA 0 – RA 9
A 13 – A 22
CA 0 – CA 9
RAS 0
CAS 0
BANK 0
1 M X 16 BIT
A 0 – A 9 DRAMs
A 3 – A 22 ADDR BUS
A 2 (BANK SELECT
RENO
RDY
READY
RAS 0
RAS 1
CAS 0 Lower
CAS 1 Upper
A 1 (BYTE
SELECT)
Byte
Strobe
A 2 (BYTE
SELECT)
W
D
Q
’BCT 2424
AENM
A 0 – A 15
AENL
ALE
B 0 – B 15
BANK 1
1 M X 16 BIT
A 0 – A 9 DRAMs
ABLEA
RAS 1
ABENM
D 0 – D 15
DATA BUS
CAS 0
CAS 1
Lower
Byte
Upper
Strobe
AB 0 – AB 15
D
ABENL
W
Q
ABLEB
ABSEL
BLE
BENM
BENL
NOTE A: The value of this delay element is dependent on the speed of the microprocessor.
Figure 2. Typical Memory Interleave Application
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74BCT2423AFN
OBSOLETE
PLCC
FN
68
TBD
Call TI
Call TI
SN74BCT2424AFN
OBSOLETE
PLCC
FN
68
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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Addendum-Page 1
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