SCAS038A − D2957, JULY 1987 − REVISED APRIL 1993
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Eight D-Type Flip-Flops in a Single Package
3-State Bus Driving Inverting Outputs
Full Parallel Access for Loading
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin VCC and GND Configurations to
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic SmallOutline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
54ACT11534 . . . JT PACKAGE
74ACT11534 . . . DW OR NT PACKAGE
(TOP VIEW)
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
OC
1D
2D
3D
4D
VCC
VCC
5D
6D
7D
8D
CLK
54ACT11534 . . . FK PACKAGE
(TOP VIEW)
3D
4D
VCC
NC
VCC
5D
6D
description
These eight flip-flops feature 3-state outputs
designed for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
5
2D
1D
OC
NC
1Q
2Q
3Q
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
7D
8D
CLK
NC
8Q
7Q
6Q
4Q
GND
GND
NC
GND
GND
5Q
The eight flip-flops of the ′ACT11534 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
complement of the logic levels at the D inputs. The
′ACT11534 is functionally equivalent to the
′ACT11373 except for having inverted outputs.
4
An output-control input (OC) is used to place the
eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly.
The
high-impedance third state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components. The output control (OC)
does not affect the internal operations of the
flip-flops. Old data can be retained, or new data
can be entered while the outputs are in the
high-impedance state.
NC − No internal connection
FUNCTION TABLE
(each flip-flop)
INPUTS
OC
CLK
D
OUTPUT
Q
L
L
L
H
↑
↑
L
X
H
L
X
X
L
H
Q0
Z
The 54ACT11534 is characterized for operation
over the full military temperature range of − 55°C
to 125°C. The 74ACT11534 is characterized for
operation from − 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2 #++ )#!#"($(!%-
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•
2−1
SCAS038A − D2957, JULY 1987 − REVISED APRIL 1993
logic symbol†
OC
CLK
1D
2D
3D
4D
5D
6D
7D
8D
24
13
23
22
logic diagram (positive logic)
OC
EN
CLK
C1
1D
1
2
21
3
20
4
17
9
16
10
15
11
14
12
1Q
1D
2Q
3Q
2D
4Q
24
13
23
22
5Q
6Q
3D
7Q
8Q
4D
21
20
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
5D
6D
7D
8D
17
16
15
14
C1
1
1D
C1
2
1D
C1
3
1D
C1
4
1D
C1
9
1D
C1
10
1D
C1
11
1D
C1
1D
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2−2
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SCAS038A − D2957, JULY 1987 − REVISED APRIL 1993
recommended operating conditions
54ACT11534
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
Dt /Dv
Low-level output current
TA
Operating free-air temperature
High-level input voltage
74ACT11534
2
2
0.8
Input transition rise or fall rate
UNIT
V
V
0.8
V
VCC
VCC
V
−24
−24
mA
24
24
mA
VCC
VCC
0
0
V
0
10
0
10
ns/ V
−55
125
− 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = − 50 mA
A
VOH
IOH = − 24 mA
IOH = − 50 mA{
IOH = − 75 mA{
IOL = 50 mA
A
VOL
IOL = 24 mA
TA = 25°C
TYP
MAX
54ACT11534
74ACT11534
VCC
MIN
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
5.5 V
MIN
MAX
MIN
MAX
UNIT
V
3.85
5.5 V
3.85
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA{
IOL = 75 mA{
5.5 V
IOZ
II
VO = VCC or GND
VI = VCC or GND
5.5 V
± 0.5
± 10
±5
mA
5.5 V
± 0.1
±1
±1
mA
ICC
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
8
160
80
mA
5.5 V
0.9
1
1
mA
DICC}
Ci
VI = VCC or GND
VO = VCC or GND
1.65
5.5 V
1.65
5V
4
Co
5V
10
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
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pF
pF
2−3
SCAS038A − D2957, JULY 1987 − REVISED APRIL 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
54ACT11534
MAX
MIN
MAX
0
55
0
55
UNIT
fclock
tw
Clock frequency
0
Pulse duration, CLK low or CLK high
9
9
9
ns
tsu
th
Setup time, data before CLK ↑
3
3
3
ns
5.5
5.5
5.5
ns
Hold time, data after CLK ↑
55
74ACT11534
MIN
MHz
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
CLK
Any Q
OC
Any Q
OC
Any Q
MIN
TA = 25°C
TYP
MAX
54ACT11534
MIN
74ACT11534
MAX
MIN
55
MAX
55
70
1.5
8.5
12.7
1.5
15.7
1.5
55
14.5
1.5
8.5
13.3
1.5
16.3
1.5
15
1.5
7.5
12
1.5
14.2
1.5
13.3
1.5
7.5
12.2
1.5
14.5
1.5
13.5
1.5
11
12.9
1.5
13.9
1.5
13.5
1.5
8
11.2
1.5
12.5
1.5
12
UNIT
MHz
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
2−4
Power dissipation capacitance per flip-flop
Outputs disabled
•
UNIT
92
CL = 50 pF,
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•
TYP
f = 1 MHz
82
pF
SCAS038A − D2957, JULY 1987 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
3V
Timing Input
(see Note B)
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
1.5 V
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
50% VCC
3V
Output
Waveform 2
S1 at GND
(see Note C)
VOH
50% VCC
VOL
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
tPLH
tPHL
Out-of-Phase
Output
VOLTAGE WAVEFORMS
50% VCC
20% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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•
2−5
SCAS038A − D2957, JULY 1987 − REVISED APRIL 1993
2−6
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