IDT MPC9446AC

3.3V and 2.5V, LVCMOS Clock Fanout Buffer
DATASHEET
NRND – Not Recommend for New Designs
The MPC9446 is a 2.5 V and 3.3 V compatible 1:10 clock distribution buffer designed
for low-voltage mid-range to high-performance telecom, networking and computing
applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for mixed-voltage
applications. The MPC9446 offers 10 low-skew outputs and 2 selectable inputs for clock
redundancy. The outputs are configurable and support 1:1 and 1:2 output to input
frequency ratios. The MPC9446 is specified for the extended temperature range of –40C
to 85C.
Features
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MPC9446
NRND
Configurable 10 outputs LVCMOS clock distribution buffer
Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply
Wide range output clock frequency up to 250 MHz
Designed for mid-range to high-performance telecom, networking
and computer applications
Supports applications requiring clock redundancy
Maximum output skew of 200 ps (150 ps within one bank)
Selectable output configurations per output bank
Tristable outputs
32-lead LQFP package, Pb-free
Ambient operating temperature range of –40 to 85C
MPC9446
LOW VOLTAGE SINGLE OR
DUAL SUPPLY 2.5 V AND 3.3 V
LVCMOS CLOCK
DISTRIBUTION BUFFER
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
Functional Description
The MPC9446 is a full static fanout buffer design supporting clock frequencies up to 250
MHz. The signals are generated and retimed on-chip to ensure minimal skew between the
three output banks. Two independent LVCMOS compatible clock inputs are available. This
feature supports redundant clock sources or the addition of a test clock into the system design. Each of the three output banks can be
individually supplied by 2.5 V or 3.3 V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9446 can be
rese,t and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting MR/OE will enable the outputs.
All inputs accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 
transmission lines. Please consult the MPC9456 specification for a 1:10 mixed voltage buffer with LVPECL compatible inputs. For series
terminated transmission lines, each of the MPC9446 outputs can drive one or two traces giving the devices an effective fanout of 1:20.
The device is packaged in a 7x7 mm2 32-lead LQFP package.
MPC9446 REVISION 5 DECEMBER 21, 2012
1
©2012 Integrated Device Technology, Inc.
MPC9446 Data Sheet
3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER
VCC
25k
CCLK0
Bank A
VCC
25k
CCLK1
CCLK_SEL
0
CLK
0
1
CLK  2
1
QA0
QA1
25k
0
QA2
Bank B
QB0
QB1
1
QB2
QC0
Bank C
FSELA
25k
FSELB
25k
FSELC
0
QC1
1
QC2
QC3
25k
MR/OE
25k
VCCC
VCCB
QB2
GND
QB1
VCCB
QB0
GND
Figure 1. MPC9446 Logic Diagram
VCCB is internally connected to VCC
24
23
22
21
20
19
18
17
VCCA
25
16
QC3
QA2
26
15
GND
GND
27
14
QC2
QA1
28
13
VCCC
VCCA
29
12
QC1
QA0
30
11
GND
GND
31
10
QC0
MR/OE
32
9
VCCC
VCC
CCLK0
CCLK1
5
6
7
8
GND
4
FSELC
3
FSELB
2
FSELA
1
CCLK_SEL
MPC9446
Figure 2. Pinout: 32-Lead Package Pinout (Top View)
MPC9446 REVISION 5 DECEMBER 21, 2012
2
©2012 Integrated Device Technology, Inc.
MPC9446 Data Sheet
3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER
Table 1. Pin Configuration
Pin
I/O
Type
Function
CCLK0,1
Input
LVCMOS
LVCMOS clock inputs
FSELA, FSELB, FSELC
Input
LVCMOS
Output bank divide select input
MR/OE
Input
LVCMOS
Internal reset and output (high impedance) control
Supply
Negative voltage supply (GND)
Supply
Positive voltage supply for output banks
GND
VCCA, VCCB
(1),
VCCC
VCC
Supply
Positive voltage supply for core (VCC)
QA0 – QA2
Output
LVCMOS
Bank A outputs
QB0 – QB2
Output
LVCMOS
Bank B outputs
QC0 – QC3
Output
LVCMOS
Bank C outputs
1. VCCB is internally connected to VCC.
Table 2. Supported Single and Dual Supply Configurations
VCC(1)
VCCA(2)
VCCB(3)
VCCC(4)
GND
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
0V
Mixed Voltage Supply
3.3 V
3.3 V or 2.5 V
3.3 V
3.3 V or 2.5 V
0V
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
0V
Supply Voltage Configuration
1.
2.
3.
4.
VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels.
VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels.
VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC.
VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels.
Table 3. Function Table (Controls)
Control
Default
0
1
CCLK_SEL
0
CCLK0
CCLK1
FSELA
0
fQA0:2 = fREF
fQA0:2 = fREF  2
FSELB
0
fQB0:2 = fREF
fQB0:2 = fREF  2
FSELC
0
fQC0:3 = fREF
fQC0:3 = fREF  2
MR/OE
0
Outputs enabled
Internal reset outputs disabled (tristate)
Table 4. Absolute Maximum Ratings(1)
Symbol
Min
Max
Unit
VCC
Supply Voltage
–0.3
3.6
V
VIN
DC Input Voltage
–0.3
VCC+0.3
V
DC Output Voltage
–0.3
VCC+0.3
V
DC Input Current
20
mA
DC Output Current
50
mA
125
C
VOUT
IIN
IOUT
TS
Characteristics
Storage Temperature
–65
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
MPC9446 REVISION 5 DECEMBER 21, 2012
3
©2012 Integrated Device Technology, Inc.
MPC9446 Data Sheet
3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER
Table 5. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
VCC  2
VTT
Output Termination Voltage
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
LU
Latch-Up Immunity
200
mA
CPD
Power Dissipation Capacitance
10
pF
CIN
Input Capacitance
4.0
pF
Condition
V
Per output
Table 6. DC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3 V ± 5%, TA = –40°C to +85°C)
Symbol
Characteristics
Min
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
–0.3
IIN
Input Current(1)
VOH
Output High Voltage
VOL
Output Low Voltage
ZOUT
Output Impedance
ICCQ
(3)
Typ
Max
Unit
VCC + 0.3
V
LVCMOS
0.8
V
LVCMOS
200
A
VIN = GND or VIN = VCC
V
IOH = –24 mA(2)
V
V
IOL = 24 mA(2)
IOL = 12 mA
2.4
0.55
0.30

14 – 17
Maximum Quiescent Supply Current
Condition
2.0
mA
All VCC Pins
1. Input pull-up / pull-down resistors influence input current.
2. The MPC9446 is capable of driving 50  transmission lines on the incident edge. Each output drives one 50  parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series terminated transmission lines.
3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 7. AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3 V ± 5%, TA = –40°C to +85°C)(1)
Symbol
fref
Characteristics
Min
Input Frequency
fMAX
Maximum Output Frequency
tP, REF
Reference Input Pulse Width
tr, tf
CCLK Input Rise/Fall Time
tPLH
tPHL
Propagation Delay
1 output
2 output
Typ
Max
0
250
MHz
0
0
250(2)
125
MHz
MHz
1.4
CCLK0,1 to any Q
CCLK0,1 to any Q
Unit
(2)
Condition
FSELx = 0
FSELx = 1
ns
2.2
2.2
2.8
2.8
1.0(3)
ns
4.45
4.2
ns
ns
0.8 to 2.0 V
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tsk(O)
Output-to-Output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
200
350
ps
ps
ps
tsk(PP)
Device-to-Device Skew
2.25
ns
tSK(P)
Output Pulse Skew(4)
200
ps
DCQ
Output Duty Cycle
53
55
%
%
DCREF = 50%
DCREF = 25%–75%
tr, tf
Output Rise/Fall Time
1.0
ns
0.55 to 2.4 V
1 output
2 output
47
45
50
50
0.1
1. AC characteristics apply for parallel output termination of 50  to VTT.
2. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
4. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency
dependent: DCQ = (0.5 ± tSK(P) • fOUT). For example at fOUT = 125 MHz the output duty cycle limit is 50% ± 2.5%.
MPC9446 REVISION 5 DECEMBER 21, 2012
4
©2012 Integrated Device Technology, Inc.
MPC9446 Data Sheet
3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER
Table 8. DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40°C to +85°C)
Symbol
Max
Unit
VIH
Input High Voltage
Characteristics
Min
1.7
VCC + 0.3
V
LVCMOS
0.7
V
LVCMOS
V
IOH = –15 mA(1)
V
IOL = 15 mA
VIL
Input Low Voltage
–0.3
VOH
Output High Voltage
1.8
VOL
Output Low Voltage
ZOUT
Output Impedance
IIN
ICCQ(3)
Typ
0.6
17 – 20(2)
Input Current(2)
Condition

200
A
VIN = GND or VIN = VCC
2.0
mA
All VCC Pins
Maximum Quiescent Supply Current
1. The MPC9446 is capable of driving 50  transmission lines on the incident edge. Each output drives one 50  parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series terminated transmission lines per
output.
2. Input pull-up / pull-down resistors influence input current.
3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40°C to +85°C)(1)
Symbol
fref
Characteristics
Min
Input Frequency
fMAX
Maximum Output Frequency
tP, REF
Reference Input Pulse Width
tr, tf
CCLK Input Rise/Fall Time
tPLH
tPHL
Propagation Delay
tPLZ, HZ
Output Disable Time
tPZL, LZ
1 output
2 output
Typ
Max
250
(2)
MHz
0
0
250(2)
125
MHz
MHz
1.4
CCLK0,1 to any Q
CCLK0,1 to any Q
Unit
0
Condition
FSELx = 0
FSELx = 1
ns
1.0(3)
ns
5.6
5.5
ns
ns
10
ns
2.6
2.6
0.7 to 1.7 V
Output Enable Time
10
ns
tsk(O)
Output-to-Output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
200
350
ps
ps
ps
tsk(PP)
Device-to-Device Skew
3.0
ns
tSK(P)
Output Pulse Skew(4)
200
ps
DCQ
Output Duty Cycle
55
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
1.0
ns
0.6 to 1.8 V
1 or 2 output
45
50
0.1
1. AC characteristics apply for parallel output termination of 50  to VTT.
2. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
4. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency
dependent: DCQ = (0.5 ± tSK(P) • fOUT). For example at fOUT = 125 MHz the output duty cycle limit is 50% ± 2.5%.
Table 10. AC Characteristics (VCC = 3.3 V + 5%, VCCA, VCCB, VCCC = 2.5 V + 5% or 3.3 V + 5%, TA = –40°C to +85°C)(1) (2)
Symbol
Characteristics
tsk(O)
Output-to-Output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
tsk(PP)
Device-to-Device Skew
tPLH,HL
Propagation Delay
tSK(P)
Output Pulse Skew(3)
DCQ
Output Duty Cycle
Min
Typ
CCLK0,1 to any Q
1 or 2 output
Max
Unit
150
250
350
ps
ps
ps
2.5
ns
250
ps
55
%
Condition
See 3.3 V Table
45
50
DCREF = 50%
1. AC characteristics apply for parallel output termination of 50  to VTT.
2. For all other AC specifications, refer to 2.5 V or 3.3 V tables according to the supply voltage of the output bank.
3. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency
dependent: DCQ = (0.5 ± tSK(P) • fOUT).
MPC9446 REVISION 5 DECEMBER 21, 2012
5
©2012 Integrated Device Technology, Inc.
MPC9446 Data Sheet
3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER
APPLICATIONS INFORMATION
Driving Transmission Lines
The MPC9446 clock driver was designed to drive highspeed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20  the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50  resistance to VCC2.
This technique draws a fairly high level of DC current, and
thus, only a single terminated line can be driven by each
output of the MPC9446 clock driver. For the series terminated
case, however, there is no DC current draw; thus, the outputs
can drive multiple series terminated lines. Figure 3 illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9446 clock driver is effectively doubled
due to its capability to drive multiple lines.
the line impedances. The voltage wave launched down the
two lines will equal:
VL =
Z0 =
RS =
R0 =
VL =
=
VS (Z0  (RS + R0 + Z0))
50  || 50 
36  || 36 
14 
3.0 (25  (18 + 14 + 25)
1.31 V
At the load end, the voltage will double, due to the near
unity reflection coefficient, to 2.5 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
3.0
2.5
OutA
tD = 3.8956
OutB
tD = 3.9386
Voltage (V)
2.0
In
1.5
1.0
MPC9446
Output
Buffer
IN
14
0.5
RS = 36
ZO = 50
OutA
0
2
MPC9446
Output
Buffer
IN
4
6
8
Time (ns)
10
12
14
Figure 4. Single versus Dual Waveforms
RS = 36
ZO = 50
RS = 36
ZO = 50
Since this step is well above the threshold region, it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in Figure 5 should be used. In this case, the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
OutB0
14
OutB1
Figure 3. Single versus Dual Transmission Lines
The waveform plots in Figure 4 show the simulation
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9446 output buffer
is more than sufficient to drive 50  transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9446. The output waveform
in Figure 4 shows a step in the waveform. This step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36  series resistor plus the
output impedance does not match the parallel combination of
MPC9446 REVISION 5 DECEMBER 21, 2012
MPC9446
Output
Buffer
RS = 22
ZO = 50
RS = 22
ZO = 50
14
14  + 22  || 22  = 50  || 50 
25 = 25 
Figure 5. Optimized Dual Line Termination
6
©2012 Integrated Device Technology, Inc.
MPC9446 Data Sheet
3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER
MPC9446 DUT
Pulse
Generator
Z = 50
ZO = 50 
ZO = 50
RT = 50
RT = 50
VTT
VTT
Figure 6. CCLK0, 1 MPC9446 AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
tF
VCC = 3.3V
VCC = 2.5V
2.4
1.8V
0.55
0.6V
VCC
VCC2
CCLK
GND
VCC
VCC2
Qx
tR
GND
t(LH)
t(HL)
Figure 8. Propagation Delay (tPD) Test Reference
Figure 7. Output Transition Time Test Reference
VCC
VCC
CCLK
VCC2
VCC2
GND
GND
VCC
VCC2
VCC
VCC2
QX
GND
tSK(LH)
GND
tSK(HL)
t(LH)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any two similar delay paths
within a single device.
t(HL)
tSK(P) = | tPLH – tPHL |
Figure 9. Output-to-Output Skew tSK(LH, HL)
Figure 10. Output Pulse Skew (tSK(P)) Test Reference
VCC
VCC2
GND
tP
T0
DC = tP/T0 x 100%
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
Figure 11. Output Duty Cycle (DC)
MPC9446 REVISION 5 DECEMBER 21, 2012
7
©2012 Integrated Device Technology, Inc.
MPC9446 Data Sheet
3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER
PACKAGE DIMENSIONS
PAGE 1 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC9446 REVISION 5 DECEMBER 21, 2012
8
©2012 Integrated Device Technology, Inc.
MPC9446 Data Sheet
3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER
PACKAGE DIMENSIONS
PAGE 2 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC9446 REVISION 5 DECEMBER 21, 2012
9
©2012 Integrated Device Technology, Inc.
MPC9446 Data Sheet
3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER
PACKAGE DIMENSIONS
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC9446 REVISION 5 DECEMBER 21, 2012
10
PAGE 3 OF 3
©2012 Integrated Device Technology, Inc.
MPC9446 Data Sheet
3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER
Revision History Sheet
Rev
5
Table
Page
1
Description of Change
Date
NRND – Not Recommend for New Designs
MPC9446 REVISION 5 DECEMBER 21, 2012
11
12/21/12
©2012 Integrated Device Technology, Inc.
MPC9446 Data Sheet
3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER
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