TI TM2EJ64DPN

SMMS685 − AUGUST 1997
D
D
D
D
− TM2xJ64xPN-xx . . . 2 097 152 × 64 Bits
Single 3.3-V Power Supply
(±10% Tolerance)
JEDEC 144-Pin Small Outline Dual-In-Line
Memory Module (SODIMM) Without Buffer
for Use With Socket
TM2xJ64xPN-xx — Utilizes Eight 16M-Bit
(2M × 8-Bit) Dynamic RAMs in TSOPs
Performance ranges
’2xJ64xPN-50
’2xJ64xPN-60
’2xJ64xPN-70
ACCESS ACCESS ACCESS
TIME
TIME
TIME
tRAC
tCAC
tAA
MAX
MAX
MAX
50 ns
13 ns
25 ns
60 ns
15 ns
30 ns
70 ns
18 ns
35 ns
EDO
CYCLE
tHPC
MIN
20 ns
25 ns
30 ns
D High-Speed, Low-Noise LVTTL Interface
D Long Refresh Period:
D
D
D
D
D
D
− TM2EJ64DPN: 32 ms (2 048 cycles)
− TM2EJ64EPN: 64 ms (4 096 cycles)
Low-Power, Battery-Backup Refresh
Available:
− TM2FJ64DPN: 128 ms (2048 cycles)
− TM2FJ64EPN: 128 ms (4 096 cycles)
3-State Output
Extended-Data-Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
Serial Presence-Detect (SPD) Using
EEPROM
Ambient Temperature Range
0°C to 70°C
Gold-Plated Contacts
description
The TM2EJ64DPN is a 16M-byte, 144-pin, small outline dual-in-line memory module (SODIMM). The SODIMM
is composed of eight TMS427809A, 2 097 152 × 8-bit 2K-refresh EDO dynamic random-access memories
(DRAMs), each in a 400-mil, 28-pin plastic thin small-outline package (TSOP) (DGC suffix) mounted on a
substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS894).
The TM2EJ64EPN is an 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809A,
2 097 152 × 8-bit 4K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a
substrate with decoupling capacitors. See the TMS426809A data sheet (literature number SMKS894).
The TM2FJ64DPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS427809AP,
2 097 152 × 8-bit 2K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP
(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809AP data sheet (literature
number SMKS894).
The TM2FJ64EPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809AP,
2 097 152 × 8-bit 4K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP
(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS426809AP data sheet (literature
number SMKS894).
operation
The TM2xJ64xPN operates as eight TMS42x809A/Ps, connected as shown in the functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
!" #$%&'()*#&$ +&$+,'$- .'&/0+*- #$ *1, %&'()*#2, &'
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POST OFFICE BOX 1443
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1
PRODUCT PREVIEW
D Organization
SMMS685 − AUGUST 1997
DUAL-IN-LINE MEMORY MODULE
( TOP VIEW )
TM2xJ64xPN
( SIDE VIEW )
PIN NOMENCLATURE
A[0:11]†
A[0:9]
DQ[0:63]
CAS[0:7]
RAS0
WE0
OE0
SDA
SCL
NC
VDD
VSS
1
Row Address Inputs
Column Address Inputs
Data In / Data Out
Column-Address Strobe
Row-Address Strobe
Write Enable
Output Enable
Serial PD Address / Data
Serial PD Clock
No-Connect Pin
3.3-V Supply
Ground
† A11 is NC for TM2xJ64DPN
PRODUCT PREVIEW
59
61
143
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMMS685 − AUGUST 1997
Pin Assignments
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN
NAME
NO.
PIN
NAME
NO.
1
VSS
VSS
37
DQ8
73
OE
109
A9
38
DQ40
74
NC
110
NC
3
DQ0
39
DQ9
75
A10
DQ32
40
DQ41
76
VSS
VSS
111
4
112
NC
5
DQ1
41
DQ10
77
NC
113
6
DQ33
42
DQ42
78
NC
114
VDD
VDD
7
DQ2
43
DQ11
79
NC
115
CAS2
8
DQ34
44
DQ43
80
NC
116
CAS6
117
CAS3
118
CAS7
2
NO.
PIN
NAME
NAME
9
DQ3
45
DQ35
46
VDD
VDD
81
10
82
VDD
VDD
11
VDD
VDD
47
DQ12
83
DQ16
119
12
48
DQ44
84
DQ48
120
VSS
VSS
13
DQ4
49
DQ13
85
DQ17
121
DQ24
14
DQ36
50
DQ45
86
DQ49
122
DQ56
15
DQ5
51
DQ14
87
DQ18
123
DQ25
16
DQ37
52
DQ46
88
DQ50
124
DQ57
17
DQ6
53
DQ15
89
DQ19
125
DQ26
18
DQ38
54
DQ47
90
DQ51
126
DQ58
19
DQ7
55
DQ27
56
92
VSS
VSS
127
DQ39
VSS
VSS
91
20
128
DQ59
21
VSS
VSS
57
NC
93
DQ20
129
22
58
NC
94
DQ52
130
VDD
VDD
23
CAS0
59
NC
95
DQ21
131
DQ28
24
CAS4
60
NC
96
DQ53
132
DQ60
25
CAS1
61
NC
97
DQ22
133
DQ29
26
CAS5
62
NC
98
DQ54
134
DQ61
27
VDD
VDD
63
DQ23
135
DQ30
64
VDD
VDD
99
28
100
DQ55
136
DQ62
29
A0
65
NC
101
DQ31
A3
66
NC
102
VDD
VDD
137
30
138
DQ63
31
A1
67
WE0
103
A6
139
32
A4
68
NC
104
A7
140
VSS
VSS
33
A2
69
RAS0
105
A8
141
SDA
34
A5
70
NC
106
A11
142
SCL
35
VSS
VSS
71
NC
107
143
72
NC
108
VSS
VSS
VDD
VDD
36
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144
PRODUCT PREVIEW
PIN
NO.
3
SMMS685 − AUGUST 1997
small outline dual-in-line memory module and components
The small−outline dual-in-line memory module and components include:
D PC substrate: 1,10 " 0,1 mm (0.04 inch) nominal thickness
D Bypass capacitors: Multilayer ceramic
D Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM2xJ64xPN
RAS0
RAS0
WE0
OE0
WE0
OE0
CAS0
DQ[0:7]
PRODUCT PREVIEW
CAS1
DQ[8:15]
CAS2
DQ[16:23]
CAS3
DQ[24:31]
CAS OE W RAS
CAS4
DQ[0:7] U0
DQ[32:39]
CAS OE W RAS
CAS5
DQ[0:7] U1
DQ[40:47]
CAS6
CAS OE W RAS
DQ[48:55]
DQ[0:7] U2
CAS7
CAS OE W RAS
DQ[56:63]
DQ[0:7] U3
CAS
OE W RAS
DQ[0:7] UB0
CAS
OE W RAS
DQ[0:7] UB1
CAS
OE W RAS
DQ[0:7] UB2
CAS
OE W RAS
DQ[0:7] UB3
TM2xJ64DPN:
A[0 : 10]
SPD EEPROM
A[0 :10] : U[0: 3], UB[0: 3]
SCL
A0
A1
A2
SDA
TM2xJ64EPN:
A[0: 11]
A[0: 11] : U[0: 3], UB[0: 3]
VSS
VDD
VSS
4
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
U[0:3], UB[0:3]
Two 0.1 µF
(minimum) per
DRAM
U[0:3], UB[0:3]
SMMS685 − AUGUST 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM2xP64DPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
TM2xP64EPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
recommended operating conditions
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
Supply voltage
VIH
VIH-SPD
High-level input voltage
2
High-level input voltage for the SPD device
2
VIL
TA
Low-level input voltage
Supply voltage
0
Ambient temperature
V
VDD + 0.3
5.5
V
V
−0.3
0.8
V
0
70
°C
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
’2xJ64xPN
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 −A10
42
pF
Ci(OE)
Input capacitance, OE0
58
pF
Ci(CAS)
Input capacitance, CASx
9
pF
Ci(RAS)
Input capacitance, RAS0
58
pF
Ci(W)
Input capacitance, WE0
58
pF
Co
Output capacitance
9
pF
Ci/o(SDA)
Input/output capacitance, SDA input
9
pF
7
pF
Ci(SPD)
Input capacitance, SA0, SA1, SA2, SCL inputs
NOTE 2: VDD = NOM supply voltage ± 10%, and the bias on pins under test is 0 V.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
5
PRODUCT PREVIEW
VDD
VSS
SMMS685 − AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM2EJ64DPN
PRODUCT PREVIEW
PARAMETER
’2EJ64DPN-50
TEST CONDITIONS†
IOH = − 2 mA
IOH = − 100 µA
IOL = 2 mA
MIN
LVTTL
High-level output
voltage
VOL
Low-level output
voltage
II
Input current
(leakage)
IOL = 100 µA
LVCMOS
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
IO
Output current
(leakage)
VDD = 3.6 V,
CASx high
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
LVCMOS
LVTTL
MIN
’2EJ64DPN-70
MAX
2.4
VDD −0.2
MIN
MAX
UNIT
2.4
VDD−0.2
V
VDD −0.2
0.4
0.4
0.4
0.2
0.2
0.2
± 10
± 10
± 10
µA
VO = 0 V to VDD,
± 10
± 10
± 10
µA
Minimum cycle
960
800
720
mA
16
16
16
mA
8
8
8
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RAS0 and CASx high
Standby current
MAX
2.4
VOH
ICC2
’2EJ64DPN-60
VIH = VDD − 0.2 V (LVCMOS),
After one memory cycle,
RAS0 and CASx high
V
ICC3‡§
Average refresh
current
(RAS-only
refresh or CBR)
VDD= 3.6 V,
Minimum cycle,
RAS0 cycling,
CASx high (RAS-only refresh),
RAS0 low after CASx low (CBR)
960
800
720
mA
ICC4‡¶
Average EDO
current
VDD = 3.6 V,
RAS0 low,
880
720
640
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS0 = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMMS685 − AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM2EJ64EPN
IOH = − 2 mA
IOH = − 100 µA
IOL = 2 mA
High-level output
voltage
VOL
Low-level output
voltage
II
Input current
(leakage)
IOL = 100 µA
LVCMOS
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
IO
Output current
(leakage)
VDD = 3.6 V,
CASx high
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
’2EJ64EPN-60
MAX
MIN
2.4
LVCMOS
’2EJ64EPN-70
MAX
2.4
VDD −0.2
LVTTL
MIN
MAX
UNIT
2.4
VDD −0.2
V
VDD−0.2
0.4
0.4
0.4
0.2
0.2
0.2
± 10
± 10
± 10
µA
VO = 0 V to VDD,
± 10
± 10
± 10
µA
Minimum cycle
720
560
480
mA
16
16
16
mA
8
8
8
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RAS0 and CASx high
Standby current
MIN
LVTTL
VOH
ICC2
’2EJ64EPN-50
TEST CONDITIONS†
VIH = VDD − 0.2 V (LVCMOS),
After one memory cycle,
RAS0 and CASx high
V
ICC3‡§
Average refresh
current
(RAS-only
refresh or CBR)
VDD = 3.6 V,
Minimum cycle,
RASx cycling,
CASx high (RAS-only refresh),
RAS0 low after CASx low (CBR)
720
560
480
mA
ICC4‡¶
Average EDO
current
VDD = 3.6 V,
RAS0 low,
800
720
640
mA
tHPC = MIN,
CASx cycling
PRODUCT PREVIEW
PARAMETER
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS0 = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
7
SMMS685 − AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperture
(unless otherwise noted) (continued)
TM2FJ64DPN
PRODUCT PREVIEW
PARAMETER
’2FJ64DPN-50
TEST CONDITIONS†
IOH = − 2 mA
IOH = − 100 µA
IOL = 2 mA
MIN
LVTTL
High-level output
voltage
VOL
Low-level output
voltage
II
Input current
(leakage)
IOL = 100 µA
LVCMOS
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
IO
Output current
(leakage)
VDD = 3.6 V,
CASx high
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
LVCMOS
LVTTL
MIN
’2FJ64DPN-70
MAX
2.4
VDD −0.2
MIN
MAX
UNIT
2.4
VDD −0.2
V
VDD −0.2
0.4
0.4
0.4
0.2
0.2
0.2
± 10
± 10
± 10
µA
VO = 0 V to VDD,
± 10
± 10
± 10
µA
Minimum cycle
960
800
720
mA
8
8
8
mA
VIH = VDD − 0.2 V (LVCMOS),
After one memory cycle,
RAS0 and CASx high
1.2
1.2
1.2
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RAS0 and CASx high
Standby current
MAX
2.4
VOH
ICC2
’2FJ64DPN-60
V
ICC3‡§
Average refresh
current
(RAS-only
refresh or CBR)
VDD= 3.6 V,
Minimum cycle,
RAS0 cycling,
CASx high (RAS-only refresh),
RAS0 low after CASx low (CBR)
960
800
720
mA
ICC4‡¶
Average EDO
current
VDD = 3.6 V,
RAS0 low,
880
720
640
mA
ICC6
Average
self-refresh
current
CASx < 0.2 V,
RAS0 < 0.2 V,
Measured after tRASS min
1.6
1.6
1.6
mA
ICC10
Average battery
back-up
operating current
(equivalent
refresh time is
128 ms), CBR
only
tRC = 31.25 µs, tRAS ≤ 300 ns
VDD − 0.2 V ≤ VIH ≤ 3.9 V,
0 V ≤ VIL ≤ 0.2 V, WE0 and OE0 =
VIH,
Address and data stable
2.8
2.8
2.8
mA
tHPC = MIN,
CASx cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS0 = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
8
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMMS685 − AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM2FJ64EPN
IOH = − 2 mA
IOH = − 100 µA
IOL = 2 mA
High-level output
voltage
VOL
Low-level output
voltage
II
Input current
(leakage)
IOL = 100 µA
LVCMOS
VDD = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VDD
IO
Output current
(leakage)
VDD = 3.6 V,
CASx high
ICC1‡§
Read- or
write-cycle
current
VDD = 3.6 V,
’2FJ64EPN-60
MAX
MIN
2.4
LVCMOS
’2FJ64EPN-70
MAX
2.4
VDD −0.2
LVTTL
MIN
MAX
UNIT
2.4
VDD −0.2
V
VDD −0.2
0.4
0.4
0.4
0.2
0.2
0.2
± 10
± 10
± 10
µA
VO = 0 V to VDD,
± 10
± 10
± 10
µA
Minimum cycle
720
560
480
mA
8
8
8
mA
VIH = VDD − 0.2 V (LVCMOS),
After one memory cycle,
RAS0 and CASx high
1.2
1.2
1.2
mA
VIH = 2 V (LVTTL),
After one memory cycle,
RAS0 and CASx high
Standby current
MIN
LVTTL
VOH
ICC2
’2FJ64EPN-50
TEST CONDITIONS†
V
ICC3‡§
Average refresh
current
(RAS-only
refresh or CBR)
VDD = 3.6 V,
Minimum cycle,
RAS0 cycling,
CASx high (RAS-only refresh),
RAS0 low after CASx low (CBR)
720
560
480
mA
ICC4‡¶
Average EDO
current
VDD = 3.6 V,
RAS0 low,
800
720
640
mA
ICC6
Average
self-refresh
current
CASx < 0.2 V,
RAS0 < 0.2 V,
Measured after tRASS min
2
2
2
mA
ICC10
Average battery
back-up
operating current
(equivalent
refresh time is
128 ms), CBR
only
tRC = 31.25 µs, tRAS ≤ 300 ns
VDD − 0.2 V ≤ VIH ≤ 3.9 V,
0 V ≤ VIL ≤ 0.2 V, WE0 and OE0 =
VIH,
Address and data stable
2.8
2.8
2.8
mA
tHPC = MIN,
CASx cycling
PRODUCT PREVIEW
PARAMETER
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS0 = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
9
SMMS685 − AUGUST 1997
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
’2XJ64xPN-50
PRODUCT PREVIEW
PARAMETER
MIN
MAX
’2XJ64xPN-60
MIN
MAX
’2XJ64xPN-70
MIN
MAX
UNIT
tAA
tCAC
Access time from column address (see Note 4)
25
30
35
ns
Access time from CASx (see Note 4)
13
15
18
ns
tCPA
tRAC
Access time from CASx precharge (see Note 4)
28
35
40
ns
Access time from RAS0 (see Note 4)
50
60
70
ns
tOEA
tCLZ
Access time from OE0 (see Note 4)
13
15
18
ns
Delay time, CASx to output in low impedance
0
tREZ
tCEZ
Output buffer turn off delay from RAS0 (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn off delay from CASx (see Note 5)
3
13
3
15
3
18
ns
tOEZ
tWEZ
Output buffer turn off delay from OE0 (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn off delay from WE0 (see Note 5)
3
13
3
15
3
18
ns
0
0
ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
4. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the outputs are no longer driven. Data-in should not be driven
until one of the applicable maximum values is satisfied.
EDO timing requirements (see Note 3)
’2XJ64xPN-50
MIN
MAX
’2XJ64xPN-60
MIN
MAX
’2XJ64xPN-70
MIN
MAX
UNIT
tHPC
tPRWC
Cycle time, EDO page mode, read-write
20
25
30
ns
Cycle time, EDO read-write
57
68
78
ns
tCSH
tCHO
Delay time, RAS0 active to CASx precharge
40
48
58
ns
Hold time, OE0 from CASx
7
10
10
ns
tDOH
tCAS
Hold time, output from CASx
5
5
5
ns
Pulse duration, CASx active
8
tWPE
tCP
Pulse duration, WE0 active (output disable only)
7
7
7
ns
Pulse duration, CASx precharge
8
10
10
ns
tOCH
tOEP
Setup time, OE0 before CASx
8
10
10
ns
Precharge time, OE0
5
5
5
ns
10 000
NOTE 3: With ac parameters, it is assumed that tT = 2 ns.
10
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
10
10 000
12
10 000
ns
SMMS685 − AUGUST 1997
ac timing requirements (see Note 3)
MIN
MAX
’2xJ64xPN-60
MIN
MAX
’2xJ64xPN-70
MIN
MAX
UNIT
tRC
tRWC
Cycle time, random read or write
tRASP
tRAS
Pulse duration, RAS0 active, fast page mode (see Note 6)
50
100 000
60
100 000
70
100 000
ns
Pulse duration, RAS0 active, non-page mode (see Note 6)
50
10 000
60
10 000
70
10 000
ns
tRP
tWP
Pulse duration, RAS0 precharge
30
tRASS
tRPS
Pulse duration, RAS0 active, self refresh (see Note 7)
tASC
tASR
Setup time, column address
Cycle time, read-write
104
124
ns
135
160
ns
40
50
ns
8
10
10
ns
100
100
100
ms
90
110
130
ns
0
0
0
ns
Setup time, row address
0
0
0
ns
tDS
tRCS
Setup time, data in (see Note 8)
0
0
0
ns
Setup time, read command
0
0
0
ns
tCWL
tRWL
Setup time, write command before CASx precharge
8
10
12
ns
Setup time, write command before RAS0 precharge
8
10
12
ns
Setup time, write command before CASx active
(early-write only)
0
0
0
ns
10
10
ns
tWCS
Pulse duration, write command
84
111
Pulse duration, RAS0 precharge after self refresh
tWRP
tCSR
Setup time, WE0 high before RAS0 low (CBR refresh only)
10
Setup time, CASx referenced to RAS0 ( CBR refresh only )
5
5
5
ns
tCAH
tDH
Hold time, column address
8
10
12
ns
Hold time, data in (see Note 8)
8
10
12
ns
tRAH
tRCH
Hold time, row address
8
10
10
ns
Hold time, read command referenced to CASx (see Note 9)
0
0
0
ns
tRRH
Hold time, read command referenced to RAS0 (see Note 9)
0
0
0
ns
tWCH
Hold time, write command during CASx active
( early-write only )
8
10
12
ns
tROH
tWRH
Hold time, RAS0 referenced to OE0
8
10
10
ns
Hold time, WE0 high after RAS0 low (CBR refresh only)
10
10
10
ns
tCHR
tOEH
Hold time, CASx referenced to RAS0 ( CBR refresh only )
10
10
10
ns
Hold time, OE0 command
13
15
18
ns
tRHCP
tCHS
Hold time, RAS0 active from CASx precharge
tAWD
Hold time, CASx referenced to RAS0 (self refresh only)
Delay time, column address to write command
( read-write only )
28
35
40
ns
− 50
− 50
− 50
ns
42
49
57
ns
PRODUCT PREVIEW
’2xJ64xPN-50
tCRP
Delay time, CASx precharge to RAS0
5
5
5
ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
6. In a read-write cycle, tRWD and tRWL must be observed.
7. During the period of 10 µs ≤ tRASS ≤100 µs, the device is in a transition state from normal-operation mode to self-refresh mode.
8. Referenced to the later of CASx or WE0 in write operations
9. Either tRRH or tRCH must be satisfied for a read cycle.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
11
SMMS685 − AUGUST 1997
ac timing requirements (see Note 3) (continued)
’2xJ64xPN-60
’2xJ64xPN-70
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tCWD
tOED
Delay time, CASx to write command (read-write only)
0
0
0
ns
Delay time, OE0 to data in
0
0
0
ns
tRAD
tRAL
Delay time, RAS0 to column address (see Note 10)
8
10
12
ns
Delay time, column address to RAS0 precharge
8
10
12
ns
tCAL
tRCD
Delay time, column address to CASx precharge
0
0
0
ns
Delay time, RAS0 to CASx (see Note 10)
5
5
5
ns
tRPC
tRSH
Delay time, RAS0 precharge to CASx
5
5
5
ns
8
10
12
ns
tRWD
Delay time, RAS0 to write command (read−write only)
67
79
92
ns
tCPW
Delay time, CASx precharge to write command
(read-write only)
45
54
62
ns
tREF
PRODUCT PREVIEW
’2xJ64xPN-50
Delay time, CASx active to RAS0 precharge
Refresh time interval
’2EJ64DPN
32
32
32
’2EJ64EPN
64
64
64
’2FJ64xPN
128
128
128
tT
Transition time
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
10. The maximum value is specified only to ensure access time.
12
POST OFFICE BOX 1443
2
30
• HOUSTON, TEXAS 77251−1443
2
30
2
30
ms
ns
SMMS685 − AUGUST 1997
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing
parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the
remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock
(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard.
See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for
further details.
Tables in this section list the SPD contents as follows:
Table 2−TM2EJ64EPN
Table 4−TM2FJ64EPN
PRODUCT PREVIEW
Table 1−TM2EJ64DPN
Table 3−TM2FJ64DPN
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
13
SMMS685 − AUGUST 1997
serial presence detect (continued)
Table 1. Serial Presence-Detect Data for the TM2EJ64DPN
PRODUCT PREVIEW
BYTE
NO.
’2EJ64DPN-50
FUNCTION DESCRIBED
’2EJ64DPN-60
’2EJ64DPN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written into
serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
11
0Bh
11
0Bh
11
0Bh
4
Number of column addresses on
this assembly
10
0Ah
10
0Ah
10
0Ah
5
Number of module banks on this
assembly
1 bank
01h
1 bank
01h
1 bank
01h
6
Data width of this assembly
64 bits
40h
64 bits
40h
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this
assembly
9
RAS0 access time of module
10
CASx access time of module
11
SODIMM configuration type
(non-parity, parity, ECC)
12
Refresh rate / type
13
DRAM width, primary DRAM
14
Error-checking SDRAM data width
62
SPD revision
63
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
tRAC = 60 ns
tCAC = 15 ns
Non-parity
00h
Non-parity
00h
Non-parity
00h
15.6 µs
00h
15.6 µs
00h
15.6 µs
00h
x8
08h
x8
08h
x8
08h
12h
N/A
00h
N/A
00h
N/A
00h
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
Checksum for bytes 0 −62
41
29h
53
35h
66
42h
Manufacturer’s JEDEC ID code per
JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
64−71
72
73−90
91
92
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
14
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMMS685 − AUGUST 1997
serial presence detect (continued)
Table 2. Serial Presence-Detect Data for the TM2EJ64EPN
’2EJ64EPN-50
FUNCTION DESCRIBED
’2EJ64EPN-60
’2EJ64EPN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written
into serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
12
0Ch
12
0Ch
12
0Ch
4
Number of column addresses on
this assembly
9
09h
9
09h
9
09h
5
Number of module banks on this
assembly
1 bank
01h
1 bank
01h
1 bank
01h
6
Data width of this assembly
64 bits
40h
64 bits
40h
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this
assembly
9
RAS0 access time of module
10
CASx access time of module
11
SODIMM configuration type
(non-parity, parity, ECC)
12
Refresh rate / type
13
DRAM width, primary DRAM
14
Error-checking SDRAM data width
62
SPD revision
63
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
tRAC = 60 ns
tCAC = 15 ns
Non-parity
00h
Non-parity
00h
Non-parity
00h
15.6 µs
00h
15.6 µs
00h
15.6 µs
00h
x8
08h
x8
08h
08h
08h
12h
N/A
00h
N/A
00h
N/A
00h
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
Checksum for bytes 0 −62
41
29h
53
35h
66
42h
Manufacturer’s JEDEC ID code
per JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
64−71
72
73−90
91
92
PRODUCT PREVIEW
BYTE
NO.
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
15
SMMS685 − AUGUST 1997
serial presence detect (continued)
Table 3. Serial Presence-Detect Data for the TM2FJ64DPN
PRODUCT PREVIEW
BYTE
NO.
’2FJ64DPN-50
FUNCTION DESCRIBED
’2FJ64DPN-60
’2FJ64DPN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written
into serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
11
0Bh
11
0Bh
11
0Bh
4
Number of column addresses on
this assembly
10
0Ah
10
0Ah
10
0Ah
5
Number of module banks on this
assembly
1 bank
01h
1 bank
01h
1 bank
01h
6
Data width of this assembly
64 bits
40h
64 bits
40h
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this
assembly
9
RAS0 access time of module
10
CASx access time of module
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
tRAC = 60 ns
tCAC = 15 ns
11
SODIMM configuration type
(non-parity, parity, ECC)
Non-parity
00h
Non-parity
00h
Non-parity
00h
12
Refresh rate / type
15.6 µs /
self-refresh
80h
15.6 µs /
self-refresh
80h
15.6 µs /
self-refresh
80h
13
DRAM width, primary DRAM
x8
08h
x8
08h
x8
08h
14
Error-checking SDRAM data width
00h
62
SPD revision
63
12h
N/A
00h
N/A
00h
N/A
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
Checksum for bytes 0 −62
169
A9h
181
B5h
194
C2h
Manufacturer’s JEDEC ID code
per JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
64−71
72
73−90
91
92
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
16
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMMS685 − AUGUST 1997
serial presence detect (continued)
Table 4. Serial Presence-Detect Data for the TM2FJ64EPN
’2FJ64EPN-50
FUNCTION DESCRIBED
’2FJ64EPN-60
’2FJ64EPN-70
ITEM
DATA
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written
into serial memory during module
manufacturing
128 bytes
80h
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD
memory device
256 bytes
08h
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
02h
EDO
02h
EDO
02h
3
Number of row addresses on this
assembly
12
0Ch
12
0Ch
12
0Ch
4
Number of column addresses on
this assembly
9
09h
9
09h
9
09h
5
Number of module banks on this
assembly
1 bank
02h
1 bank
02h
1 bank
02h
6
Data width of this assembly
64 bits
40h
64 bits
40h
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this
assembly
9
RAS0 access time of module
10
CASx access time of module
00h
00h
00h
LVTTL
01h
LVTTL
01h
LVTTL
01h
tRAC = 50 ns
tCAC = 13 ns
32h
3Ch
0Fh
tRAC = 70 ns
tCAC = 18 ns
46h
0Dh
tRAC = 60 ns
tCAC = 15 ns
11
SODIMM configuration type
(non-parity, parity, ECC)
Non-parity
00h
Non-parity
00h
Non-parity
00h
12
Refresh rate / type
15.6 µs /
self-refresh
80h
15.6 µs /
self-refresh
80h
15.6 µs /
self-refresh
80h
13
DRAM width, primary DRAM
x8
08h
x8
08h
x8
08h
14
Error-checking SDRAM data width
00h
62
SPD revision
63
12h
N/A
00h
N/A
00h
N/A
Rev. 1
01h
Rev. 1
01h
Rev. 1
01h
Checksum for bytes 0 −62
169
A9h
181
B5h
194
C2h
Manufacturer’s JEDEC ID code
per JEP-106E
97h
9700...00h
97h
9700...00h
97h
9700...00h
Manufacturing location†
TBD
TBD
TBD
Manufacturer’s part number†
Die revision code†
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
TBD
99−125
TBD
TBD
TBD
126−127
Manufacturer specific data†
Vendor specific data†
TBD
TBD
TBD
128−166
System integrator’s specific data‡
TBD
TBD
TBD
64−71
72
73−90
91
92
PRODUCT PREVIEW
BYTE
NO.
167−255 Open
† TBD indicates values are determined at manufacturing time and are module dependent.
‡ These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
17
SMMS685 − AUGUST 1997
device symbolization (TM2EJ64DPN illustrated)
TM2EJ64DPN
-SS
YY
MM
T
-SS
=
=
=
=
Year Code
Month Code
Assembly Site Code
Speed Code
PRODUCT PREVIEW
NOTE A: Location of symbolization may vary.
18
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
YYMMT
SMMS685 − AUGUST 1997
MECHANICAL DATA
BDM (R-SODIMM-N144)
SMALL OUTLINE DUAL IN-LINE MEMORY MODULE
2.665 (67,69)
2.655 (67,44)
0.024 (0,61) TYP
0.044 (1,12)
0.036 (0,91)
Notch 0.060 (1,52) x 0.158 (4,01) Deep
0.031 (0,79)
PRODUCT PREVIEW
Notch 0.157 (4,00) x 0.079 (2,00) Deep
(2 Places)
0.010 (0,25) MAX
0.788 (20,00) TYP
0.098 (2,49)
1.005 (25,53)
0.995 (25,27)
0.196 (4,98)
0.157 (4,00)
0.126 (3,20)
0.095 (2,41) MAX
0.150 (3,81) MAX
(For Double Sided Module Only)
4088187/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-190
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
19
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