TI TMS417809A

TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
D
D
D
D
D
D
D
D
D
This data sheet is applicable to all
TMS417809As
and
TMS427809A/Ps
symbolized by Revision “E” and subsequent
revisions as described in the device
symbolization section.
Organization . . . 2 097152 by 8 Bits
Single Power Supply (5 V or 3.3 V)
Performance Ranges:
’417809A-50
’417809A-60
’417809A-70
’427809A/P-50
’427809A/P-60
’427809A/P-70
ACCESS ACCESS ACCESS
TIME
TIME
TIME
tRAC
tCAC
tAA
MAX
MAX
MAX
50 ns
13 ns
25 ns
60 ns
15 ns
30 ns
70 ns
18 ns
35 ns
50 ns
13 ns
25 ns
60 ns
15 ns
30 ns
70 ns
18 ns
35 ns
DZ / DGC PACKAGE
( TOP VIEW )
VCC
DQ0
DQ1
DQ2
DQ3
W
RAS
NC
A10
A0
A1
A2
A3
VCC
EDO
CYCLE
tHPC
MIN
20 ns
25 ns
30 ns
20 ns
25 ns
30 ns
Extended-Data-Out (EDO) Operation
CAS-Before-RAS ( CBR) Refresh
Long Refresh Period and Self-Refresh
Option (TMS427809AP)
High-Impedance State Unlatched Output
High-Reliability Plastic 28-Lead
400-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DZ Suffix) and
28-Lead 400-Mil-Wide Surface-Mount Thin
Small-Outline Package (TSOP) (DGC Suffix)
Ambient Temperature Range
0°C to 70°C
description
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VSS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
PIN NOMENCLATURE
A[0 :10]
DQ[0: 7]
CAS
NC
OE
RAS
VCC
VSS
W
Address Inputs
Data In / Data Out
Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
3.3-V or 5-V Supply
Ground
Write Enable
AVAILABLE OPTIONS
The TMS417809A and TMS427809A series are
16 777 216-bit dynamic random access memory
(DRAM) devices organized as 2 097 152 words of
8 bits each. The TMS427809AP series is a
low-power, self-refresh, 16 777 216-bit DRAM
organized as 4 194 304 words of four bits.They
employ TI state-of-the-art technology for high
performance, reliability, and low power.
DEVICE
POWER
SUPPLY
REFRESH
CYCLES
TMS417809A
5V
2 048 in 32 ms
TMS427809A
3.3 V
2 048 in 32 ms
TMS427809AP
3.3 V
2 048 in 128 ms
These devices feature maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS417809A is offered in a 28-lead plastic surface-mount SOJ package (DZ suffix). The TMS427809A / P
is offered in a 28-lead plastic surface-mount TSOP package (DGC suffix). These packages are designed for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
logic symbol (TMS417809A and TMS427809A/P)†
RAM 2M x 8
A0 10
A1 11
20D10/21D0
A2 12
A3 13
A4
16
A5 17
A6 18
A
0
2 097 151
A7 19
A8 20
A9 21
A10 9
20D19/21D9
20D20
C20[ROW]
RAS
7
CAS 23
G23/[REFRESH ROW]
24[PWR DWN]
C21[COL]
G24
&
23C22
W6
OE
22
DQ0 2
23,21D
24,25EN
G25
A,22D
∇ 26
A,Z26
DQ1 3
DQ2 4
DQ3 5
DQ4 24
DQ5 25
DQ6 26
DQ7 27
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12.
2
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TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
functional block diagram (TMS417809A and TMS427809A/P)
RAS
CAS
W
OE
Timing and Control
A0
A1
10
Column Decode
Sense Amplifiers
Column Address
Buffers
256K Array
256K Array
A9
Row Address
Buffers
A10
256K Array
R
o
w
11
256K Array
DataIn
Reg.
256K Array
8
D
e
c
o
d
e
32
8
32
I/O
Buffers
DataOut
Reg.
8
8
DQ0 – DQ7
256K Array
11
operation
extended data out
Extended data out (EDO) allows data output rates up to 50 MHz for 50-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup-and-hold and for
address multiplexing is eliminated. The maximum number of columns that can be accessed is determined by
tRASP , the maximum RAS low time.
The EDO does not place the data-in / data-out pins (DQ pins) in the high-impedance state with the rising edge
of CAS. The output remains valid for the system to latch the data. After CAS goes high, the DRAM decodes the
next address. OE and W can control the output impedance. Descriptions of OE and W further explain EDO
operation benefits.
address: A0 – A10
Twenty-one address bits are required to decode each of the 2 097 152 storage-cell locations. Eleven
row-address bits are set up on inputs A0 through A10 and latched onto the chip by RAS. Ten column-address
bits are set up on A0 through A9. All addresses must be stable on or before the falling edge of RAS and CAS.
RAS is similar to a chip-enable because it activates the sense amplifiers as well as the row decoder. CAS is used
as a chip-select, activating the output buffers and latching the address bits into the column-address buffers.
output-enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two
methods of placing the DQs into the high-impedance state and maintaining that state during CAS high time. The
first method is to transition OE high before CAS transitions high and keep OE high for tCHO (hold time, OE from
CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS falls
again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a minimum
of tOEP (precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further transitions
on OE until CAS falls again (see Figure 8).
POST OFFICE BOX 1443
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3
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
write-enable ( W)
The read- or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled as long as CAS is high
(see Figure 8).
data in / data out (DQ0 – DQ7)
Data is written during a write- or read-modify-write cycle. Depending on the mode of operation, the latter of the
falling edges of CAS or W strobes data into the on-chip data latch with setup-and-hold times referenced to the
latter edge. The DQs drive valid data after all access times are met and the data remains valid except in cases
described in the W and OE descriptions.
RAS-only refresh
A refresh operation must be performed once every 32 ms (128 ms for TMS427809AP) to retain data. This can
be achieved by strobing each of the 2 048 rows (A0 – A10). A normal read- or write cycle refreshes all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving
power as the output buffers remain in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh.
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by
holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle. The external address is ignored and the refresh address is generated internally.
CAS-before-RAS ( CBR) refresh
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after
RAS falls (see parameter tCHR). For successive CBR-refresh cycles, CAS can remain low while cycling RAS.
The external address is ignored and the refresh address is generated internally.
battery-backup refresh
TMS427809AP
A low-power battery-backup refresh mode that requires less than 350 mA of refresh current is available on the
TMS427809AP. Data integrity is maintained using CBR refresh with a period of 62.5 ms while holding RAS low
for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels
(VIL < 0.2 V, VIH > VCC – 0.2 V).
self-refresh (TMS427809AP)
The self-refresh mode is entered by dropping CAS low prior to RAS going low, then CAS and RAS are both held
low for a minimum of 100 ms. The chip is refreshed internally by an on-board oscillator. No external address is
required because the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and CAS are brought high to satisfy tCHS. Upon exiting self-refresh mode, a burst refresh (refreshes a full set
of row addresses) must be executed before continuing with normal operation to ensure that the DRAM is fully
refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh
( RAS-only or CBR ) cycle.
4
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TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
absolute maximum ratings over ambient temperature range (unless otherwise noted)†
Supply voltage range, VCC (TMS417809A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Supply voltage range, VCC (TMS427809A, TMS427809AP) . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any pin (TMS417809A) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on any pin (TMS427809A, TMS427809AP) (see Note 1) . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS417809A
VCC
VSS
Supply voltage
VIH
VIL
High-level input voltage
Low-level input voltage‡
TMS427809A/P
MIN
NOM
MAX
MIN
NOM
4.5
5
5.5
3
3.3
Supply voltage
0
MAX
UNIT
3.6
V
0
2.4
6.5
2
–1
0.8
– 0.3
V
VCC + 0.3
0.8
V
V
TA
Ambient temperature
0
70
0
70
°C
‡ The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
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5
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TMS417809A
PARAMETER
VOH
VOL
High-level output voltage
II
Input current (leakage)
IO
ICC1‡§
Low-level output voltage
TEST CONDITIONS†
IOH = – 5 mA
IOL = 4.2 mA
’417809A - 50
MIN
MAX
2.4
MIN
MAX
2.4
’417809A - 70
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output current (leakage)
VCC = 5.5 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Average read- or
write-cycle current
VCC = 5.5 V,
Minimum cycle
130
110
100
mA
2
2
2
VIH = 2.4 V ( TTL),
After one memory cycle,
ICC2
’417809A - 60
Average standby current
RAS and CAS high
VIH = VCC – 0.2 V (CMOS),
After one memory cycle,
mA
1
1
1
130
110
100
mA
110
90
80
mA
RAS and CAS high
ICC3‡§
Average
g refresh current
(RAS-only refresh or CBR)
VCC = 5.5 V,
RAS cycling,
Minimum cycle,
CAS high (RAS only),
RAS low after CAS low (CBR)
ICC4‡¶
Average EDO current
VCC = 5.5 V,
RAS low,
tHPC = MIN,
CAS cycling
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
6
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TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient conditions
(unless otherwise noted) (continued)
TMS427809A/ P
PARAMETER
VOH
High-level
output
voltage
VOL
Low-level
output
voltage
II
Input current
(leakage)
IO
ICC1‡§
ICC2
’427809A / P - 50
TEST CONDITIONS†
MIN
’427809A / P -60
MAX
MIN
2.4
MIN
MAX
UNIT
IOH = – 2 mA
LVTTL
IOH = – 100 µA
LVCMOS
IOL = 2 mA
LVTTL
0.4
0.4
0.4
IOL = 100 µA
LVCMOS
0.2
0.2
0.2
VCC = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
Output
current
(leakage)
VCC = 3.6 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
Average
read- or
write-cycle
current
VCC = 3.6 V,
Minimum cycle
120
100
90
mA
Average
g
standby
current
2.4
MAX
’427809A / P - 70
2.4
V
VCC – 0.2
VCC – 0.2
VCC – 0.2
V
VIH = 2 V (LVTTL)
After one memory cycle,
cycle
RAS and CAS high
’427809A
2
2
2
’427809AP
1
1
1
VIH = VCC – 0.2 V
((LVCMOS),
),
After one memory cycle,
RAS and CAS high
’427809A
1
1
1
mA
150
150
150
µA
mA
’427809AP
ICC3‡§
Average
refresh
current
(RAS-only
refresh
or CBR)
VCC = 3.6 V,
Minimum cycle,
RAS cycling,
CAS high (RAS-only refresh),
RAS low after CAS low (CBR)
120
100
90
mA
ICC4‡¶
Average
EDO current
VCC = 3.6 V,
RAS low,
tHPC = MIN,
CAS cycling
110
90
80
mA
ICC6#
Average
self-refresh
current
CAS < 0.2 V,
RAS < 0.2 V,
Measured after tRASS min
200
200
200
µA
ICC10#
Battery
back-up
operating
current
(equivalent
refresh time
is 128 ms),
CBR only
tRC = 62.5 µs,
tRAS ≤ 300 ns
VCC – 0.2 V ≤ VIH ≤ 3.9 V,
0 V ≤ VIL ≤ 0.2 V, W and OE = VIH,
Address and data stable
350
350
350
µA
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change during each EDO cycle, tHPC
# For TMS427809AP only
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7
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A10
5
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(RC)
Input capacitance, CAS and RAS
7
pF
Ci(W)
Input capacitance, W
Output capacitance†
7
pF
7
pF
Co
† CAS and OE = VIH to disable outputs
NOTE 2: VCC = NOM supply voltage ± 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
’417809A-50
’427809A/P-50
PARAMETER
MIN
MAX
’417809A-60
’427809A/P-60
MIN
MAX
’417809A-70
’427809A/P-70
MIN
UNIT
MAX
tAA
tCAC
Access time from column address (see Note 4)
25
30
35
ns
Access time from CAS (see Note 4)
13
15
18
ns
tCPA
tRAC
Access time from CAS precharge (see Note 4)
28
35
40
ns
Access time from RAS (see Note 4)
50
60
70
ns
tOEA
tCLZ
Access time from OE (see Note 4)
13
15
18
ns
Delay time, CAS to output in low impedance
0
tREZ
tCEZ
Output buffer turn-off delay from RAS (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn-off delay from CAS (see Note 5)
3
13
3
15
3
18
ns
tOEZ
tWEZ
Output buffer turn-off delay from OE (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn-off delay from W (see Note 5)
3
13
3
15
3
18
ns
0
0
ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
4. For TMS427809A / P, access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the output is no longer driven. Data-in should not be enabled
until one of the applicable maximum values is satisfied.
EDO timing requirements (see Note 3)
’417809A-50
’427809A/P-50
MIN
MAX
’417809A-60
’427809A/P-60
MIN
MAX
’417809A-70
’427809A/P-70
MIN
UNIT
MAX
tHPC
tPRWC
Cycle time, EDO page mode, read-write
20
25
30
ns
Cycle time, EDO read-write
57
68
78
ns
tCSH
tCHO
Delay time, RAS active to CAS precharge
40
48
58
ns
Hold time, OE from CAS
7
10
10
ns
tDOH
tCAS
Hold time, output from CAS
5
5
5
ns
Pulse duration, CAS active (see Note 6)
8
tWPE
tCP
Pulse duration, W active (output disable only)
7
7
7
ns
Pulse duration, CAS precharge
8
10
10
ns
tOCH
tOEP
Setup time, OE before CAS
8
10
10
ns
Precharge time, OE
5
5
5
ns
10 000
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
6. In a read-write cycle, tCWD and tCWL must be observed.
8
POST OFFICE BOX 1443
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10
10 000
12
10 000
ns
TMS417809A, TMS427809A, TMS427809AP
2097152 BY 8-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
ac timing requirements (see Note 3)
’417809A-50
’427809A/P-50
’417809A-60
’427809A/P-60
’417809A-70
’427809A/P-70
MIN
MIN
MIN
MAX
Cycle time, random read or write
tRASP
tRAS
Pulse duration, RAS active, fast page mode (see Note 7)
50
100 000
60
100 000
70
100 000
ns
Pulse duration, RAS active, non-page mode (see Note 7)
50
10 000
60
10 000
70
10 000
ns
tRP
tWP
Pulse duration, RAS precharge
30
40
50
ns
Pulse duration, write command
8
10
10
ns
tRASS
tRPS
Pulse duration, RAS active, self refresh (see Note 8)
100
100
100
ms
90
110
130
ns
tASC
tASR
Setup time, column address
0
0
0
ns
Setup time, row address
0
0
0
ns
tDS
tRCS
Setup time, data in (see Note 9)
0
0
0
ns
Setup time, read command
0
0
0
ns
tCWL
tRWL
Setup time, write command before CAS precharge
8
10
12
ns
Setup time, write command before RAS precharge
8
10
12
ns
Setup time, write command before CAS active
(early-write only)
0
0
0
ns
Cycle time, read-write
104
UNIT
MAX
tRC
tRWC
tWCS
84
MAX
111
Pulse duration, RAS precharge after self refresh
124
135
ns
160
ns
tWRP
tCSR
Setup time, W high before RAS low (CBR refresh only)
10
10
10
ns
Setup time, CAS referenced to RAS ( CBR refresh only )
5
5
5
ns
tCAH
tDH
Hold time, column address
8
10
12
ns
Hold time, data in (see Note 9)
8
10
12
ns
tRAH
tRCH
Hold time, row address
8
10
10
ns
Hold time, read command referenced to CAS (see Note 10)
0
0
0
ns
tRRH
Hold time, read command referenced to RAS (see Note 10)
0
0
0
ns
tWCH
Hold time, write command during CAS active
( early-write only )
8
10
12
ns
tROH
tWRH
Hold time, RAS referenced to OE
8
10
10
ns
Hold time, W high after RAS low (CBR refresh only)
10
10
10
ns
tCHR
tOEH
Hold time, CAS referenced to RAS ( CBR refresh only )
10
10
10
ns
Hold time, OE command
13
15
18
ns
tRHCP
tCHS
Hold time, RAS active from CAS precharge
28
35
40
ns
– 50
– 50
– 50
ns
42
49
57
ns
tAWD
Hold time, CAS referenced to RAS (self refresh only)
Delay time, column address to write command
( read-write only )
tCRP
Delay time, CAS precharge to RAS
5
5
5
ns
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
7. In a read-write cycle, tRWD and tRWL must be observed.
8. During the period of 10 µs ≤ tRASS ≤100 µs, the device is in a transition state from normal-operation mode to self-refresh mode.
9. Referenced to the later of CAS or W in write operations
10. Either tRRH or tRCH must be satisfied for a read cycle.
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ac timing requirements (see Note 3) (continued)
’417809A-50
’427809A/P-50
’417809A-60
’427809A/P-60
’417809A-70
’427809A/P-70
MIN
MIN
MIN
MAX
MAX
tCWD
tOED
Delay time, CAS to write command ( read-write only )
30
Delay time, OE to data in
13
tRAD
tRAL
Delay time, RAS to column address ( see Note 11)
10
Delay time, column address to RAS precharge
25
30
35
ns
tCAL
Delay time, column address to CAS precharge
18
20
25
ns
tRCD
tRPC
Delay time, RAS to CAS ( see Note 11)
12
Delay time, RAS precharge to CAS
5
5
5
ns
tRSH
tRWD
Delay time, CAS active to RAS precharge
8
10
12
ns
Delay time, RAS to write command (read-write only)
67
79
92
ns
Delay time, CAS precharge to write command
(read-write only)
45
54
62
ns
tCPW
’417809A
tREF
Refresh time interval
’427809A
2
40
15
25
12
37
14
32
’427809AP
tT
Transition time
NOTES: 3. With ac parameters, it is assumed that tT = 2 ns.
11. The maximum value is specified only to ensure access time.
34
UNIT
MAX
ns
18
30
45
ns
12
35
14
52
32
32
32
32
128
128
2
30
2
30
PARAMETER MEASUREMENT INFORMATION
VTH
VCC
RL
R1
Output Under Test
Output Under Test
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
DEVICE
’417809A
VCC (V)
5
’427809A/P
3.3
R1 (W)
R2 (W)
828
295
VTH (V)
1.31
1178
868
1.4
RL (W)
218
500
Figure 1. Load Circuits for Timing Parameters
10
R2
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
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ns
32
128
30
ns
ms
ns
TMS417809A, TMS427809A, TMS427809AP
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PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tCSH
tRCD
tRSH
tCRP
tCAS
tASR
CAS
tRAD
tCP
tASC
tRAH
Address
Row
tCAL
tRAL
Don’t Care
Column
tRCS
tRRH
tRCH
tCAH
W
Don’t Care
Don’t Care
tCAC
tCEZ
tREZ
tAA
DQ0 – DQ7
Hi-Z
Valid Data Out
See Note A
tCLZ
tRAC
tWEZ
tOEA
tWPE
tOEZ
tROH
OE
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCSH
tCAS
tASR
CAS
tCP
tASC
tCAL
tRAL
tCAH
tRAH
Address
Row
Don’t Care
Column
tCWL
tRAD
tRWL
tWCH
W
tWCS
Don’t Care
Don’t Care
tDH
tDS
DQ0 – DQ7
Don’t Care
Valid Data
Don’t Care
OE
Figure 3. Early-Write-Cycle Timing
12
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PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCAS
tCSH
tASR
tASC
CAS
tCP
tRAL
tRAH
tCAL
tCAH
Address
Row
Don’t Care
Column
tCWL
tRAD
W
tDS
tRWL
Don’t Care
Don’t Care
tWP
tCLZ
tDH
Don’t Care
Valid Data In
DQ0 – DQ7
Invalid Data Out
tOED
tOEH
OE
Don’t Care
Don’t Care
Figure 4. Write-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tCRP
tRCD
tCAS
tASR
CAS
tCP
tRAH
tCAH
tRAD
Address
tT
tASC
Row
Don’t Care
Column
tCWL
tRCS
tRWL
tRWD
tWP
Don’t Care
W
tAWD
tCWD
tCAC
tDS
tAA
tDH
tCLZ
DQ0 – DQ7
Hi-Z
Data
Out
See Note A
tRAC
Data
In
tOEZ
tOEA
tOED
OE
Don’t Care
tOEH
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 5. Read-Write-Cycle Timing
14
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PARAMETER MEASUREMENT INFORMATION
tRASP
RAS
tT
tRCD
tRSH
tCSH
tCRP
tHPC
tCAS
CAS
tRP
tRHCP
tCAS
tCP
tRAH
tASC
tCAL
tCAL
tASR
tRAL
tCAH
Address
Row
Column #1
Column #2
Column #3
tRAD
tRCH
tOEA
OE
tRCS
tCAC
tRRH
tDOH
W
tCAC
tAA
tAA
tCEZ
tRAC
tREZ
tCLZ
DQ0 – DQ7
(see Note C)
tCPA
Data #1
Data #2
Data #3
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. Access time is tCPA-, tAA-, or tCAC-dependent.
C. Output is turned off by tCEZ if RAS goes high during CAS low.
Figure 6. EDO Read Cycle
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PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tCAS
CAS
tRHCP
tHPC
tCP
tCAS
tRSH
tASR
tCAL
tRAH
tCAL
tASC
tRAL
tCAH
Row
Address
Column #1
Column #2
Column #3
tRAD
tOCH
tCHO
tOEP
OE
tOEA
tRRH
tRCS
tRCH
tOEA
W
tCAC
tDOH
tCLZ
tOEZ
tCAC
tREZ
tOEZ
tRAC
DQ0 – DQ7
tCEZ
tCPA
tAA
tAA
Data #1
Data #1
Data #2
NOTE A: Output is turned off by tCEZ if RAS goes high during CAS low.
Figure 7. EDO Read-Cycle With OE Control
16
(see Note A)
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Data #3
TMS417809A, TMS427809A, TMS427809AP
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SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
tRASP
RAS
tRP
tCSH
tRHCP
tHPC
tCRP
tRSH
tCP
tCAS
CAS
tASR
tRAH
tASC
Address
Row
tCAH
tCAL
Column #1
tRAL
Column #3
Column #2
tRAD
OE
tOEA
tCAC
tRCS
tCAC
tWPE
tRCH
tRRH
W
tDOH
tCAC
tWEZ
tAA
tCPA
tCPA
tCLZ
tCEZ
tAA
tAA
tREZ
tRAC
DQ0 – DQ7
Data #1
Data #2
Data #3
Figure 8. EDO Read-Cycle With W Control
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17
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SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tRHCP
tHPC
tCSH
tRCD
tCAS
tASC
CAS
tRAH
tCP
tCAL
tCAH
tRAL
tASR
Address
tCRP
tRSH
Row
tCAL
Column
Don’t Care
Column
tCWL
tCWL
tRAD
tWCH
tRWL
tWCS
W
Don’t Care
Don’t Care
Don’t Care
tDH
tDS
DQ0 – DQ7
Data In
Data In
Don’t Care
Don’t Care
OE
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 9. EDO-Early-Write-Cycle Timing
18
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SMKS894B – AUGUST 1996 – REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tHPC
tCRP
tRSH
tRCD
tCAL
tCAS
tASC
CAS
tRAH
tCP
Address
tRAL
tCAH
tASR
Row
Column
Column
Don’t Care
tRAD
tCAL
tCWL
tCWL
W
tRWL
tWP
tDS
Don’t Care
Don’t Care
tOEH
tDH
DQ0 – DQ7
Don’t Care
Don’t Care
tCLZ
Valid
In
Valid Data In
Don’t Care
Invalid Data out
tOEH
tOED
Don’t Care
OE
Don’t Care
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 10. EDO Write-Cycle Timing
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PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRSH
tPRWC
tRCD
tCAS
tASR
tASC
CAS
tCAL
tCAH
tRAL
tRAD
Row
Address
tCRP
tCP
Column 1
Column 2
Don’t Care
tRAH
tCWL
tCWD
tCPW
tAWD
tRWL
tWP
tRWD
W
tRCS
tCPA
tAA
tDH
tRAC
Valid Out 2
See Note A
tDS
tCAC
Valid
In 1
DQ0 – DQ7
tCLZ
tOEA
tOEH
Valid
In 2
Valid
Out 1
tOEZ
tOED
tOEH
OE
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated.
Figure 11. EDO Read-Write-Cycle Timing
20
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PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tCRP
tRP
tT
CAS
Don’t Care
tRPC
tRAH
tASR
Address
Don’t Care
Row
Don’t Care
Row
Don’t Care
W
DQ0 – DQ7
Hi-Z
Don’t Care
OE
Figure 12. RAS-Only Refresh-Cycle Timing
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21
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PARAMETER MEASUREMENT INFORMATION
tRC
tRP
RAS
tRAS
tCSR
tRPC
tCHR
tT
CAS
tWRP
W
tWRH
Don’t Care
Don’t Care
Address
Don’t Care
OE
Don’t Care
DQ0 – DQ7
Hi-Z
Figure 13. Automatic-CBR-Refresh-Cycle Timing
22
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PARAMETER MEASUREMENT INFORMATION
tRASS
RAS
tRPC
tRPS
tCSR
tCHS
CAS
tCP
Address
Don’t Care
tWRP
tWRH
W
Don’t Care
OE
Don’t Care
DQ0 – DQ7
Hi-Z
Figure 14. Self-Refresh-Cycle Timing
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23
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PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRP
tRAS
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Address
Row
Col
Don’t Care
tWRH
tWRH
tRRH
tWRP
tWRP
tRCS
tRAC
W
tCAC
tREZ
tWEZ
tCEZ
tAA
Valid Data Out
DQ0 – DQ7
Don’t Care
tCLZ
tOEZ
tOEA
OE
Figure 15. Hidden-Refresh-Cycle (Read) Timing
24
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PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Row
Address
Don’t Care
Col
tWRH
tWCS
tWRP
tWP
W
tWCH
tDH
tDS
DQ0 – DQ7
Don’t Care
Valid Data
Don’t Care
OE
Figure 16. Hidden-Refresh-Cycle ( Write) Timing
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MECHANICAL DATA
DGC (R-PDSO-G28)
PLASTIC SMALL-OUTLINE PACKAGE
0.020 (0,50)
0.012 (0,30)
0.050 (1,27)
28
0.008 (0,20) M
15
0.471 (11,96)
0.455 (11,56)
0.404 (10,26)
0.396 (10,06)
0.006 (0,15) NOM
1
14
Gage Plane
0.729 (18,51)
0.721 (18,31)
0.010 (0,25)
0°– 5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.047 (1,20) MAX
0.004 (0,10)
0.000 (0,00) MIN
4040260-2 / B 02/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
26
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MECHANICAL DATA
DZ (R-PDSO-J**)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
32 PIN SHOWN
A
32
17
0.445 (11,30)
0.435 (11,05)
0.405 (10,29)
0.395 (10,03)
1
16
0.032 (0,81)
0.026 (0,66)
0.148 (3,76)
0.128 (3,25)
0.106 (2,69) NOM
0.008 (0,20) NOM
Seating Plane
0.020 (0,51)
0.016 (0,41)
0.004 (0,10)
0.007 (0,18) M
0.380 (9,65)
0.360 (9,14)
0.050 (1,27)
PINS **
24
28
32
40
42
A MAX
0.730
(18,54)
0.730
(18,54)
0.830
(21,08)
1.030
(26,16)
1.080
(27,43)
A MIN
0.720
(18,29)
0.720
(18,29)
0.820
(20,83)
1.020
(25,91)
1.070
(27,18)
DIM
4040094 / C 11/95
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,13).
The 24 pin package has the center two pins removed on both sides.
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device symbolization (TMS417809A illustrated)
TI
-SS
Speed ( - 50, - 60, - 70)
Low-Power/Self Refresh Designator (Blank or P)
TMS417809A DZ
W
E
Y
M LLLL
P
Package Code
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
28
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