TI TMS464409

TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
D
D
D
D
D
D
D
D
D
DGC PACKAGE
( TOP VIEW )
Organization . . . 16 777 216 by 4 Bits
Single 3.3-V Power Supply
(± 0.3-V Tolerance)
Performance Ranges:
VCC
DQ1
DQ2
NC
NC
NC
NC
W
RAS
A0
A1
A2
A3
A4
A5
VCC
ACCESS ACCESS ACCESS EDO
TIME
TIME
TIME
CYCLE
tRAC
tCAC
tAA
tHPC
(MAX)
(MAX)
(MAX)
(MIN)
’46x409/P-40 40 ns
11 ns
20 ns
16 ns
’46x409/P-50 50 ns
13 ns
25 ns
20 ns
’46x409/P-60 60 ns
15 ns
30 ns
25 ns
Extended-Data-Out (EDO) Operation
CAS-Before-RAS (CBR) Refresh
Long Refresh Period (See Available
Options Table)
Low-Power, Self-Refresh Version
(TMS46x409P)
3-State Unlatched Output
All Inputs / Outputs and Clocks Are
Low-Voltage TTL (LVTTL) Compatible
High-Reliability Plastic 32-Lead
400-Mil-Wide Thin Small-Outline (TSOP)
Package (DGC Suffix)
Operating Free-Air Temperature Range
0°C to 70°C
TMS464409
TMS464409P
TMS465409
TMS465409P
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VSS
DQ4
DQ3
NC
NC
NC
CAS
OE
A12†
A11
A10
A9
A8
A7
A6
VSS
† A12 is NC for TMS465409 and TMS465409P.
PIN NOMENCLATURE
AVAILABLE OPTIONS
DEVICE
1
PRODUCT PREVIEW
D
D
SELF-REFRESH
BATTERY
BACKUP
RAS-ONLY
REFRESH
CYCLES
CBR
REFRESH
CYCLES
—
8 192 in 64 ms
4 096 in 64 ms
YES
8 192 in 128 ms
4 096 in 128 ms
—
4 096 in 64 ms
4 096 in 64 ms
YES
4 096 in 128 ms
4 096 in 128 ms
A0 – A12
CAS
DQ1 – DQ4
NC
OE
RAS
W
VCC
VSS
Address Inputs
Column-Address Strobe
Data In / Data Out
No Internal Connection
Output Enable
Row-Address Strobe
Write Enable
3.3-V Supply
Ground
description
The TMS464409 and TMS465409 series are low-voltage, 67 108 864-bit dynamic random-access memories
(DRAMs), organized as 16 777 216 words of 4 bits each. The TMS464409P and TMS465409P series are
high-speed, low-voltage, low-power, self-refresh, 67 108 864-bit DRAMs, organized as 16 777 216 words of
4 bits each. Both sets of devices employ state-of-the-art technology for high performance, reliability, and low
power.
These devices feature maximum RAS access times of 40, 50, and 60 ns. All inputs and outputs, including clocks,
are compatible with LVTTL. All addresses and data-in lines are latched on chip to simplify system design. Data
out is unlatched to allow greater system flexibility.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
1
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
description (continued)
The TMS46x409 and TMS46x409P series are offered in a 400-mil, 32-lead plastic surface mount TSOP
package (DGC suffix). This package is designed for operation from 0°C to 70°C.
logic symbol (TMS464409 and TMS464409P)†
RAM 16M × 4
A0 10
A1 11
20D11/21D0
A2 12
A3 13
A4
14
A5 15
A6 18
A
A7 19
A8 20
PRODUCT PREVIEW
A9 21
A10 22
A11 23
A12 24
0
16777216
20D20/21D9
20D21/21D10
20D22/
20D23/
C20[ROW]
RAS
9
CAS 26
G23/[REFRESH ROW]
24[PWR DWN]
C21[COL]
G24
&
23C22
W 8
OE
25
DQ1 2
23,21D
24,25EN
G25
A,22D
∇ 26
A,Z26
DQ2 3
DQ3 30
DQ4 31
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
logic symbol (TMS465409 and TMS465409P)†
RAM 16M × 4
A0 10
A1 11
20D12/21D0
A2 12
A3 13
A4
14
A5 15
A6 18
A
0
16777216
A7 19
A8 20
A9 21
A10 22
A11 23
20D22/21D10
20D23/21D11
RAS
9
CAS 26
PRODUCT PREVIEW
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21[COL]
G24
&
23C22
W 8
OE
25
DQ1 2
23,21D
24,25EN
G25
A,22D
∇ 26
A,Z26
DQ2 3
DQ3 30
DQ4 31
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
3
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
functional block diagram
TMS464409, TMS464409P
RAS
CAS
W
OE
Timing and Control
A0
A1
11
Column Decode
Sense Amplifiers
ColumnAddress
Buffers
R
o
w
A10
PRODUCT PREVIEW
RowAddress
Buffers
A11,
A12
DataIn
Reg.
512K Array
4
D
e
c
o
d
e
13
4
512K Array
I/O
Buffers
32
4
4
DataOut
Reg.
512K Array
DQ1 – DQ4
12
2
TMS465409, TMS465409P
RAS
CAS
W
OE
Timing and Control
A0
A1
12
Column Decode
Sense Amplifiers
ColumnAddress
Buffers
512K Array R
512K Array o
w
A11
16
RowAddress
Buffers
12
4
512K Array
D
e
c
o
d
512K Array e 512K Array
4
16
11
4
POST OFFICE BOX 1443
DataIn
Reg.
512K Array
• HOUSTON, TEXAS 77251–1443
I/O
Buffers
4
4
DataOut
Reg.
DQ1 – DQ4
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
operation
extended data out
Extended data out (EDO) allows data output rates up to 66 MHz for 40-ns devices. When keeping the same
row address while selecting random column addresses, the time for row-address setup and hold and for address
multiplex is eliminated. The maximum number of columns that can be accessed is determined by tRASP , the
maximum RAS low time.
Extended data out does not place the data in / data out pins (DQ pins) into the high-impedance state with the
rising edge of CAS during RAS low. The output remains valid for the system to latch the data. After CAS goes
high, the DRAM decodes the next address. OE and W can control the output impedance. Descriptions of OE
and W further explain EDO operation benefit.
Twenty-four address bits are required to decode each one of 16 777 216 storage cell locations. For the
TMS465409 and TMS465409P,12 row-address bits are set up on A0 through A11 and latched onto the chip by
the row-address strobe (RAS). Twelve column-address bits are set up on A0 through A11. For the TMS464409
and TMS464409P, 13 row-address bits are set up on inputs A0 through A12 and latched onto the chip by RAS.
Eleven column-address bits are set up on A0 through A10. All addresses must be stable on or before the falling
edge of RAS and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the
row decoder. CAS is used as a chip select, activating the output buffers and latching the address bits into the
column-address buffers.
output enable (OE)
OE controls the impedance of the output buffers. While CAS and RAS are low and W is high, OE can be brought
low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two
methods for placing the DQs into the high-impedance state and maintaining that state during CAS high time.
The first method is to transition OE high before CAS transitions high and keep OE high for tCHO (hold time, OE
from CAS) past the CAS transition. This disables the DQs and they remain disabled, regardless of OE, until CAS
falls again. The second method is to have OE low as CAS transitions high. Then OE can pulse high for a
minimum of tOEP (precharge time, OE) anytime during CAS high time, disabling the DQs regardless of further
transitions on OE until CAS falls again (see Figure 8).
write enable ( W)
The read or write mode is selected through W. A logic high on W selects the read mode, and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to CAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded. If W goes low in an extended-data-out read cycle, the DQs are disabled so long as CAS is high
(see Figure 9).
data in / data out (DQ1 – DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the later falling
edge of CAS or W strobes data into the on-chip data latch with setup and hold times referenced to the later edge.
The DQs drive valid data after all access times are met and remain valid except in cases described in the W
and OE descriptions.
RAS-only refresh
A refresh operation must be performed at least once every 64 ms (128 ms for TMS46x409P) to retain data by
strobing each of the 4096 rows for TMS465409/P or 8192 rows for TMS464409/P. A normal read or write cycle
refreshes all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high
(inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally
generated addresses must be used for a RAS-only refresh.
POST OFFICE BOX 1443
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5
PRODUCT PREVIEW
address: A0 – A11 ( TMS465409/P) and A0 – A12 (TMS464409/P)
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
hidden refresh
A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by
holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a
RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally.
CAS-before-RAS ( CBR) refresh
CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after
RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS.
The external address is ignored, and the refresh address is generated internally.
battery-backup refresh
A low-power battery-backup refresh mode that requires less than 250 mA of refresh current is available on the
TMS464409P and TMS465409P. Data integrity is maintained using CBR refresh with a period of 31.25 ms while
holding RAS low for less than 300 ns. To minimize current consumption, all input levels must be at LVCMOS
levels (VIL < 0.2 V, VIH > VCC – 0.2 V).
PRODUCT PREVIEW
self-refresh (TMS46x409P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 ms. The chip is then refreshed internally by an on-board oscillator. No external
address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode,
both RAS and CAS are brought high to satisfy tCHS. Upon exiting self-refresh mode, a burst refresh (refreshes
a full set of row addresses) must be executed before continuing with normal operation. The burst refresh
ensures the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh
( RAS-only or CBR ) cycle.
test mode
The test mode (see Figure 1) is initiated with a CBR-refresh cycle while simultaneously holding the W input low.
The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or
write on subsequent cycles. While in the test mode, any data sequence can be performed. The device exits test
mode if a CBR refresh cycle with W held high or a RAS-only refresh cycle is performed.
In the test mode, the device is configured as 1024K bits × 4 bits for each DQ. Each DQ pin has a separate 4-bit
parallel read and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal
bits are compared for each DQ pin. If the four bits agree, DQ goes high; if not, DQ goes low. During a write cycle,
the data states of all four DQs must be the same to ensure proper function of the test mode. Test time is reduced
by a factor of four for this series.
6
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
test mode (continued)
Exit Cycle
Entry Cycle
Test Mode Cycle
Normal
Mode
RAS
CAS
W
NOTE A: The states of W, data in, and address are defined by the type of cycle used during test mode.
PRODUCT PREVIEW
Figure 1. Test-Mode Cycle
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
7
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range on VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
PRODUCT PREVIEW
recommended operating conditions
MIN
NOM
MAX
VCC
VIH
Supply voltage
3
3.3
3.6
V
High-level input voltage
2
V
VIL
Low-level input voltage (see Note 2)
VCC + 0.3
0.8
TA
Operating free-air temperature
70
°C
– 0.3
0
UNIT
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic voltage levels only.
8
POST OFFICE BOX 1443
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TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TMS464409/P
TEST CONDITIONS†
’464409-40
’464409P-40
’464409-50
’464409P-50
’464409-60
’464409P-60
MIN
MIN
MIN
MAX
High-level
g
output voltage
IOH = – 2 mA
IOH = – 100 µA
LVTTL
VOL
Low-level
output voltage
IOL = 2 mA
IOL = 100 µA
LVTTL
0.4
0.4
0.4
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VCC = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
IO
Output current
(leakage)
VCC = 3.6 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
ICC1‡§
Average reador write-cycle
current
VCC = 3.6 V,
Minimum cycle
125
100
90
mA
1
1
1
mA
’464409
500
500
500
µA
’464409P
150
150
150
µA
Average
standby current
LVCMOS
After one memory cycle,
RAS and CAS high,
VIH = 2 V (LVTTL)
After one memory cycle,
RAS and CAS high,
g ,
VIH = VCC – 0.2 V
(LVCMOS)
2.4
UNIT
MAX
VOH
ICC2
2.4
MAX
VCC – 0.2
2.4
VCC – 0.2
V
VCC – 0.2
V
ICC3§
Average
RAS-only
refresh current
VCC = 3.6 V,
RAS cycling,
Minimum cycle,
CAS high (RAS only)
125
100
90
mA
ICC4‡¶
Average EDO
current
VCC = 3.6 V,
RAS low,
tPC = minimum,
CAS cycling
140
110
90
mA
ICC5
Average CBR
refresh current
VCC = 3.6 V,
Minimum cycle,
RAS low after CAS low
160
130
110
mA
ICC6#
Average
self-refresh
current
CAS < 0.2 V,
RAS < 0.2 V,
Measured after tRASS minimum
300
300
300
µA
ICC10#
Average
battery-backup
operating
current,
CBR only
tRAS ≤ 300 ns, tRC = 31.25 ms
VCC – 0.2 V ≤ VIH ≤ 3.9 V,
0 V ≤ VIL ≤ 0.2 V,
W and OE = VIH,
Address and data stable
400
400
400
µA
PRODUCT PREVIEW
PARAMETER
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change per EDO cycle, tHPC
# For TMS464409P only
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
9
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
TMS465409/P
PRODUCT PREVIEW
PARAMETER
TEST CONDITIONS†
’465409-40
’465409P-40
’465409-50
’465409P-50
’465409-60
’465409P-60
MIN
MIN
MIN
MAX
High-level
g
output voltage
IOH = – 2 mA
IOH = – 100 µA
LVTTL
VOL
Low-level
output voltage
IOL = 2 mA
IOL = 100 µA
LVTTL
0.4
0.4
0.4
LVCMOS
0.2
0.2
0.2
II
Input current
(leakage)
VCC = 3.6 V,
VI = 0 V to 3.9 V,
All others = 0 V to VCC
± 10
± 10
± 10
µA
IO
Output current
(leakage)
VCC = 3.6 V,
CAS high
VO = 0 V to VCC,
± 10
± 10
± 10
µA
ICC1‡§
Average reador write-cycle
current
VCC = 3.6 V,
Minimum cycle
160
130
110
mA
1
1
1
mA
’465409
500
500
500
µA
’465409P
150
150
150
µA
ICC2
Average
standby current
After one memory cycle,
RAS and CAS high,
VIH = 2 V (LVTTL)
After one memory cycle,
RAS and CAS high,
g ,
VIH = VCC – 0.2 V
(LVCMOS)
2.4
UNIT
MAX
VOH
LVCMOS
2.4
MAX
VCC – 0.2
2.4
VCC – 0.2
V
VCC – 0.2
V
ICC3§
Average
RAS-only
refresh current
VCC = 3.6 V,
RAS cycling,
Minimum cycle,
CAS high (RAS only)
160
130
110
mA
ICC4‡¶
Average EDO
current
VCC = 3.6 V,
RAS low,
tPC = minimum,
CAS cycling
150
120
100
mA
ICC5
Average CBR
refresh current
VCC = 3.6 V,
Minimum cycle,
RAS low after CAS low
160
130
110
mA
ICC6#
Average
self-refresh
current
CAS < 0.2 V,
RAS < 0.2 V,
Measured after tRASS minimum
300
300
300
µA
ICC10#
Average
battery-backup
operating
current,
CBR only
tRAS ≤ 300 ns, tRC = 31.25 ms
VCC – 0.2 V ≤ VIH ≤ 3.9 V,
0 V ≤ VIL ≤ 0.2 V,
W and OE = VIH,
Address and data stable
400
400
400
µA
† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.
‡ Measured with outputs open
§ Measured with a maximum of one address change while RAS = VIL
¶ Measured with a maximum of one address change per EDO cycle, tHPC
# For TMS465409P only
10
POST OFFICE BOX 1443
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TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, A0 – A12†
5
pF
Ci(OE)
Input capacitance, OE
7
pF
Ci(RC)
Input capacitance, CAS and RAS
7
pF
Ci(W)
Input capacitance, W
Output capacitance‡
7
pF
7
pF
Co
† A12 is NC (no internal connection) for TMS465409 and TMS465409P.
‡ CAS and OE = VIH to disable outputs
NOTE 3: VCC = 3.3 V ± 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
MIN
MAX
’46x409-50
’46x409P-50
MIN
MAX
’46x409-60
’46x409P-60
MIN
UNIT
MAX
tAA
tCAC
Access time from column address (see Note 5)
20
25
30
ns
tCPA
tRAC
Access time from CAS (see Note 5)
11
13
15
ns
Access time from CAS precharge (see Note 5)
22
28
35
ns
tOEA
tCLZ
Access time from RAS (see Note 5)
40
50
60
ns
Access time from OE (see Note 5)
11
13
15
Delay time, CAS to output in low impedance
0
ns
tREZ
tCEZ
Output buffer turn off delay from RAS (see Note 6)
3
11
3
13
3
15
ns
Output buffer turn off delay from CAS (see Note 6)
3
11
3
13
3
15
ns
tOEZ
tWEZ
Output buffer turn off delay from OE (see Note 6)
3
11
3
13
3
15
ns
Output buffer turn off delay from W (see Note 6)
3
11
3
13
3
15
ns
0
0
ns
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
5. Access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V.
6. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the output is no longer driven. Data in should not be driven
until one of the applicable maximum specs is satisfied.
EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’46x409-40
’46x409P-40
MIN
MAX
’46x409-50
’46x409P-50
MIN
MAX
’46x409-60
’46x409P-60
MIN
UNIT
MAX
tHPC
tPRWC
Cycle time, EDO page mode, read-write
16
20
25
ns
Cycle time, EDO read-write
47
57
68
ns
tCSH
tCHO
Delay time, RAS active to CAS precharge
32
40
48
ns
Hold time, OE from CAS
5
5
5
ns
tDOH
tCAS
Hold time, output from CAS
5
Pulse duration, CAS active (see Note 7)
6
tWPE
tOCH
Pulse duration, W active (output disable only)
5
5
Setup time, OE before CAS
5
tCP
tOEP
Pulse duration, CAS precharge
6
Precharge time, OE
5
5
10 000
8
5
10 000
10
ns
10 000
ns
5
ns
5
5
ns
8
10
ns
5
5
ns
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
7. In a read-write cycle, tCWD and tCWL must be observed.
POST OFFICE BOX 1443
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11
PRODUCT PREVIEW
’46x409-40
’46x409P-40
PARAMETER
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PRODUCT PREVIEW
timing requirements (see Note 4)
’46x409-40
’46x409P-40
’46x409-50
’46x409P-50
’46x409-60
’46x409P-60
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tRC
tRWC
Cycle time, random read or write
69
84
104
ns
Cycle time, read-write
92
111
135
ns
tRASP
tRAS
Pulse duration, RAS active, fast page mode (see Note 8)
40 100 000
50 100 000
60 100 000
ns
Pulse duration, RAS active, non-page mode (see Note 8)
40
50
60
ns
tRP
tWP
Pulse duration, RAS precharge
25
30
40
ns
Pulse duration, write command
6
8
10
ns
tRASS
tRPS
Pulse duration, RAS active, self refresh (see Note 9)
100
100
100
ms
70
90
110
ns
tASC
tASR
Setup time, column address
0
0
0
ns
Setup time, row address
0
0
0
ns
tDS
tRCS
Setup time, data in (see Note 9)
0
0
0
ns
Setup time, read command
0
0
0
ns
tCWL
tRWL
Setup time, write command before CAS precharge
6
8
10
ns
Setup time, write command before RAS precharge
6
8
10
ns
Setup time, write command before CAS active
(early-write only)
0
0
0
ns
tWRP
tWTS
Setup time, W high before RAS low (CBR refresh only)
5
5
5
ns
Setup time, W low before RAS low (test mode only)
5
5
5
ns
tCSR
tCAH
Setup time, CAS referenced to RAS ( CBR refresh only )
5
5
5
ns
Hold time, column address
6
8
10
ns
tDH
tRAH
Hold time, data in (see Note 10)
6
8
10
ns
Hold time, row address
6
8
10
ns
tRCH
tRRH
Hold time, read command referenced to CAS (see Note 11)
0
0
0
ns
Hold time, read command referenced to RAS (see Note 11)
0
0
0
ns
Hold time, write command during CAS active
( early-write only )
6
8
10
ns
tROH
tWRH
Hold time, RAS referenced to OE
6
8
10
ns
Hold time, W high after RAS low (CBR refresh)
6
8
10
ns
tWTH
tCHR
Hold time, W low after RAS low (test mode only)
6
8
10
ns
Hold time, CAS referenced to RAS (CBR refresh only )
6
8
10
ns
tOEH
tCHS
Hold time, OE command
tWCS
tWCH
Pulse duration, RAS precharge after self refresh
Hold time, CAS active after RAS precharge (self-refresh)
10 000
10 000
10 000
11
13
15
ns
–50
–50
–50
ns
tRHCP Hold time, RAS active from CAS precharge
22
28
35
ns
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
8. In a read-write cycle, tRWD and tRWL must be observed.
9. During the period of 10 ms
tRASS
100 ms, the device is in transition state from normal operation mode to self-refresh mode.
10. Referenced to the later of CAS or W in write operations
11. Either tRRH or tRCH must be satisfied for a read cycle.
12
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
timing requirements (see Note 4) (continued)
’46x409-40
’46x409P-40
’46x409-50
’46x409P-50
’46x409-60
’46x409P-60
MIN
MIN
MIN
MAX
UNIT
MAX
Delay time, column address to write command
( read-write only )
35
42
49
ns
tCPW
tCRP
Delay time, W low after xCAS precharge (read-write only)
37
45
54
ns
5
5
5
ns
tCWD
tOED
Delay time, CAS to write command ( read-write only )
26
30
34
ns
Delay time, OE to data in
11
tRAD
tRAL
Delay time, RAS to column address (see Note 12)
Delay time, column address to RAS precharge
20
tCAL
tRCD
Delay time, column address to CAS precharge
12
Delay time, RAS to CAS ( see Note 12)
10
tRPC
Delay time, RAS precharge to CAS
5
5
5
ns
tRSH
Delay time, CAS active to RAS precharge
6
8
10
ns
tRWD
Delay time, RAS to write command (read-write only)
55
67
79
ns
tTAA
Access time from address (test mode)
25
30
35
ns
tTCPA
Access time, from column precharge (test mode)
30
35
40
ns
tTRAC
Access time, from RAS (test mode)
45
55
65
ns
tT
Transition time
tAWD
Delay time, CAS precharge to RAS
8
1
’46x409
tREF
13
20
10
15
25
25
50
12
1
ns
30
30
15
29
12
ns
18
37
50
14
1
ns
ns
45
ns
50
ns
64
64
64
ms
128
128
128
ms
PRODUCT PREVIEW
MAX
Refresh time interval
’46x409P
NOTES: 4. With ac parameters, it is assumed that tT = 2 ns.
12. The maximum value is specified only to ensure access time.
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13
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
1.4 V
3.3 V
500 W
1178 W
Output Under Test
Output Under Test
CL = 100 pF
(see Note A)
CL = 100 pF
(see Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: CL includes probe and fixture capacitance.
PRODUCT PREVIEW
Figure 2. Load Circuits for Timing Parameters
14
868 W
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TMS464409, TMS464409P, TMS465409, TMS465409P
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tCSH
tRCD
tRSH
tCRP
tCAS
tASR
CAS
tRAD
tCP
tASC
tRAH
Row
Don’t Care
Column
tRCS
tRRH
tRCH
tCAH
W
Don’t Care
Don’t Care
tCAC
tCEZ
tREZ
tAA
DQ1 – DQ4
PRODUCT PREVIEW
Address
tCAL
tRAL
Hi-Z
Valid Data Out
See Note A
tCLZ
tRAC
tWEZ
tOEA
tWPE
tOEZ
tROH
OE
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 3. Read-Cycle Timing
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15
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCSH
tCAS
tASR
CAS
tCP
tASC
tCAL
tRAL
tRAH
PRODUCT PREVIEW
Address
tCAH
Row
Don’t Care
Column
tCWL
tRAD
tRWL
tWCH
W
tWCS
Don’t Care
Don’t Care
tDH
tDS
DQ1 – DQ4
Don’t Care
Valid Data
Don’t Care
OE
Figure 4. Early-Write-Cycle Timing
16
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tRP
tT
tRSH
tRCD
tCRP
tCAS
tCSH
tASR
tASC
CAS
tCP
tRAL
PRODUCT PREVIEW
tCAL
tRAH
tCAH
Address
Row
Don’t Care
Column
tCWL
tRAD
W
tDS
tRWL
Don’t Care
Don’t Care
tWP
tCLZ
tDH
Don’t Care
Valid Data In
DQ1 – DQ4
Invalid Data Out
tOED
tOEH
OE
Don’t Care
Don’t Care
Figure 5. Write-Cycle Timing
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17
TMS464409, TMS464409P, TMS465409, TMS465409P
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRWC
tRAS
RAS
tRP
tT
tCRP
tRCD
tCAS
tASR
CAS
tCP
tRAH
tCAH
tRAD
Address
tT
tASC
Row
Don’t Care
Column
tCWL
tRCS
tRWL
PRODUCT PREVIEW
tRWD
tWP
Don’t Care
W
tAWD
tCWD
tCAC
tDS
tAA
tDH
tCLZ
DQ1 – DQ4
Hi-Z
Data
Out
See Note A
tRAC
Data
In
tOEZ
tOEA
tOED
OE
Don’t Care
tOEH
Don’t Care
Don’t Care
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 6. Read-Write-Cycle Timing
18
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TMS464409, TMS464409P, TMS465409, TMS465409P
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRASP
RAS
tT
tRCD
tCSH
tCRP
tHPC
tCAS
CAS
tRP
tRHCP
tRSH
tCP
tRAH
tASC
tCAL
tASR
tRAL
Address
Row
Column #1
Column #2
Column #3
tRAD
tRCH
tOEA
OE
tRCS
tCAC
tRRH
tDOH
W
tCAC
tAA
(see Note B)
tCPA
tAA
tRAC
tCEZ
(see Note C
tREZ
tCLZ
DQ1 – DQ4
(see Note A)
Data #1
Data #2
Data #3
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. Access time is tCPA-, tAA-, or tCAC-dependent.
C. Output is turned off by tCEZ if RAS goes high during CAS low.
Figure 7. EDO Read Cycle
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19
PRODUCT PREVIEW
tCAH
TMS464409, TMS464409P, TMS465409, TMS465409P
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DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRHCP
tHPC
tCP
tCAS
tRSH
tASR
CAS
tRAH
tASC
tCAL
tCAH
Row
Address
tRAL
Column #1
Column #2
Column #3
tRAD
PRODUCT PREVIEW
tOCH
tCHO
tOEP
tOEP
OE
tOEA
tRRH
tRCS
tRCH
tOEA
W
tCAC
tDOH
tCLZ
tOEZ
tCAC
tAA
DQ1 – DQ4
tREZ
tOEZ
tRAC
tAA
Data #1
Data #1
Data #2
NOTE A: Output is turned off by tCEZ if RAS goes high during CAS low.
Figure 8. EDO Read-Cycle With OE Control
20
(see Note A)
tCEZ
tCPA
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Data #3
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRASP
RAS
tCSH
tRHCP
tHPC
tCP
tASR
tRAH
tASC
Address
tCRP
tRSH
tCAS
CAS
tRP
Row
tCAH
tRAL
tCAL
Column #1
Column #2
Column #3
tRAD
tOEA
PRODUCT PREVIEW
OE
tCAC
tRCS
tCAC
tWPE
tRCH
tRRH
W
tDOH
tCAC
tWEZ
tAA
tCLZ
tRAC
DQ1 – DQ4
tCPA
tCPA
tAA
Data #1
tCEZ
tAA
tREZ
Data #2
Data #3
Figure 9. EDO Read-Cycle With W Control
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21
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tRCD
tHPC
tCAS
tASC
CAS
tRAH
tCP
tCAH
tASR
Address
tRAL
tCAL
Row
Column
Column
tCWL
PRODUCT PREVIEW
tCRP
tRSH
Don’t Care
tCWL
tRAD
tWCH
tRWL
tWCS
W
Don’t Care
Don’t Care
Don’t Care
tDH
tDS
DQ1 – DQ4
Data In
Data In
Don’t Care
Don’t Care
OE
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 10. EDO Early-Write-Cycle Timing (see Note A)
22
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16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
tRHCP
RAS
tCSH
tHPC
tCRP
tRSH
tRCD
tCAL
tCAS
tASC
CAS
tRAH
tCP
Row
tRAD
tCWL
tCWL
tRWL
tWP
tDS
W
Don’t Care
Don’t Care
Don’t Care
Don’t Care
tOEH
tDH
DQ1 – DQ4
Don’t Care
Column
Column
PRODUCT PREVIEW
Address
tRAL
tCAH
tASR
tCLZ
Valid
In
Valid Data In
Don’t Care
Invalid Data out
tOEH
tOED
Don’t Care
OE
Don’t Care
NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated.
Figure 11. EDO Write-Cycle Timing (see Note A)
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23
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRP
tRASP
RAS
tCSH
tRSH
tPRWC
tRCD
tCAS
tASR
tASC
CAS
tCAL
tCAH
tRAL
tRAD
Row
Address
tCRP
tCP
Column 2
Column 1
Don’t Care
tRAH
tCWL
tCWD
tCPW
PRODUCT PREVIEW
tAWD
tRWL
tWP
tRWD
W
tRCS
tCPA
tAA
tDH
tRAC
Valid Out 2
(See Note A)
tDS
tCAC
Valid
In 1
DQ1 – DQ4
tCLZ
tOEA
tOEH
Valid
In 2
Valid
Out 1
tOEZ
tOED
tOEH
OE
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated.
Figure 12. EDO Read-Write-Cycle Timing (see Note B)
24
POST OFFICE BOX 1443
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TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRAS
RAS
tCRP
tRP
tT
CAS
Don’t Care
tRPC
tRAH
tASR
Don’t Care
Row
Don’t Care
Row
Don’t Care
W
PRODUCT PREVIEW
Address
Hi Z
Don’t Care
OE
Figure 13. RAS-Only Refresh-Cycle Timing
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25
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWRP
tWRH
PRODUCT PREVIEW
W
Address
Don’t Care
OE
Don’t Care
DQ1 – DQ4
Hi-Z
Figure 14. Automatic-CBR-Refresh-Cycle Timing
26
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TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRASS
RAS
tRPC
tRPS
tCSR
tCHS
CAS
tCP
Address
Don’t Care
PRODUCT PREVIEW
tWRP
tWRH
W
Don’t Care
OE
Don’t Care
DQ1 – DQ4
Hi-Z
Figure 15. Self-Refresh-Cycle Timing
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27
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
Memory Cycle
tRP
tRP
tRAS
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
PRODUCT PREVIEW
tASR
Address
Row
Col
Don’t Care
tWRH
tWRP
tWRH
tRRH
tWRP
W
tRAC
tREZ
tCAC
tCEZ
tAA
tWEZ
Valid Data Out
DQ1 – DQ4
tCLZ
tOEZ
tOEA
OE
Figure 16. Hidden-Refresh-Cycle (Read) Timing
28
tWRH
tWRP
tRCS
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TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
tRP
tRAS
tRP
tRAS
RAS
tCHR
tCAS
CAS
tCAH
tASC
tRAH
tASR
Don’t Care
Col
PRODUCT PREVIEW
Row
Address
tWRH
tWRP
tWCS
tWP
W
tWCH
tDH
tDS
DQ1 – DQ4
Don’t Care
Valid Data
Don’t Care
OE
Figure 17. Hidden-Refresh-Cycle (Write) Timing
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29
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
tRC
tRP
tRAS
RAS
tCSR
tCHR
tRPC
tT
CAS
tWTH
tWTS
Don’t Care
PRODUCT PREVIEW
W
Address
Don’t Care
OE
Don’t Care
DQ1 – DQ4
Hi-Z
Figure 18. Test-Mode-Entry-Cycle Timing
tRC
tRP
tRAS
RAS
tCSR
tRPC
tCHR
tT
CAS
tWRP
W
Don’t Care
Don’t Care
tWRH
Address
Don’t Care
tREZ
tCEZ
DQ1 – DQ4
Hi-Z
Don’t Care
Figure 19. Test-Mode-Exit-Cycle CBR-Refresh-Cycle Timing
30
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16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
MECHANICAL DATA
DGC (R-PDSO-G32)
PLASTIC SMALL-OUTLINE PACKAGE
0.020 (0,50)
0.012 (0,30)
0.050 (1,27)
32
0.008 (0,20) M
17
0.471 (11,96)
0.455 (11,56)
0.404 (10,26)
0.396 (10,06)
1
16
PRODUCT PREVIEW
0.006 (0,15) NOM
Gage Plane
0.829 (21,05)
0.821 (20,85)
0.010 (0,25)
0°– 5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.047 (1,20) MAX
0.000 (0,00) MIN
0.004 (0,10)
4040260-3 / B 02/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
device symbolization (TMS464409 illustrated)
-SS
TI
Speed ( - 40, - 50, - 60)
Low-Power / Self-Refresh Designator (Blank or P)
TMS464409 DGC
Package Code
W
A
Y
M LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
31
TMS464409, TMS464409P, TMS465409, TMS465409P
16 777 216 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
PRODUCT PREVIEW
SMKS895A – MAY 1997 – REVISED OCTOBER 1997
32
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
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