STMICROELECTRONICS TDA7407D

TDA7407D
ADVANCED CAR SIGNAL PROCESSOR
1
■
FEATURES
Figure 1. Package
FULLY INTEGRATED SIGNAL PROCESSOR
OPTIMIZED FOR CAR RADIO
APPLICATIONS
)
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2 DESCRIPTION
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FULLY PROGRAMMABLE BY I2C BUS
INCLUDES AUDIOPROCESSOR, STEREO DECODER WITH NOISE BLANKER AND
MULTIPATH DETECTOR
PROGRAMMABLE ROLL-OFF
COMPENSATION
NO EXTERNAL COMPONENTS
The TDA7407D is the newcomer of the CSP family
introduced by TDA7460/61. It uses the same innovative concepts and design technologies allowing
fully software programmability through I2C bus
and overall cost optimisation for the system designer.
SO28
Table 1. Order Codes
Part Number
Package
TDA7407D
SO28
TDA7407DTR
SO28 in Tape & Reel
The device includes a three band audioprocessor
with configurable inputs and absence of external
components for filter settings, a last generation
stereodecoder with multipath detector and a sophisticated stereoblend and noise cancellation circuitry.Strength points of the CSP approach are
flexibility and overall cost/room saving in the application, combined with high performances.
Figure 2. BLOCK DIAGRAM
April 2005
Rev. 1
1/34
TDA7407D
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
VS
Parameter
Operating Supply Voltage
Value
Unit
10.5
V
Tamb
Operating Ambient Temperature Range
-40 to 85
°C
Tstg
Operating Storage Temperature Range
-55 to 150
°C
Table 3. SUPPLY
Symbol
Parameter
VS
Supply Voltage
IS
Supply Current
Test Condition
Min.
Typ.
Max.
7.5
9
10
V
30
35
40
mA
VS = 9V
Unit
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SVRR
Ripple Rejection @ 1KHz
Audioprocessor (all filters flat)
50
60
dB
Stereodecoder + Audioprocessor
45
55
dB
Value
Unit
85
°C/W
All pins are protected against ESD according to the MIL883 standard.
Figure 3. PIN CONNECTION (Top view)
VREF
1
28
ACOUTL
CREF
2
27
ACOUTR
CassL
3
26
OUT LF
CassR
4
25
OUT RF
CDR
5
24
OUT LR
CDGND
6
23
OUT RR
CDL
7
22
VDD
Ph
8
21
GND
AFS
9
20
SDA
AM
10
19
SCL
MPX
11
18
SMUTE
LEVEL
12
17
QUAL
MPIN
13
16
MUX R
MPOUT
14
15
MUX L
pincon_TDA7407d
Table 4. THERMAL DATA
Symbol
Rth-j pins
2/34
Parameter
Thermal Resistance Junction to pins
Max
TDA7407D
Table 5. PIN DESCRIPTION
N.
Name
Function
Type
1
VREF
Reference Voltage Output
I
2
CREF
Reference Capacitor Pin
S
3
TAPEL
Tape Input Left
I
4
TAPER
Tape Input Right
I
5
CDR
CD Right Channel Input
I
6
CDGND
CD Input Common Ground
I
7
CDL
CD Input Left Channel
I
8
PH
Phone Input
I
9
AFS
AFS Drive
I
10
AM
AM Input
I
11
MPX
FM Stereodecoder Input
I
12
LEVEL
Level Input Stereodecoder
I
13
MPIN
Multipath Input
I
14
MPOUT
Multipath Output
O
15
MUXL
Multiplexer Output Left Channel
O
16
MUXR
Multiplexer Output Right Channel
O
17
QUAL
Stereodecoder Quality Output
O
18
SMUTE
Soft Mute Drive
I
19
SCL
I2C Clock Line
I
20
SDA
I2C Data Line
I/O
21
GND
Supply Ground
S
22
VS
Supply Voltage
S
23
OUTRR
Right Rear Speaker Output
O
24
OUTLR
Left Rear Speaker Output
O
25
OUTRF
Right Front Spaeaker Output
O
26
OUTLF
Left Front Speaker Output
O
27
ACOUTR
Pre-speaker AC Output Right Channel
O
28
ACOUTL
Pre-speaker AC Output Left Channel
O
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Pin type legenda: I = Input O = Output I/O = Input/Output S = Supply nc = not connected
3/34
TDA7407D
4
AUDIO PROCESSOR PART
4.0.4 Mid Control
4.0.1 Input Multiplexer
■
Quasi-differential CD and cassette stereo input
■
2nd order frequency response
■
AM mono input
■
Q-factor programmable in 2 steps
■
Phone inverting input
■
Center frequency programmable in 4 steps
■
Multiplexer signal after In-Gain available at
separate pins
■
±15 x1dB steps
4.0.5 Treble Control
– 2nd order frequency response
4.0.2 Volume control
■
1dB attenuator
– Center frequency programmable in 4 steps
Max. gain 15dB
– ±15 x 1dB steps
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Max. attenuation 79dB
■
4.0.6 Speaker Control
4.0.3 Bass Control
■
■
■
4 independent speaker controls in 1dB steps
2nd order frequency response
■
max gain 15dB
Q-factor programmable in 4 steps
■
max. attenuation 79dB
Center frequency programmable in 4(5) steps
■
4.0.7 Mute Functions
DC gain programmable
■
±15 x 1dB steps
■
■
Direct mute
■
Digitally controlled softmute with 4
programmable mute time.
4.1 ELECTRICAL CHARACTERISTICS
Table 6. Electrical Characteristics
(VS = 9V; Tamb = 25°C; RL = 10KΩ; all gains = 0dB; f = 1KHz; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
70
100
130
KΩ
INPUT SELECTOR
Rin
Input Resistance
VCL
Clipping Level
2.2
2.6
VRMS
SIN
Input Separation
80
100
dB
GIN MIN
Min. Input Gain
-1
0
1
dB
GIN MAX
Max. Input Gain
13
15
17
dB
GSTEP
Step Resolution
0.5
1
1.5
dB
Adjacent Gain Step
-5
0.5
5
mV
GMIN to GMAX
-10
5
10
mV
Differential
70
100
130
KΩ
Common Mode
70
100
130
KΩ
VCM = 1VRMS @ 1KHz
45
70
dB
VCM = 1VRMS @ 10KHz
45
60
dB
VDC
DC Steps
all inputs except Phone
DIFFERENTIAL CD STEREO INPUT
O
Rin
CMRR
eN
Input Resistance
Common Mode Rejection Ratio
Output Noise @ Speaker
Outputs
20Hz to 20KHz flat; all stages 0dB
6
15
mV
PHONE INPUT
Rin
4/34
Input Resistance
40
56
KΩ
TDA7407D
Table 6. Electrical Characteristics (continued)
(VS = 9V; Tamb = 25°C; RL = 10KΩ; all gains = 0dB; f = 1KHz; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
17
dB
VOLUME CONTROL
GMAX
Max Gain
13
15
AMAX
Max Attenuation
70
79
ASTEP
Step Resolution
0.5
1
1.5
dB
G = -20 to 20dB
-1.25
0
1.25
dB
G = -60 to 20dB
-4
0
3
dB
EA
Attenuation Set Error
dB
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ET
VDC
Tracking Error
DC Steps
2
dB
Adjacent Attenuation Steps
0.1
3
mV
From 0dB to GMIN
0.5
5
mV
SOFT MUTE/AFS
AMUTE
TD
Mute Attenuation
Delay Time
VTH low
Low Threshold for SM-/AFSPin1)
VTH high
High Threshold for SM-/AFS-Pin
RPD
80
100
dB
T1
0.48
ms
T2
0.96
ms
T3
40.4
ms
T4
324
ms
1
2.5
Internal Pull-up Resistor
V
V
45
KΩ
BASS CONTROL
CRANGE
ASTEP
fC
QBASS
O
DCGAIN
Control Range
±13
±15
±17
dB
Step Resolution
0.5
1
1.5
dB
fC1
54
60
66
Hz
fC2
63
70
77
Hz
fC3
72
80
88
Hz
fC4
90
100
(150)(2)
110
Hz
Q1
0.9
1
1.1
Q2
1.1
1.25
1.4
Q3
1.3
1.5
1.7
Q4
1.8
2
2.2
DC = off
-1
0
1
dB
DC = on
3.5
4.4
5.5
dB
Control Range
±13
±15
±17
dB
Step Resolution
0.5
1
1.5
dB
Center Frequency
Quality Factor
Bass-Dc-Gain
MID CONTROL
CRANGE
ASTEP
5/34
TDA7407D
Table 6. Electrical Characteristics (continued)
(VS = 9V; Tamb = 25°C; RL = 10KΩ; all gains = 0dB; f = 1KHz; unless otherwise specified)
Symbol
fC
QMID
Parameter
Center Frequency
Quality Factor
Test Condition
Min.
Typ.
Max.
Unit
fC1
450
500
550
Hz
fC2
0.9
1
1.1
kHz
fC3
1.35
1.5
1.65
kHz
fC4
1.8
2
2.2
kHz
Q1
0.9
1
1.1
Q2
1.8
2
2.2
)
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TREBLE CONTROL
CRANGE
Control Range
±13
±15
±17
dB
Step Resolution
0.5
1
1.5
dB
fC1
8
10
12
KHz
fC2
10
12.5
15
KHz
fC3
12
15
18
KHz
fC4
14
17.5
21
KHz
Input Impedance
35
50
65
KΩ
GMAX
Max Gain
13
15
17
dB
AMAX
Max Attenuation
-70
-79
ASTEP
Step Resolution
0.5
1
AMUTE
Output Mute Attenuation
80
90
ASTEP
fC
Center Frequency
SPEAKER ATTENUATORS
RIN
EE
VDC
Attenuation Set Error
DC Steps
Adjacent Attenuation Steps
0.1
dB
1.5
dB
dB
±2
dB
5
mV
AUDIO OUTPUTS
VCLIP
Clipping Level
RL
Output Load Resistance
CL
Output Load Capacitance
ROUT
Output Impedance
VDC
DC Voltage Level
d = 0.3%
2.2
VRMS
2.6
2
KΩ
10
nF
30
120
Ω
4.5
4.7
V
BW = 20 Hz to 20 KHz
output muted
3
15
µV
BW = 20 Hz to 20 KHz
all gain = 0dB
6.5
15
µV
4.3
GENERAL
eNO
O
S/N
d
6/34
Output Noise
Signal to Noise Ratio
Distortion
all gain = 0dB flat; VO = 2VRMS
102
110
dB
bass treble at 12dB;
a-weighted; VO = 2.6VRMS
96
100
dB
VIN = 1VRMS; all stages 0dB
0.002
0.1
%
VIN = 1VRMS; Bass & Treble =
12dB
0.05
0.1
%
TDA7407D
Table 6. Electrical Characteristics (continued)
(VS = 9V; Tamb = 25°C; RL = 10KΩ; all gains = 0dB; f = 1KHz; unless otherwise specified)
Symbol
Parameter
SC
Channel separation Left/Right
ET
Total Tracking Error
Test Condition
Min.
Typ.
Max.
Unit
80
100
AV = 0 to -20dB
-1
0
1
dB
AV = -20 to -60dB
-2
0
2
dB
0.8
V
dB
BUS INPUTS
VIL
Input Low Voltage
VIH
Input High Voltage
d = 0.3%
2.5
V
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IIN
Input Current
VIN = 0.4V
VO
Output Voltage SDA
IO = 1.6mA
-5
5
µA
0.4
V
1) The SM pin is active low (Mute = 0)
2) See note in Programming Part
4.2 STEREODECODER PART.
Table 7. Electrical Characteristics
(VS = 9V; deemphasis time constant = 50µs,VMPX = 500mV(75KHz deviation), fm= 1KHz, Gv = 6dB,
Tamb = 25°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vin
MPX Input Level
0.5
1.25
VRMS
Rin
Input Resistance
70
100
130
KΩ
GMIN
Min. Input Gain
1.5
3.5
4.5
dB
GMAX
Max. Input Gain
8.5
11
12.5
dB
GSTEP
Step Resolution
1.75
2.5
3.25
dB
SVRR
Supply Voltage Ripple Rejection
α
Max. channel Separation
THD
Total Harmonic Distortion
S+N
-------------N
Signal plus Noise to Noise Ratio
Gv = 3.5dB
Vripple = 100mV; f = 1KHz
35
60
dB
30
50
dB
0.02
A-weighted, S = 2VRMS
80
91
0.3
%
dB
MONO/STEREO-SWITCH
VPTHST1
Pilot Threshold Voltage
for Stereo, PTH = 1
10
15
25
mV
VPTHST0
Pilot Threshold Voltage
for Stereo, PTH = 0
15
25
35
mV
VPTHMO1 Pilot Threshold Voltage
for Mono, PTH = 1
7
12
17
mV
VPTHMO0 Pilot Threshold Voltage
for Mono, PTH = 1
10
19
25
mV
PLL
∆f/f
Capture Range
0.5
%
DEEMPHASIS and HIGHCUT
O
tHC50
Deemphasis Time Constant
Bit 7, Subadr, 10 = 0,
VLEVEL >> VHCH
25
50
75
µs
tHC75
Deemphasis Time Constant
Bit 7, Subadr, 10 = 1,
VLEVEL >> VHCH
50
75
100
µs
tHC50
Highcut Time Constant
Bit 7, Subadr, 10 = 0,
VLEVEL >> VHCL
100
150
200
µs
tHC75
Highcut Time Constant
Bit 7, Subadr, 10 = 1,
VLEVEL >> VHCL
150
225
300
µs
7/34
TDA7407D
Table 7. Electrical Characteristics (continued)
(VS = 9V; deemphasis time constant = 50µs,VMPX = 500mV(75KHz deviation), fm= 1KHz, Gv = 6dB,
Tamb = 25°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
4.7
5
5.3
V
STEREOBLEND-and HIGHCUT-CONTROL
REF5V
Internal Reference Voltage
TCREF5V
Temperature Coefficient
3300
ppm
LGmin
Min. LEVEL Gain
-1
0
1
dB
LGmax
Max. LEVEL Gain
8
10
12
dB
LGstep
LEVEL Gain Step Resolution
0.3
0.67
1
dB
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VSBLmin Min. Voltage for Mono
25
29
33
%REF5V
VSBLmax Min. Voltage for Mono
54
58
62
%REF5V
VSBLstep Step Resolution
2.2
4.2
6.2
%REF5V
VHCHmin Min. Voltage for NO Highcut
38
42
46
%REF5V
VHCHmax Min. Voltage for NO Highcut
62
66
70
%REF5V
VHCHstep Step Resolution
5
8.4
12
%REF5V
VHCLmin Min. Voltage for FULL Highcut
12
17
22
%VHCH
VHCLmax Max. Voltage for FULL Highcut
28
33
38
%VHCH
VHCLstep Step Resolution
2.2
4.2
6.2
%VHCH
40
50
Carrier and harmonic suppression at the output
α19
Pilot Signal f = 19KHz
α38
Subcarrier f = 38KHz
75
dB
α57
Subcarrier f = 57KHz
62
dB
α76
Subcarrier f = 76KHz
90
dB
dB
Intermodulation (Note 1)
α2
fmod = 10KHz, fspur = 1KHz
65
dB
α3
fmod = 13KHz, fspur = 1KHz
75
dB
70
dB
75
dB
Traffic Ratio (Note 2)
α57
Signal f = 57KHz
SCA - Subsidiary Communications Authoorization (Note 3)
α67
Signal f = 67KHz
ACI - Adjacent Channel Interference (Note 4)
α114
Signal f = 114KHz
95
dB
α190
Signal f = 190KHz
84
dB
Notes to the characteristics:
1. Intermodulation Suppression:
O
V O ( signal ) ( at1kHz )
α2 = ------------------------------------------------------ ; fs = (2 x 10kHz) - 19kHz
V O ( spurious ) ( at1kHz )
V O ( signal ) ( at1kHz )
α3 = ------------------------------------------------------ ; fs = (3 x 13kHz) - 38kHz
V O ( spurious ) ( at1kHz )
measured with: 91% pilot signal; fm = 10kHz or 13kHz.
2. Traffic Radio (V.F.) Suppression: measured with: 91% stereo signal; 9% pilot signal; fm=1kHz; 5% sub-
8/34
TDA7407D
carrier (f = 57kHz, fm = 23Hz AM, m = 60%)
V O ( signal ) ( at1kHz )
α57 ( V.W > F. ) = -------------------------------------------------------------------------V O ( spurious ) ( at1kHz ± 23kHz )
3. SCA ( Subsidiary Communications Authorization ) measured with: 81% mono signal; 9% pilot signal;
fm = 1kHz; 10%SCA - subcarrier ( fs = 67kHz, unmodulated ).
V O ( signal ) ( at1kHz )
α67 = ------------------------------------------------------ ; Fs =(2 x 38kHz) - 67kHz
V O ( spurious ) ( at9kHz )
4. ACI ( Adjacent Channel Interference ):
V O ( signal ) ( at1kHz )
α114 = ------------------------------------------------------ ; Fs = 110kHz - (3 x 38kHz)
V O ( spurious ) ( at4kHz )
)
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O
V O ( signal ) ( at1kHz )
α114 = ------------------------------------------------------ ; Fs = 186kHz - (5 x 38kHz)
V O ( spurious ) ( at4kHz )
measured with: 90% mono signal; 9% pilot signal; fm =1kHz; 1% spurious signal( fs = 110kHz or 186kHz,
unmodulated).
■
internal 2nd order 140kHz high pass filter
■
programmable trigger threshold
■
trigger threshold dependent on high frequency noise with programmable gain
■
additional circuits for deviation and fieldstrength dependent trigger adjustment
■
very low offset current during hold time due to opamps wMOS inputs
■
four selectable pulse suppression times
■
programmable noise rectifier charge/discharge current
Table 8. ELECTRICAL CHARACTERISTICS (continued)
Symbol
VTR
Parameter
Trigger Threshold
0) 1)
VTRNOISE Noise Controlled Trigger
Threshold 2)
VRECT
Rectifier Voltage
Test Condition
meas. with VPEAK = 0.9V
meas. with VPEAK = 1.5V
Min.
Typ.
Max.
Unit
NBT = 111
(c)
30
(c)
mVOP
NBT = 110
(c)
35
(c)
mVOP
NBT = 101
(c)
40
(c)
mVOP
NBT = 100
(c)
45
(c)
mVOP
NBT = 011
(c)
50
(c)
mVOP
NBT = 010
(c)
55
(c)
mVOP
NBT = 001
(c)
60
(c)
mVOP
NBT = 000
(c)
65
(c)
mVOP
NCT = 00
(c)
260
(c)
mVOP
NCT = 01
(c)
220
(c)
mVOP
NCT = 10
(c)
180
(c)
mVOP
NCT = 11
(c)
140
(c)
mVOP
6)
0.5
0.9
1.3
V
VMPX = 50mV; f = 150KHz
1.5
1.7
2.1
V
VMPX = 200mV; f = 150KHz
2.2
2.5
2.9
V
VMPX = 0mV
NRD
= 00
9/34
TDA7407D
Table 8. ELECTRICAL CHARACTERISTICS (continued)
Symbol
Parameter
Test Condition
VRECT DEV deviation dependent
rectifier Voltage 3)
VRECT FS Fieldstrength Controlled
Rectifier Voltage 4)
means. with
VMPX = 800mV
(75KHz dev.)
means. with
VMPX = 0mV
VLEVEL << VSBL
(fully mono)
Min.
Typ.
Max.
Unit
OVD = 11
0.5
0.9(off)
1.3
VOP
OVD = 10
0.9
1.2
1.5
VOP
OVD = 01
1.7
2.0
2.3
VOP
OVD = 00
2.5
2.8
3.1
VOP
FSC = 11
0.5
0.9(off)
1.3
V
FSC = 10
0.9
1.4
1.5
V
FSC = 01
1.7
1.9
2.3
V
FSC = 00
2.1
2.4
3.1
V
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TS
Suppression Pulse
Duration 5)
Signal HOLDNin Testmode
VRECTADJ Noise Rectifier discharge
adjustment 6)
SRPEAK
VADJMP
Noise Rectifier Charge
Noise Rectifier adjustment
through Multipath 8)
Signal PEAK in Testmode
Signal PEAK in Testmode
Signal PEAK in Testmode
BLT = 00
TBD
38
TBD
µs
BLT = 10
TBD
32
TBD
µs
BLT = 01
TBD
25.5
TBD
µs
BLT = 00
TBD
22
TBD
µs
NRD = 00
6)
(c)
0.3
(c)
V/ms
NRD = 01
6)
(c)
0.8
(c)
V/ms
NRD = 10
6)
(c)
1.3
(c)
V/ms
NRD = 11
6)
(c)
2.0
(c)
V/ms
PCH = 0
7)
(c)
10
(c)
mV/µs
PCH = 1
7)
(c)
20
(c)
mV/µs
MPNB = 00 8)
(c)
0.3
(c)
V/ms
MPNB = 01 8)
(c)
0.5
(c)
V/ms
MPNB = 10 8)
(c)
0.7
(c)
V/ms
MPNB = 11 8)
(c)
0.9
(c)
V/ms
(c) = by design/characterization functionally guaranteed through dedicated test mode structure
0) All Thresholds are measured using a pulse with TR =2ms, THIGH = 2ms and TF = 10ms. The repetition rate must not increase the PEAK
voltage.
1) NBT represents the Noiseblanker Byte bits D2, D0 for the noise blanker trigger threshold
2) NAT represents the Noiseblanker Byte bit pair D4, D3 for the noise controlled triggeradjustment
3) OVD represents the Noiseblanker Byte bit pair D7, D6 for the over deviation detector
4) FSC represents the Fieldstrength Byte bit pair D1, D0 for the fieldstrength control
5) BLT represents the Speaker RR Byte bit pair D7, D6 for the blanktime adjustment
6) NRD represents the Configuration-Byte bit pair D1, D0 for the noise rectifier discharge-adjustment
7) PCH represents the Stereodecoder-Byte bit D5 for the noise rectifier charge-current adjustment
8) MPNB represents the HighCut-Byte bit D7 and the Fieldstrength-Byte D7 for the noise rectifier multipath adjustment
Figure 4.
O
VIN
VOP
DC
D97AU636
10/34
TR
THIGH
TF
Time
TDA7407D
Figure 5. Trigger Threshold vs.VPEAK
VTH
260mV(00)
220mV(01)
180mV(10)
140mV(11)
MIN. TRIG. THRESHOLD
NOISE CONTROLLED
TRIG. THRESHOLD
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65mV
8 STEPS
30mV
0.9V
VPEAK(V)
1.5V
D97AU648
Figure 6. Deviation Controlled Trigger Adjustment
VPEAK
(VOP)
00
01
2.8
2.0
10
1.2
0.9
DETECTOR OFF (11)
D97AU649
20
32.5
45
DEVIATION(KHz)
75
Figure 7. Fieldstrength Controlled Trigger Adjustment
VPEAK
MONO
O
STEREO
»3V
2.4V(00)
1.9V(01)
1.4V(10)
NOISE
noisy signal
0.9V
ATC_SB OFF (11)
D97AU650
good signal
E'
11/34
TDA7407D
6
MULTIPATH DETECTOR
■
Internal 19kHz band pass filter
■
Programmable band pass and rectifier gain
■
two pin solution fully independent usable for external programming
■
selectable internal influence on Stereoblend
Table 9. ELECTRICAL CHARACTERISTICS (continued)
Symbol
fCMP
Parameter
Test Condition
Min.
Typ.
Max.
19
Unit
Center Frequency of MultipathBandpass
stereodecoder locked on
Pilottono
KHz
Bandpass Gain
bits D2, D1 configuration byte = 00
6
dB
bits D2, D1 configuration byte = 10
12
dB
bits D2, D1 configuration byte = 01
16
dB
bits D2, D1 configuration byte = 11
18
dB
bits D7, D6 configuration byte = 00
7.6
dB
bits D7, D6 configuration byte = 01
4.6
dB
bits D7, D6 configuration byte = 10
0
dB
bits D7, D6 configuration byte = 11
off
dB
bit D5 configuration byte = 0
0.5
µA
bit D5 configuration byte = 1
1.0
µA
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GBPMP
GRECTMP Rectifier Gain
ICHMP
IDISMP
Rectifier Charge Current
Rectifier Discharge Current
0.5
1
1.5
mA
Min.
Typ.
Max.
Unit
Table 10. Quality Detector
Symbol
Parameter
Test Condition
A
Multipath Influence Factor
Addr. 12 / Bit 5+6
00
01
10
11
0.7
0.85
1.00
1.15
dB
dB
dB
dB
B
Noise Influence Factor
Addr. 16 / Bit 1+2
00
01
10
11
15
12
9
6
dB
dB
dB
dB
6.1
DESCRIPTION OF THE AUDIOPROCESSORPART
6.1.1 Input Multiplexer
■
■
O
■
CD quasi differential
Cassette stereo
Phone inverting
■
AM mono
■
Stereodecoder input.
6.1.2 Input stages
Most of the input stages have remained the same as in preceeding ST audioprocessors with exception of
the CD inputs (see figure 8).In the meantime there are some CD players in the market having a significant
high source impedance which affects strongly the common-mode rejection of the normal differential input
stage. The additional buffer of the CD input avoids this drawback and offers the full common-mode rejec12/34
TDA7407D
tion even with those CD players.
The output of the Cd stage is permanently available of the Cd out-pins
6.1.3 AutoZero
In order to reduce the number of pins there is no AC coupling between the In-Gain and the following stage,
so that any offset generated by or before the In-Gain stage would be transferred or even amplified to the
output.
To avoid that effect a special offset cancellation stage called AutoZero is implemented.
This stage is located before the volume-block to eliminate all offsets generated by the Stereodecoder, the
Input Stage and the In-Gain (Please notice that externally generated offsets, e.g. generated through the
leakage current of the coupling capacitors, are not cancelled).
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The auto-zeroing is started every time the DATA-BYTE 0 is selected and takes a time of max. 0.3ms. To
avoid audible clicks the audioprocessor is muted before the volume stage during this time.
6.1.4 AutoZero Remain
In some cases, for example if the µP is executing a refresh cycle of the I2C bus programming, it is not
useful to start a new AutoZero action because no new source is selected and an undesired mute would
appear at the outputs. For such applications the TDA7407D could be switched in the "Auto Zero Remain
mode" (Bit 6 of the subaddress byte). If this bit is set to high, the DATABYTE 0 could be loaded without
invoking the AutoZero and the old adjustment value remains.
6.1.5 Multiplexer Output
The output signal of the Input Multiplexer is available at separate pins (please see the Blockdiagram). This
signal represents the input signal amplifier by the In Gain stage and is also going into the Mixer stage.
6.1.6 Softmute
The digitally controlled softmute stage allows muting/demuting the signal with a I2C bus programmable
slope. The mute process can either be activated by the softmute pin or by the I2C bus. The slope is realized in a special S shaped curve to mute slow in the critical regions (see figure 9).
Figure 8. Input Stages
15K
CD+
15K
1
100K
+
-
15K
CD-
15K
1
100K
27K
28K
+
-
27K
O
28K
IN GAIN
PHONE-
CASSETTE
100K
AM
100K
STEREODECODER
MPX
100K
D98AU854D
13/34
TDA7407D
Figure 9. Softmute Timing
EXT.
MUTE
1
+SIGNAL
REF
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-SIGNAL
1
I2C BUS
OUT
D97AU634
Time
Note: Please notice that a started Mute action is always terminated and could not be interrupted by a change of the mute signal.
For timing purposes the Bit 3 of the I2C bus output register is set to 1 from the start of muting until the end
of demuting.
6.2 BASS
There are four parameters programmable in the bass stage: (see figs 10, 11, 12, 13):
6.2.1 Attenuation
Figure 10 shows the attenuation as a function of frequency at a center frequency at a center frequency of 80Hz.
6.2.2 Center Frequency
Figure 11 shows the four possible center frequencies 60,70,80 and 100Hz.
6.2.3 Quality Factors
Figure 12 shows the four possible quality factors 1, 1.25, 1.5 and 2.
6.2.4 DC Mode
In this mode the DC gain is increased by 5.1dB. In addition the programmed center frequency and quality
factor is decreased by 25% which can be used to reach alternative center frequencies or quality factors.
6.3 MID
There are 3 parameters programmable in the mid stage (see figs. 14, 15 & 16)
O
6.3.1 Attenuation
Figure 14 shows the attenuation as a function of frequency at a center frequency of 1kHz.
6.3.2 Center Frequency
Figure 15 shows the four possible center frequencies 500Hz, 1kHz, 1.5kHz and 2kHz.
6.3.3 Quality Factor
Figure 16 shows the two possible quality factors 1 and 2 at a center frequency of 1kHz.
14/34
TDA7407D
6.4 TREBLE
There are two parameters programmable in the treble stage (see figs 17, 18):
6.4.1 Attenuation
Figure 17 shows the attenuation as a function of frequency at a center frequency of 17.5KHz.
6.4.2 Center Frequency
Figure 15 shows the four possible Center Frequency (10, 12.5, 15 and 17.5kHz).
6.4.3 AC Coupling
In some applications additional signal manipulations are desired, for example surround-sound or moreband-equalizing. For this purpose a AC-Coupling is placed before the Speaker-attenuators, which can be
activated or internally shorted by Bit7 in the Bass/Treble-Configuration byte. In short condition the inputsignal of the speaker-attenuator is available at AC Outputs and the AC Input could be used as additional
stereo inputs. The input impedance of the AC Inputs is always 50KΩ.
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6.4.4 Speaker Attenuator
The speaker attenuators have exactely the same structure and range like the Volume stage.
Figure 10. Bass Control @ fc = 80Hz, Q = 1
Figure 12. Bass Quality factors @ Gain = 14dB,
fc = 80Hz
15.0
15.0
10.0
12.5
5.0
10.0
0.0
7.5
-5.0
5.0
-10.0
2.5
0.0
-15.0
10.0
100.0
1.0K
10.0K
Figure 11. Bass Center @ Gain = 14dB, Q = 1
10.0
100.0
1.0K
10.0K
Figure 13. Bass normal and DC Mode @ Gain =
14dB, fc = 80Hz
15.0
15.0
12.5
12.5
10.0
O
10.0
7.5
7.5
5.0
5.0
2.5
2.5
0.0
0.0
10.0
100.0
1.0K
10.0K
10.0
100.0
1.0K
10.0K
Note: In general the center frequency, Q and DC-mode can be set
independently. The exception from this rule is the mode (5/xx1111xx)
where the center frequency is set to 150Hz instead of 100Hz.
15/34
TDA7407D
Figure 17. Treble Control @ fc = 17.5KHz
Figure 14. Mid Control @ fc=1kHz, Q=1
15.0
15.0
10.0
10.0
5.0
5.0
0.0
0.0
-5.0
-5.0
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-10.0
-10.0
-15.0
10.0
100.0
1.0K
10.0K
15.0
12.5
10.0
7.5
5.0
2.5
0.0
100.0
1.0K
10.0K
Figure 16. Mid Q-factor @ fc=1kHz, Gain=14dB
15.0
12.5
10.0
O
7.5
5.0
2.5
0.0
10.0
16/34
100.0
1.0K
100.0
1.0K
10.0K
Figure 18. Treble Center Frequencies @ Gain =
14dB
Figure 15. Mid Center Frequency @
Gain=14dB, Q1
10.0
-15.0
10.0
10.0K
TDA7407D
6.5 FUNCTIONAL DESCRIPTION OF STEREODECODER
The stereodecoder part of the TDA7407D (see Fig. 19) contains all functions necessary to demodulate
the MPX signal like pilot tone dependent MONO/STEREO switching as well as "stereoblend" and "highcut"
functions.
6.5.1 Stereodecoder Mute
The TDA7407 has a fast and easy to control RDS mute function which is a combination of the audioprocessor's softmute and the high-ohmic mute of the stereodecoder. If the stereodecoder is selected and a
softmute command is sent (or activated through the SM pin) the stereodecoder will be set automatically
to the high-ohmic mute condition after the audio signal has been softmuted.
Hence a checking of alternate frequencies could be performed. To release the system from the mute condition simply the unmute command must be sent: the stereodecoder is unmuted immediately and the audioprocessor is softly unmuted. Fig. 20 shows the output signal VO as well as the internal stereodecoder
mute signal. This influence of Softmute on the stereodecoder mute can be switched off by setting bit 3 of
the Softmute byte to "0". A stereodecoder mute command (bit 0, stereodecoder byte set to "1") will set the
stereodecoder in any case independently to the high-ohmic mute state.
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Figure 19. Block Diagram of the Stereodecoder
Figure 20. Signals During Stereodecoder's Softmute
SOFTMUTE
COMMAND
t
O
STD MUTE
t
VO
D97AU638
t
17/34
TDA7407D
Figure 21. Internal Stereoblend Characteristics
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If any other source than the stereodecoder is selected the decoder remains muted and the MPX pin is
connected to Vref to avoid any discharge of the coupling capacitor through leakage currents.
6.5.2 Ingain + Infilter
The Ingain stage allows to adjust the MPX signal to a magnitude of about 1Vrms internally which is the
recommended value. The 4th order input filter has a corner frequency of 80KHz and is used to attenuate
spikes and nose and acts as an anti allasing filter for the following switch capacitor filters.
6.5.3 Demodulator
In the demodulator block the left and the right channel are separated from the MPX signal. In this stage
also the 19 kHz pilot tone is cancelled. For reaching a high channel separation the TDA7407D offers an
I2C bus programmable roll-off adjustment which is able to compensate the lowpass behaviour of the tuner
section. If the tuner attenuation at 38kHz is in a range from 7.2% to 31.0% the TDA7407D needs no external network in front of the MPX pin. Within this range an adjustment to obtain at least 40dB channel
separation is possible.
The bits for this adjustment are located together with the fieldstrength adjustment in one byte. This gives
the possibility to perform an optimization step during the production of the carradio where the channel separation and the fieldstrength control are trimmed.
6.5.4 Deemphasis and Highcut.
The lowpass filter for the deemphasis allows to choose between a time constant of 50µs and 75µs (bit D7,
Stereodecoder byte).
The highcut control range will be in both cases τHC = 2 · τDeemp. Inside the highcut control range (between
VHCH and VHCL) the LEVEL signal is converted into a 5 bit word which controls the lowpass time constant between τDeemp...3 · τDeemp. There by the resolution will remain always 5 bits independently of the
absolute voltage range between the VHCH and VHCL values.
The highcut function can be switched off by I2C bus (bit D7, Fieldstrength byte set to "0").
6.5.5 PLL and Pilot Tone Detector
The PLL has the task to lock on the 19kHz pilotone during a stereo transmission to allow a correct demodulation. The included detector enables the demodulation if the pilot tone reaches the selected pilot tone
threshold VPTHST. Two different thresholds are available. The detector output (signal STEREO, see block
diagram) can be checked by reading the status byte of the TDA7407D via I2C bus.
O
Fieldstrength Control
The fieldstrength input is used to control the high cut and the stereoblend function. In addition the signal
can be also used to control the noiseblanker thresholds and as input for the multipath detector.
18/34
TDA7407D
Figure 22. Relation Between Internal and External LEVEL Voltage and Setup of Stereoblend
INTERNAL
VOLTAGES
INTERNAL
VOLTAGES
SETUP OF VST
SETUP OF VMO
LEVEL INTERN
REF 5V
LEVEL INTERN
REF 5V
LEVEL
VSBL
VSBL
VMO
58%
50%
42%
33%
t
VST
VST
t
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FIELDSTRENGHT VOLTAGE
D97AU639
VMO
FIELDSTRENGHT VOLTAGE
Figure 23. High cut Characteristics
LOWPASS
TIME CONSTANT
3•τDeemp
τDeemp
VHCL
VHCH
FIELDSTRENGHT
D97AU640
6.5.6 LEVEL Input and Gain
To suppress undesired high frequency modulation on the highcut and stereoblend function the LEVEL signal is lowpass filtered firstly.
The filter is a combination of a 1st order RC lowpass at 53kHz (working as anti-aliasing filter) and a 1storder switched capacitor lowpass at 2.2kHz. The second stage is a programmable gain stage to adapt the
LEVEL signal internally to different IF device (see Testmode section 5 LEVELINTERN).
The gain is widely programmable in 16 steps from 0dB to 10dB (step = 0.67dB). These 4 bits are located
together with the Roll-Off bits in the "Stereodecoder Adjustment" byte to simplify a possible adaptation during the production of the carradio.
6.5.7 Stereoblend Control
The stereoblend control block converts the internal LEVEL voltage (LEVEL INTERN) into an demodulator
compatible analog signal which is used to control the channel separation between 0dB and the maximum
separation. Internally this control range has a fixed upper limit which is the internal reference voltage
REF5V. The lower limit can be programmed between 29.2% and 58%, of REF5V in 4.167% steps (see
figs. 22, 23). To adjust the external LEVEL voltage to the internal range two values must be defined: the
LEVEL gain LG and VSBL (see fig. 15). To adjust the voltage where the full channel separation is reached
(VST) the LEVEL gain LG has to be defined. The following equation can be used to estimate the gain:
O
REF5V
L G = --------------------------------------------------------------------------------------Field strenght voltage [STEREO]
19/34
TDA7407D
The gain can be programmed through 4 bits in the "Stereodecoder-Adjustment" byte.
The MONO voltage VMO (0dB channel separation) can be choosen selecting VSBLAll necessary internal
reference voltages like REF5V are derived from a bandgap circuit. Therefore they have a temperature coefficient near zero. This is useful if the fieldstrength signal is also temperature compensated.
But most IF devices apply a LEVEL voltage with a TC of 3300ppm. The TDA7407D offers this TC for the
reference voltages, too. The TC is selectable with bit D7 of the "stereodecoder adjustment" byte.
6.5.8 Highcut Control
The highcut control setup is similar to the stereoblend control setup : the starting point VHCH can be set
with 2 bits to be 42, 50, 58 or 66% of REF5V whereas the range can be set to be 17, 22, 28 or 33% of
VHCH (see fig. 23).
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6.6 FUNCTIONAL DESCRIPTION OF THE NOISEBLANKER
In the automotive environment the MPX signal is disturbed by spikes produced by the ignition and for example the wiper motor. The aim of the noiseblanker part is to cancel the audible influence of the spikes.
Therefore the output of the stereodecoder is held at the actual voltage for a time between 22 and 38µs
(programmable).
The block diagram of the noiseblanker is given in fig. 24.
In a first stage the spikes must be detected but to avoid a wrong triggering on high frequency (white) noise
a complex trigger control is implemented. Behind the triggerstage a pulse former generates the "blanking"
pulse. To avoid any crosstalk to the signalpath the noiseblanker is supplied by his own biasing circuit.
6.6.1 Trigger Path
The incoming MPX signal is highpass filtered, amplified and rectified. This second order highpass-filter
has a corner frequency of 140kHz.
The rectified signal, RECT, is lowpass filtered to generate a signal called PEAK. Also noise with a frequency 140kHz increases the PEAK voltage. The resulting voltage can be adjusted by use of the noise rectifier
discharge current.
The PEAK voltage is fed to a threshold generator, which adds to the PEAK voltage a DC dependent
threshold VTH. Both signals, RECT and PEAK+VTH are fed to a comparator which triggers a re-triggerable monoflop. The monoflop's output activates the sample-and-hold circuits in the signalpath for selected
duration.
Figure 24. Block Diagram of the Noiseblanker
MPX
RECTIFIER
RECT
+
-
+
O
MPX
CONTROL
D98AU856
20/34
VTH
PEAK
LOWPASS
MONOFLOP
THRESHOLD
GENERATOR
+
ADDITIONAL
THRESHOLD
CONTROL
HOLDN
TDA7407D
6.6.2 Automatic Noise Controlled ThresholdAdjustment (ATC)
There are mainly two independent possibilities for programming the trigger threshold:
a
the low threshold in 8 steps (bits D0 to D2 of the noiseblanker byte)
b
the noise adjusted threshold in 4 steps (bits D3 and D4 of the noiseblanker byte).
The low threshold is active in combination with a good MPX signal without any noise; the PEAK voltage
is less than 1V. The sensitivity in this operation is high.
If the MPX signal is noisy the PEAK voltage increases due to the higher noise, which is also rectified. With
increasing of the PEAK voltage the trigger threshold increases, too. This particular gain is programmable
in 4 steps.
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6.7
AUTOMATIC THRESHOLD CONTROL MECHANISM
6.7.1 Automatic Threshold Control by the Stereoblend Voltage
Besides the noise controlled threshold adjustment there is an additional possibility for influencing the trigger threshold. It is depending on the stereoblend control.
The point where the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting
point of the normal noise-controlled trigger adjustment is fixed (fig. ). In some cases the behaviour of the
noiseblanker can be improved by increasing the threshold even in a region of higher fieldstrength. Sometimes a wrong triggering occures for the MPX signal often shows distortion in this range which can be
avoided even if using a low threshold.Because of the overlap of this range and the range of the stereo/
mono transition it can be controlled by stereoblend. This threshold increase is programmable in 3 steps
or switched off with bits D0 and D1 of the fieldstrength control byte.
Figure 25. Block Diagram of the Multipath Detector
6.7.2 Over Deviation Detector
If the system is tuned to stations with a high deviation the noiseblanker can trigger on the higher frequencies of the modulation. To avoid this wrong behaviour, which causes noise in the output signal, the noiseblanker offers a deviation dependent threshold adjustment.
By rectifying the MPX signal a further signal representing the actual deviation is obtained. It is used to increase the PEAK voltage. Offset and gain of this circuit are programmable in 3 steps with the bits D6 and
D7 of the stereodecoder byte (the first step turns off the detector, see fig. 25).
O
6.8 FUNCTIONAL DESCRIPTION OF THE MULTIPATH DETECTOR
Using the internal multipath detector the audible effects of a multipath condition can be minimized. A multipath condition is detected by rectifying the 19kHz spectrum in the fieldstrength signal.An external capacitor is used to define the attack and decay times. the MPOUT pin is used as detector output connected to
a capacitor of about 47nF and additionally the MPIN pin is selected to be the fieldstrength input. Using the
21/34
TDA7407D
configuration an external adaptation to the user's requirement is given in fig.25.
To keep the old value of the Multipath Detector during an AF-jump, the external capacitor can be disconnected by the MP-Hold switch. This switch can be controlled directly by the AFS-Pin.
Selecting the "internal influence" in the configuration byte, the channel separation is automatically reduced
during a multipath condition according to the voltage appearing at the MP_OUT pin. A possible application
is shown in fig. 25.
6.8.1 Programming
To obtain a good multipath performance an adaptation is necessary. Therefore tha gain of the 19kHz
bandpass is programmable in four steps as well as the rectifier gain. The attack and decay times can be
set by the external capacitor value.
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6.9 QUALITY DETECTOR
The TDA7407D offers a quality detector output which gives a voltage representing the FM reception conditions. To calculate this voltage the MPX noise and the multipath detector output are summed according
to the following formula:
Quality = 1.6 (Vnoise -0.8V)+ a (REF5V - VMPOUT)
The noise signal is the PEAK signal without additional influences. The factor "a" can be programmed from
0.7 to 1.15. the output is a low impedance output able to drive external circuitry as well as simply fed to
an A/D converter for RDS applications.
6.9.1 AF Search Control
The TDA7407D is supplied with several functionality to support AF-checks using the stereodecoder. As
mentioned already before the highohmic-mute feature avoids any clicks during the jump condition. It is
possible a the same time to evaluate the noise- and multipath-content of the alternate frequency by using
the Quality detector output. Therefore the multipath-detector is switched automatically to a small time-constant.
One additional pin (AFS) is implemented in order to separate the audioprocessor-mute and stereodecoder
AF-functions. In Figure 24 the block diagram and control-functions of the complete AFS-functionality is
shown (please note that the pins AFS and SM are active low as well as all control-bits indicated by an
overbar).
6.10 TEST MODE
During the test mode, which can be activated by setting bit D0 of the testing byte and bit D5 of the subaddress byte to "1", several internal signals are available at the CASSR pin.
During this mode the input resistor of 100kOhm is disconnected from the pin. The internal signals available
are shown in the software specification.
O
22/34
TDA7407D
Figure 26. Mute Control Logic
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7 I C BUS INTERFACE
DESCRIPTION
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2
7.1 Interface Protocol
The interface protocol comprises:
-a start condition (S)
-a chip address byte (the LSB bit determines read / write transmission)
-a subaddress byte
-a sequence of data (N-bytes + acknowledge)
-a stop condition (P)
Figure 27.
CHIP ADDRESS
MSB
S
1
SUBADDRESS
LSB
0
0
0
1
1
0 R/W ACK
MSB
X AZ T
DATA 1 to DATA n
LSB
I
A3 A2 A1 A0
MSB
ACK
LSB
DATA
ACK
P
D97AU627
23/34
TDA7407D
S = Start
ACK = Acknowledge
AZ = AutoZero-Remain
T = Testing
I = Autoincrement
P = Stop
MAX CLOCK SPEED 500kbits/s
The transmitted data is automatically updated after each ACK. Transmission can be repeated without new
chip address.
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7.2 Auto increment
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled.
Table 11. TRANSMITTED DATA (send mode)
MSB
LSB
X
X
X
X
ST
SM
X
SM = Soft mute activated
ST = Stereo
X = Not Used
Table 12. SUBADDRESS (receive mode)
MSB
I3
LSB
I2
I1
I0
A3
A2
A1
A0
AutoZero Remain
off
on
0
1
Testmode
off
on
0
1
Auto Increment Mode
off
on
0
1
O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
24/34
FUNCTION
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input Multiplexer
Volume
Treble
Bass
Speaker attenuator LF
Speaker attenuator RF
Speaker attenuator LR
Speaker attenuator RR
Soft Mute / Bass Prog.
Stereodecoder
Noiseblanker
High Cut Control
Fieldstrength & Quality
Configuration
EEPROM
Testing
New Quality/Control
Middle Filter
X
TDA7407D
8
DATA BYTE SPECIFICATION
After power on reset all register are set to 11111110
Table 13. Input Selector (subaddress 0H)
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FUNCTION
Source Selector
CD
Cassette
Phone
AM
Stereo Decoder
Not Allowed
Mute
Not Allowed
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0
0
:
1
1
0
0
:
1
1
0
0
:
1
1
In-Gain
15dB
14dB
:
1 dB
0 dB
0
1
:
0
1
1
must be “1”
Table 14. Volume and Speaker Attenuation (subaddress 1H, 4H, 5H, 6H, 7H)
MSB
LSB
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
1
:
1
1
0
:
0
0
0
:
0
0
1
:
1
1
1
:
0
0
1
:
0
0
1
:
0
0
1
:
1
0
not used configurations
1
:
1
0
0
0
:
0
0
:
0
0
0
:
0
0
0
0
:
0
0
:
1
1
0
:
0
0
0
0
:
0
0
:
0
0
0
:
0
0
0
0
:
0
1
:
0
0
1
:
0
0
0
0
:
1
0
:
1
1
1
:
0
0
0
0
:
1
0
:
1
1
1
:
0
0
0
0
:
1
0
:
1
1
1
:
1
0
0
1
:
1
0
:
0
1
+15dB
:
+1dB
0dB
0dB
-1dB
:
-15dB
-16dB
:
-78dB
-79dB
X
1
1
X
X
X
X
X
Mute
O
25/34
TDA7407D
Table 15. Treble Filter (subaddress 2H)
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
0
0
:
0
0
1
1
:
1
1
0
0
:
1
1
1
1
:
0
0
0
0
:
1
1
1
1
:
0
0
0
0
:
1
1
1
1
:
0
0
0
1
:
0
1
1
0
:
1
0
FUNCTION
Treble Steps
-15dB
-14dB
:
-1dB
0dB
0dB
+1dB
:
+14dB
+15dB
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0
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1
1
Treble Center Frequency
10.0KHz
12.5KHz
15.0KHz
17.5KHz
0
1
0
1
1
must be “1”
Table 16. Bass Filter (subaddress 3H)
MSB
D7
LSB
D6
0
0
1
1
0
1
O
26/34
D5
0
1
0
1
D4
D3
D2
D1
D0
0
0
:
0
0
1
1
:
1
1
0
0
:
1
1
1
1
:
0
0
0
0
:
1
1
1
1
:
0
0
0
0
:
1
1
1
1
:
0
0
0
1
:
0
1
1
0
:
1
0
FUNCTION
Bass Steps
-15dB
-14dB
:
-1dB
0dB
0dB
+1dB
:
+14dB
+15dB
Bass Q-Factor
1.0
1.25
1.50
2.0
Bass DC Mode
off
on
TDA7407D
Table 17. Soft Mute and Bass Programming (subaddress 8H)
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
FUNCTION
0
1
0
1
0
1
Mute
Enable Soft Mute
Disable Soft Mute
Mutetime = 0.48ms
Mutetime = 0.96ms
Mutetime = 40.4ms
Mutetime = 324ms
Stereodecoder Soft Mute Influence = on
Stereodecoder Soft Mute Influence = off
)
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0
0
1
1
1
0
0
1
1
Bass Center Frequency
Center Frequency = 60 Hz
Center Frequency = 70 Hz
Center Frequency = 80 Hz
Center Frequency = 100Hz
Center Frequency = 150Hz (1)
0
1
0
1
1
Noise Blanker Time
38µs
25.5µs
32µs
22µs
0
1
0
1
1 Only for Bass Q-Factor = 2.0
Table 18. Stereodecoder (subaddress 9H)
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
1
0
1
0
1
0
1
O
0
1
0
1
0
1
FUNCTION
STD Unmuted
STD Muted
In Gain 11dB
In Gain 8.5dB
In Gain 6dB
In Gain 3.5dB
must be “1”
Forced Mono
Mono/Stereo switch automatically
Noiseblanker PEAK charge current low
Noiseblanker PEAK charge current high
Pilot Threshold HIGH
Pilot Threshold LOW
Deemphasis 50µs
Deemphasis 75µs
27/34
TDA7407D
Table 19. Noiseblanker (subaddress AH)
MSB
D7
LSB
D6
D5
D4
0
0
1
1
D3
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
Low Threshold 65mV
Low Threshold 60mV
Low Threshold 55mV
Low Threshold 50mV
Low Threshold 45mV
Low Threshold 40mV
Low Threshold 35mV
Low Threshold 30mV
Noise Controlled Threshold 320mV
Noise Controlled Threshold 260mV
Noise Controlled Threshold 200mV
Noise Controlled Threshold 140mV
)
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0
1
0
0
1
1
Noise blanker OFF
Noise blanker ON
0
1
0
1
Over deviation Adjust 2.8V
Over deviation Adjust 2.0V
Over deviation Adjust 1.2V
Over deviation Detector OFF
Table 20. High Cut (subaddress BH)
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
O
28/34
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
High Cut OFF
High Cut ON
Max. High Cut 2dB
Max. High Cut 5dB
Max. High Cut 7dB
Max. High Cut 10dB
VHCH at 42% REF 5V
VHCH at 50% REF 5V
VHCH at 58% REF 5V
VHCH at 66% REF 5V
VHCL at 16.7% VHCH
VHCL at 22.2% VHCH
VHCL at 27.8% VHCH
VHCL at 33.3% VHCH
Strong Multipath influence on PEAK 18K
OFF
ON (18K Discharge if VMPOUT <2.5V)
TDA7407D
Table 21. Fieldstrength Control (subaddress CH)
MSB
D7
LSB
D6
D5
D4
0
0
1
1
D3
D2
D1
D0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
VSBL at 29% REF 5V
VSBL at 33% REF 5V
VSBL at 38% REF 5V
VSBL at 42% REF 5V
VSBL at 46% REF 5V
VSBL at 50% REF 5V
VSBL at 54% REF 5V
VSBL at 58% REF 5V
Noiseblanker Field strength Adj 2.3V
Noiseblanker Field strength Adj 1.8V
Noiseblanker Field strength Adj 1.3V
Noiseblanker Field strength Adj OFF
)
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1
1
0
1
0
1
Quality Detector Coefficient a = 0.7
Quality Detector Coefficient a = 0.85
Quality Detector Coefficient a = 1.0
Quality Detector Coefficient a = 1.15
0
1
Multipath off influence on PEAK discharge
-1V/ms (at MPout = 2.5V
Table 22. Configuration (subaddress DH)
MSB
D7
LSB
D6
D5
D4
D3
0
1
0
1
0
1
0
1
O
0
0
1
1
0
1
0
1
D2
0
0
1
1
D1
D0
0
0
1
1
0
1
0
1
FUNCTION
Noise Rectifier Discharge Resistor
R = infinite
R = 56kΩ
R = 33kΩ
R =18kΩ
Multipath Detector Bandpass Gain
6dB
12dB
16dB
18dB
Multipath Detector internal influence
ON
OFF
Multipath Detector Charge Current 0.5µA
Multipath Detector Charge Current 1µA
Multipath Detector Reflection Gain
Gain = 7.6dB
Gain = 4.6dB
Gain = 0dB
disabled
29/34
TDA7407D
Table 23. Stereodecoder Adjustment (subaddress EH)
MSB
D7
D6
D5
D4
D3
0
0
0
:
0
:
0
1
1
1
:
1
:
1
D2
D1
LSB
D0
0
0
0
:
1
:
1
0
0
0
:
1
:
1
0
0
1
:
0
:
1
0
0
1
:
0
:
1
0
1
0
:
0
:
1
0
1
0
:
0
:
1
D2
D1
LSB
D0
FUNCTION
Roll Off Compensation
not allowed
7.2%
9.4%
:
13.7%
:
20.2%
not allowed
19.6%
21.5%
:
25.3%
:
31.0%
Level Gain
0dB
0.66dB
1.33dB
:
10dB
)
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0
0
0
:
1
0
0
0
:
1
0
0
1
:
1
0
1
0
:
1
Table 24. Testing (subaddress FH)
MSB
D7
D6
D5
D4
D3
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
O
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION
Stereodecoder test signals
OFF
Test signals enabled if bit D5 of the
subaddress (test mode bit) is set to "1", too
External Clock
Internal Clock
Testsignals at CASS_R
VHCCH
Level intern
Pilot magnitude
VCOCON; VCO Control Voltage
Pilot threshold
HOLDN
NB threshold
F228
VHCCL
VSBL
not used
not used
PEAK
not used
REF5V
not used
VCO
OFF
ON
Audioprocessor test mode
enabled if bit D5 of the subaddress(test mode
bit) is set to "1"
OFF
Note : This byte is used for testing or evaluation purposes only and must not be set to other values than the default "11111110" in the application!
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TDA7407D
Table 25. New Quality / Control (subaddress 10H)
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
0
1
0
0
1
1
0
1
0
1
0
1
FUNCTION
Reference Generation
Internal Reference-Divider
External Reference Force
Quality Noise-Gain
15dB
12dB
9dB
6dB
SC-Clock-Mode
Fast Mode
Normal Mode
Auto-Zero
Off
On
Smoothing Filter
On
Off
Enable AF-Pin
Enable Pin
Disable Pin
AF-Pin ST-Decoder-Mute-Influence
On
Off
)
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1
Table 26. Mid Filter (subaddress 11H)
MSB
D7
O
LSB
D6
0
0
1
1
01
D5
0
1
0
1
D4
D3
D2
D1
D0
0
0
:
0
0
1
1
:
1
1
0
0
:
1
1
1
1
:
0
0
0
1
:
1
1
1
1
:
0
0
0
1
:
1
1
1
1
:
0
0
0
1
:
0
1
1
0
:
1
0
FUNCTION
Attenuation
-15dB
-14dB
:
-1dB
0dB
0dB
+1dB
:
+14dB
+15dB
Middle Center-frequency
500Hz
1.0kHz
1.5kHz
2.0kHz
Mid Q Factor1.02.0
31/34
TDA7407D
Figure 28. SO28 Mechanical Data & Package Dimensions
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
2.65
MAX.
OUTLINE AND
MECHANICAL DATA
0.104
a1
0.1
0.3
0.004
0.012
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
)
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P
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C
0.5
c1
32/34
45° (typ.)
D
17.7
18.1
0.697
0.713
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
16.51
0.65
F
7.4
7.6
0.291
0.299
L
0.4
1.27
0.016
0.050
S
O
0.020
8 ° (max.)
TDA7407D
9
REVISION HISTORY
Table 27. Revision History
Date
Revision
April 2004
1
Description of Changes
First Issue
)
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33/34
TDA7407D
)
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