FAIRCHILD AN-9735

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AN-9735
Design Guideline for LED Lamp Control Using PrimarySide Regulated Flyback Converter, FAN103 & FSEZ1317
Introduction
Many LED lamp systems use the flyback converter
topology. In applications where precise output current
regulation is required, current sensing in the secondary side
is always necessary, which results in additional sensing loss.
For power supply designers struggling to meet increasing
regulatory pressures, the output current sensing is a daunting
design challenge.
Primary-Side Regulation (PSR) for power supplies can be
an optimal solution for compliance and cost in LED lamp
systems. Primary-side regulation controls the output voltage
and current precisely with information in the primary side of
the LED lamp controller only. This removes the output
current sensing loss and eliminates all secondary-feedback
circuitry. This facilitates a higher efficiency power supply
design without incurring tremendous costs. Fairchild
Semiconductor PWM PSR controller FAN103 and Fairchild
Power Switch (FPS™) (MOSFET + Controller, EZ-PSR)
FSEZ1317 significantly simplify meeting tighter efficiency
requirements with fewer external components.
This application note presents design considerations for
LED lamp systems employing Fairchild Semiconductor
components. It includes designing the transformer and
output filter, selecting the components, and implementing
constant-current control. The step-by-step procedure
completes a power supply design. The design is verified
through an experimental prototype converter using
FSEZ1317. Figure 1 shows the typical application circuit
for an LED lamp using FSEZ1317.
Figure 1. Typical Application Circuit
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
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AN-9735
APPLICATION NOTE
current (IF) decreases linearly from the peak value to zero.
At the end of tDIS, all the energy stored in the inductor has
been delivered to the output.
Operation Principle of Primary-Side
Regulation
Stage III
When the diode current reaches zero, the transformer
auxiliary winding voltage (VA) begins to oscillate by the
resonance between the primary-side inductor (Lm) and the
output capacitor of MOSFET.
Figure 2 shows typical waveforms of a flyback converter.
Generally, Discontinuous Conduction Mode (DCM)
operation is preferred for primary-side regulation since it
allows better output regulation. The key of primary-side
regulation is how to obtain output voltage and current
information without directly sensing them. Once these
values are obtained, the control can be accomplished by the
conventional feedback compensation method.
Stage I
Stage III
Stage II
Design Procedure
In this section, a design procedure is presented using the
schematic in Figure 3 as a reference.
Stage I
IPK
IDS
I
PK

N
N
P
S
IO = IF_AVG
IF
VF 
Figure 3. CV & CC Operation Area
NA
NS
[STEP-1] Estimate the Efficiencies
N
VO  A
NS
Figure 3 shows the CV & CC operation area. To optimize
the power stage design, the efficiencies and input powers
should be specified for operating point A (nominal output
voltage and current), B (70% of nominal output voltage),
and C (minimum output voltage).
VA
tON
1.
Estimated overall efficiency (η) for operating points
A, B, and C: The overall power conversion efficiency
should be estimated to calculate the input power. If
no reference data is available, set η = 0.7 ~ 0.75 for
low-voltage output applications and η = 0.8 ~ 0.85
for high-voltage output applications.
2.
Estimated primary-side efficiency (ηP) and
secondary-side efficiency (ηS) for operating points A,
B, and C. Figure 4 shows the definition of primaryside and secondary-side efficiencies, where the
primary-side efficiency is for the power transfer from
AC line input to the transformer primary side, while
the secondary-side efficiency is for the power transfer
from the transformer primary side to the power
supply output.
tDIS
tS
Figure 2. Key Waveforms of PSR Flyback Converter
The operation principles of DCM flyback converter are:
Stage I
During the MOSFET ON time (tON), input voltage (VDL) is
applied across the primary-side inductor (Lm). Then
MOSFET current (IDS) increases linearly from zero to the
peak value (IPK). During this time, the energy is drawn from
the input and stored in the inductor.
Stage II
When the MOSFET is turned off, the energy stored in the
inductor forces the rectifier diode (DF) to be turned on.
During the diode conduction time (tDIS), the output voltage
(VO), together with diode forward-voltage drop (VF), are
applied across the secondary-side inductor and the diode
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
The typical values for the primary-side and secondary-side
efficiencies are given as:
1
3
2
3
 P   , S   ;VO  10V
(1)
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AN-9735
APPLICATION NOTE
2
3
1
3
The secondary-side efficiency at 70% of nominal output
voltage (operating point B) can be approximated as:
(2)
 P   , S   ;VO  10V
S @ B
0.7  VO
V V
 S 
 O N F
N
0.7  VO  VF
VO
N
N
(6)
Then, the power supply input power and transformer input
power at 70% nominal output voltage (operating point B)
are given as:
0.7  VO  I O
N
PIN @ B 
N
(7)
@ B
0.7  VO  I O
N
PIN _ T @ B 
With the estimated overall efficiency, the input power at
nominal output is given as:
PIN 
VO  I O
@ C   
N
(3)

PIN _ T 
@ C
N
When the output voltage drops below 70% of its nominal
value, the frequency is reduced to 33kHz to prevent CCM
operation. Thus, the transformer should be designed for
DCM both at 70% of nominal output voltage and minimum
output voltage.
0.7  VO
V V
 O N F
N
0.7  VO  VF
VO
(9)
min
V V
  S  min
 O N F
VO  VF
VO
VO
PIN _ T @ B 
N
(10)
min
 IO
N
(11)
@ C
VO
min
 IO
N
(12)
S @C
[STEP-2] Determine the DC Link Capacitor
(CDL) and the DC Link Voltage Range
The overall efficiency at 70% of nominal output voltage
(operating point B) can be approximated as:
@ B   
 VF
VO
PIN @ C 
As output voltage reduces in CC Mode, the efficiency also
drops. To optimize the transformer design, it is necessary to
estimate the efficiencies properly at 70% of nominal output
voltage and minimum output voltage conditions.
N
min
VO  VF
N
VO
N

Then, the power supply input power and transformer input
power at the minimum output voltage (operating point C)
are given as:
(4)
S
VO
min
The secondary-side efficiency at minimum output voltage
(operating point C) can be approximated as:
The input power of transformer at nominal output is given
as:
N
VO
where, Vomin is the minimum output voltage.
where VON and ION are the nominal output voltage and
current, respectively.
VO  I O
(8)
S @ B
The overall efficiency at the minimum output voltage
(operating point C) can be approximated as:
Figure 4. Primary- and Secondary-Side Efficiency
N
N
It is typical to select the DC link capacitor as 2-3µF per watt
of input power for universal input range (90 ~ 265VRMS) and
1µF per watt of input power for European input range (195
~ 265VRMS). With the DC link capacitor chosen, the
minimum DC link voltage is obtained as:
N
(5)
where VF is diode forward-voltage drop.
VDL
min
 2  (VLINE
min 2
) 
PIN (1  Dch )
C DL  f L
(13)
where VLINEmin is the minimum line voltage, CDL is the
DC link capacitor, fL is the line frequency, and Dch is the
DC link capacitor charging duty ratio defined as shown in
Figure 5, which is typically about 0.2.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
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AN-9735
APPLICATION NOTE
voltage should be also considered. The maximum voltage
stress of MOSFET is given as:
VDS
T
 1
T2
D ch
The maximum DC link voltage is given as:
max
 2  VLINE
max
 VDL
(VO  VF ) 
The minimum input DC link voltage at 70% nominal output
voltage are given as:
min
 2  (VLINE
min 2
) 
PIN @ B (1  Dch )
C DL  f L
min
 2  (VLINE
min 2
) 
PIN @ C (1  Dch )
C DL  f L
The transformer turns ratio between the auxiliary winding
and secondary winding (NA/NS) should be determined by
considering the permissible IC supply voltage (VDD) range
and minimum output voltage in constant current. When the
LED operates in constant current, VDD is changed, together
with the output voltage, as seen Figure 7. The overshoot of
auxiliary winding voltage caused by the leakage inductance
also affects the VDD. VDD voltage at light-load condition,
where the overshoot of auxiliary winding voltage is
negligible, is given as:
(16)
Figure 6 shows the MOSFET drain-to-source voltage
waveforms. When the MOSFET is turned off, the sum of
the input voltage (VDL) and the output voltage reflected to
the primary is imposed across the MOSFET as:
nom
 VDL
max
 VRO
VDD min 1 
(17)
NS
 VO  VF 
NP
(18)
where VF is the diode forward voltage drop and NP and NS
are number of turns for the primary side and secondary
side, respectively.
When the MOSFET is turned on, the output voltage,
together with input voltage reflected to the secondary, are
imposed across the diode as:
N
max
VF  VO  S  VDL
NP
(19)
(21)
VDD max 

N
NA 
 VO  VF  S  VOS   VFA
NS 
NP

(22)
VDD min 2 

N
N A  min
 VO  VF  S  VOS   VFA
NS 
NP

(23)
where VFA is the diode forward-voltage drop of auxiliary
winding diode.
As observed in Equations (5) and (6), increasing the
transformer turns ratio (NP/NS) results in increased voltage
of MOSFET, while it leads to reduced voltage stress of
rectifier diode. Therefore, the transformer turns ratio
(NP/NS) should be determined by the compromise between
MOSFET and diode voltage stresses. When determining the
transformer turns ratio, the voltage overshoot (VOS) on drain
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
NA
 VO  VF   VFA
NS
The actual VDD voltage at heavy load is higher than
Equation (21) due to the overshoot by the leakage
inductance, which is proportional to the voltage overshoot
of MOSFET drain-to-source voltage shown in Figure 7.
Considering the effect of voltage overshoot, the VDD
voltages for nominal output voltage and minimum output
voltage are given as:
where VRO is reflected output voltage defined as:
VRO 
NP
NS
Figure 6. Voltage Stress of MOSFET
[STEP-3] Determine the Transformer Turns
Ratio
VDS
(20)
(15)
The minimum input DC link voltage at minimum output
voltage are given as:
VDL @ C
 VRO  VOS
(14)
where VLINEmax is the maximum line voltage.
VDL @ B
max
For reasonable snubber design, voltage overshoot (VOS) is
typically 1~1.5 times the reflected output voltage. It is also
typical to have a margin of 15~20% of breakdown voltage
for maximum MOSFET voltage stress.
Figure 5. DC Link Voltage Waveforms
VDL
max
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AN-9735
APPLICATION NOTE
Transformer primary-side inductance can be calculated as:
Lm 
(VDL @ B
min
 tON @ B ) 2  f S
2  PIN _ T @ B
(26)
The maximum peak-drain current can be obtained at the
nominal output condition as:
I DS
PK

2  PIN _ T
Lm  f S
(27)
The MOSFET conduction time at the nominal output
condition is obtained as:
tON  I DS
[STEP-4] Design the Transformer
NP
Figure 8 shows the definition of MOSFET conduction time
(tON), diode conduction time (tDIS), and non-conduction time
(tOFF). The sum of MOSFET conduction time and diode
conduction time at 70% of nominal output voltage is
obtained as:
t ON @ B  t DIS @ B
Lm
VDL
min
(28)




L I
 m DS
Bsat  Ae
PK
(29)
Figure 9 shows the typical characteristics of ferrite core
from TDK (PC40). Since the saturation flux density (Bsat)
decreases as the temperature rises, the high-temperature
characteristics should be considered when it comes to
charger in enclosed case. If there is no reference data, use
Bsat =0.25~0.3T.
(24)
Once the turns ratio is obtained, determine the proper
integer for NS so that the resulting NP is larger than NPmin
obtained from Equation (29).
Once the tOFF is determined, by considering the frequency
variation caused by frequency hopping and its own
tolerance, the MOSFET conduction time is obtained as:
1
 t OFF @ B
fS

min
VDL @ B
N
1 S 
N P 0.7  VO  VF
min
where Ae is the cross-sectional area of the core in m2 and
Bsat is the saturation flux density in Tesla.
The first step in transformer design is to determine how
much non-conduction time (tOFF) is allowed in DCM
operation.
t ON @ B

The minimum number of turns for the transformer primary
side to avoid the core saturation is given by:
Figure 7. VDD and Winding Voltage
min
 N
VDL @ B
S

 t ON @ B 1 

 N P 0.7  VO  VF

PK
(25)
Figure 8. Definition of tON, tDIS, and tOFF
Figure 9. Typical B-H Curves of Ferrite Core (TDK/PC40)
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
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AN-9735
APPLICATION NOTE
DCM operation at minimum output voltage should be also
checked. The MOSFET conduction time at minimum output
voltage is given as:
tON @ C 
1
VDL @ C
min

N
R1 VO
N

 A 1
R2 Vref N S
Select 1% tolerance resistor for better output regulation.
2  PIN _ T @ C  Lm
(30)
f SR
It is recommended to place a bypass capacitor of 22~68pF
closely between the VS pin and the GND pin to bypass the
switching noise and keep the accuracy of the sampled
voltage for CV regulation. The value of the capacitor affects
the load regulation and constant-current regulation. Figure
10 illustrates the measured waveform on the VS pin with a
different VS capacitor. If a higher value VS capacitor is
used, the charging time becomes longer and the sampled
voltage is higher than the actual value.
where fSR is the reduced switching frequency to prevent
CCM operation.
Then, the non-conduction time at minimum output voltage
is given as:
min
VDL @ C
N
1
)

 t ON @ C (1  P  min
f SR
N S VO  VF
t OFF @ C
(38)
(31)
The non-conduction time should be larger than 3µs (10% of
the switching period), considering the tolerance of the
switching frequency.
[STEP-5] Calculate the Voltage and Current of
the Switching Devices
Primary-Side MOSFET
The voltage stress of the MOSFET was discussed when
determining the turns ratio in STEP-3. Assuming that drainvoltage overshoot is the same as the reflected output
voltage, maximum drain voltage is given as:
VDS
max
 VDL
max
 VRO  VOS
(32)
The RMS current though the MOSFET is given as:
I DS
rms
 I DS
PK

tON  f S
3
(33)
Figure 10. Effect on Sampling Voltage with
Different VS Capacitor
Secondary-Side diode
[STEP-7] Determine the Output Filter Stage
The maximum reverse voltage and the RMS current of the
rectifier diode are obtained, respectively, as:
VF  VO 
N
NS
max
 VDL
NP
The peak to peak ripple of capacitor current is given as:
I CO 
(34)
IF
 I DS
rms
V
N
 DL  P
VRO
NS
(35)
N
I CO  t DIS  I CO  I O


VO 
2  CO
 I CO
[STEP-6] Output Voltage and Current Setting
NP
N
N S  I O  8.5
(37)
The voltage divider R1 and R2 should be determined such
that VS is 2.5V at the end of diode current conduction time,
as shown in Figure 8.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
2

  I CO  RC


(40)
Sometimes it is impossible to meet the ripple specification
with a single output capacitor (CO) due to the high ESR (RC)
of the electrolytic capacitor. Additional LC filter stages
(post filter) can be used. When using the post filters, do not
to place the corner frequency too low. Too low a corner
frequency may make the system unstable or limit the control
bandwidth. It is typical to set the corner frequency of the
post filter at around 1/10 ~ 1/5 of the switching frequency.
The nominal output current is determined by the sensing
resistor value and transformer turns ratio as:
RSense 
(39)
The voltage ripple on the output is given by:
min
rms
NP
PK
 I DS
NS
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AN-9735
APPLICATION NOTE
once the MOSFET drain voltage exceeds the voltage of
cathode of DSN. In the analysis of snubber network, it is
assumed that the snubber capacitor is large enough that its
voltage does not change significantly during one switching
cycle. The snubber capacitor should be ceramic or a
material that offers low ESR. Electrolytic or tantalum
capacitors are unacceptable for these reasons.
[STEP-8] Cable Voltage-Drop Compensation
When the load is far away from output, the output voltage
needs to compensate for voltage drop. FAN103 and
FSEZ1317 have cable voltage-drop compensation that can
be programmed by a resistor on the COMR pin, as shown in
Table 1. If the COMR is not used, such as for LED bulb, it
needs be to connected to GND.
Table 1.
The snubber capacitor voltage at full-load condition (VSN) is
given as:
Cable Compensation
% of Voltage Drop Compensation COMR Resistor
7%
Open
6%
900㏀
5%
380㏀
4%
230㏀
3%
180㏀
2%
145㏀
1%
100㏀
0%
45㏀
VSN  VRO  VOS
The power dissipated in the snubber network is obtained as:
2
PSN 
VSN
VSN
1
PK
  Llk  ( I DS ) 2 
 fS
RSN
2
VSN  VOS
(42)
where IDSPK is peak-drain current at full load, Llk is the
leakage inductance, VSN is the snubber capacitor voltage
at full load, and RSN is the snubber resistor.
The leakage inductance is measured at the switching
frequency on the primary winding with all other windings
shorted. Then, the snubber resistor with proper rated
wattage should be chosen based on the power loss. The
maximum ripple of the snubber capacitor voltage is
obtained as:
[STEP-9] Design RCD Snubber in Primary
Side
VSN 
When the power MOSFET is turned off, there is a highvoltage spike on the drain due to the transformer leakage
inductance. This excessive voltage on the MOSFET may
lead to an avalanche breakdown and, eventually, failure of
the device. Therefore, it is necessary to use an additional
network to clamp the voltage. The RCD snubber circuit and
MOSFET drain-voltage waveform are shown in Figure 6.
The RCD snubber network absorbs the current in the
leakage inductance by turning on the snubber diode (DSN)
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
(41)
VSN
C SN  RSN  f S
(43)
In general, 5~20% ripple of the selected capacitor voltage is
reasonable.
In the snubber design in this section, neither the lossy
discharge of the inductor nor stray capacitance is
considered. In the actual converter, the loss in the snubber
network is less than the designed value due to this effect.
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AN-9735
APPLICATION NOTE
Design Example Using FSFR1317
Table 2. Cable Compensation
Application
LED Bulb
Device
Input
Output
FSEZ1317MY
90VAC ~ 265VAC (50 ~ 60Hz)
4.2W (12V/0.35A)
Description
Symbol
Value
Unit
System Specifications
Minimum Line Input Voltage
VLINEmin
90
VAC
Maximum Line Input Voltage
VLINEmax
265
VAC
fL
60
Hz
V
Line Frequency
Setting Output Voltage
Input
VO
12
Output Voltage at Point B
VO@B
8.40
V
Minimum Output Voltage
VOmin
3
V
Normal Output Current
ION
0.35
A
Output Diode Voltage Drop
VF
0.55
V
Normal Switching Frequency
fS
50
kHz
Switching Frequency between Point B and Point C
fSR
33
kHz
Efficiency
η
0.75
Secondary-Side Efficiency
ηS
0.91
Estimated Efficiency
Input
Input Power
Output
PIN
5.60
Input Power of Transformer
PIN_T
4.62
Efficiency at Point B
η@B
0.74
Secondary-Side Efficiency at Point B
ηS@B
0.89
Input Power at Point B
PIN@B
3.99
PIN_T@B
3.30
Efficiency at Point C
η@C
0.66
Secondary-Side Efficiency at Point C
ηS@C
0.80
Input Power at Point C
PIN@C
1.58
PIN_T@C
1.31
Input Power of Transformer at Point B
Input Power of Transformer at Point C
W
Determine DC Link Capacitor & DC Link Voltage Range
Input
Output
DC Link Capacitor
CDL
9.40
Minimum DC Link Voltage
VDLmin
90.87
Maximum DC Link Voltage
VDLmax
374.77
Minimum DC Link Voltage at Point B
VDL@Bmin
102.64
Minimum DC Link Voltage at Point C
VDL@Cmin
118.12
µF
V
Determine the Transformer Turn Ratio
VRO
70.0
Maximum VDD
VDDmax
24.0
Minimum VDD
VDDmin
5.5
VDD Ripple in Burst Mode
VDDripple
2.5
VDD Diode Drop Voltage
VFA
0.70
Rectifier Output Voltage
Input
NA/NS Ratio
NA/Ns
0.80
VOS
70.00
NP/NS
5.58
0.69
Determine Minimum NA/NS Ratio
NA/NSmin1
NA/NSmin2
NA/Nsmin
Determine Maximum NA/NS Ratio
NA/Nsmax
0.98
MOSFET Overshoot Voltage
NP/NS Ratio
Output
Minimum NA/NS Ratio 1
Minimum NA/NS Ratio 2
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
V
0.39
0.69
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8
AN-9735
APPLICATION NOTE
Description
Symbol
Value
Unit
tOFF@B
5.00
µs
Transformer Core Cross-Sectional Area
Ae
20.10
mm2
Maximum Flux Density
Bsat
0.30
T
Determine Secondary-Side Turns
NS
20
Turns
tON@B
4.91
µs
mH
Transformer Design
Non Conduction Time at Point B
Input
MOSFET Conduction Time at Point B
Transformer Primary-Side Inductance
Output
Lm
1.92
Peak Drain Current
IDSPK
0.31
A
Minimum Primary-Side Turns
Npmin
98.93
Turns
Determine Primary-Side Turns
Np
112
Turns
Determine Auxillary Winding Turns
NA
16
Turns
Final NP/NS Ratio
NP/NS
5.60
Final NA/NS Ratio
NA/Ns
0.80
MOSFET Conduction Time
tON
6.57
µs
Inductor Discharge Time
tDIS
8.49
µs
µs
Non-Conduction Time
tOFF
4.95
MOSFET Conduction Time at Point C
tON@C
3.31
µs
Inductor Discharge Time at Point C
tDIS@C
19.65
µs
Non Conduction Time at Point C
tOFF@C
7.35
µs
MOSFET Maximum Drain-Source Voltage
VDSmax
514.77
V
MOSFET RMS Current
IDSrms
0.10
A
Maximum Diode Voltage
VF
78.92
V
Maximum Diode RMS Current
IF
0.65
A
Selection Switching Device
Output
Setting Output Voltage & Current
VS Low-Side Resistor
Input
R2
33.00
KΩ
Current-Sensing Resistor 1
Rsense1
3.9
Ω
Current-Sensing Resistor 2
Rsense2
3.6
Ω
Real VS High-Side Resistor
R1_real
100
KΩ
R1
93.72
KΩ
Rsense
1.92
Ω
VS High-Side Resistor
Current-Sensing Resistor
Output
Real Output Voltage Setting
VO
11.34
V
Real Current-Sensing Resistor
RS
1.872
Ω
Real Output Current Setting
IO
0.36
A
Design RCD Snubber Stage
Input
Leakage Inductance of Primary Side
Llk
50
µH
Rectifier Output Voltage
VRO
70
V
MOSFET Overshoot Voltage
VOS
70
V
Snubber Voltage
VSN
141
V
ΔVSN
28.11
V
µs
Snubber Capacitor Ripple Voltage
Output
Resonance Time
tS
0.22
Power Dissipation in Snubber Resistor
PSN
0.24
W
Snubber Resistor
RSN
82.26
KΩ
Snubber Capacitor
CSN
1.22
nF
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
www.fairchildsemi.com
9
F1
250V/1A
+
3
-
2
L
4
N
1
L
N
MB6S
U2
+
L1
1mH
C4
C5
4.7uF/400V 4.7uF/400V
L4
0
+
4
1
8
5
D7
1N4007
C1
4.7n/1kV
C6
10uF/50V
DRAIN
VS
HV
COMR
CS
GND
VDD
U1
+
R3
100K3216
2
7
3
FSEZ1317
D5
1N4007
C7
47pF/2012
R14
3R9/3216
1
2
3
4
T1
R9
100K/2012
R13
3R6/3216
8
5
C14
C2
Open
2.2n/1K
R15
33K/2012
D6
R4
Open
EGP20D
+
OUTPUT
C8
220uF/16V
GND
10
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© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
APPLICATION NOTE
AN-9735
Design Summary using FSFR1317
Figure 11. Schematic for LED Bulb
AN-9735
APPLICATION NOTE
Transformer for LED Bulb
Core : EE-16 (Material: PC-40)
Bobbin : 8-Pin
Figure 12. Transformer Specifications and Construction
Table 3. Winding Specifications
No.
Winding
Pin (S → F)
Wire
Turns
Winding Method
1
Np
21
0.12φ×1
112 Ts
Solenoid winding
Ns
85
2
3
Insulation: Polyester Tape t = 0.025mm, 3 Layer
4
5
0.32φ(TEX)×1
20 Ts
Solenoid winding
Insulation: Polyester Tape t = 0.025mm, 3 Layer
Naux
34
6
0.15φ×1
16 Ts
Solenoid winding
Insulation: Polyester Tape t = 0.025mm, 3 Layer
Table 4. Electrical Characteristics
Inductance
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
Pin
Specification
Remark
1–2
1.90mH ±10%
1kHz, 1V
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11
AN-9735
APPLICATION NOTE
Related Datasheets
FSEZ1317 — Primary- Side Regulation PWM with Power MOSFET Integrated Datasheet
FAN103 — Primary-Side Regulation PWM Controller Datasheet
AN-8033 — Design and Application of Primary-Side Regulation (PSR) PWM Controller
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HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
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WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1.
Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
2.
A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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