AN043 Flyback Converter Using Variable Off-time Controller---HFC0300 The Future of Analog IC Technology Application Note for Flyback Converter Using Variable Off-time Controller---HFC0300 Prepared by Henry Xu March, 01, 2011 AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 1 AN043 Flyback Converter Using Variable Off-time Controller---HFC0300 The Future of Analog IC Technology ABSTRACT This paper presents design guidelines for flyback converter using variable off-time controller-HFC0300 from MPS as shown in Figure 1. Design of a flyback converter with variable off time (or quasi fixed on time) control is quite simple and straightforward through the step-by-step design procedure described in this application note. Experimental results based on the design example are presented in the last part. T1 Output * Input 85Vac to 265Vac * * HV 1 8 2 VCC FSET 6 3 5 4 DRV CS GND COMP HFC0300 Figure 1― Flyback Converter Using Variable Off-time Controller--HFC0300 AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 2 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL INDEX 1. 2. 3. 4. 5. 6. HFC0300 INTRODUCTION ............................................................................................................ 4 VARIABLE OFF-TIME CONTROL INTRODUCTION ..................................................................... 4 DESIGN PROCEDURE .................................................................................................................. 5 A. Predetermined Input and Output Specifications .................................................................. 5 B. Determine the Startup Circuitry ............................................................................................ 6 C. Turns Ratio-N, Primary MOSFET and Secondary Rectifier Diode Selection ...................... 7 D. Current Sense Resistor.......................................................................................................... 9 E. Primary side Inductance Lm ................................................................................................. 11 F. Design of CFSET and OLP function ....................................................................................... 12 G. Transformer Design ............................................................................................................. 14 G-1. Transformer Core Selection ............................................................................................ 14 G-2. Primary and Secondary Winding Turns........................................................................... 14 G-3. Wire Size ........................................................................................................................ 14 G-4. Air Gap ........................................................................................................................... 15 H. Ramp Compensation Circuit ............................................................................................... 16 I. Design the RCD Snubber ..................................................................................................... 16 J. Design the Output Filters ..................................................................................................... 18 DESIGN SUMMARY ..................................................................................................................... 18 EXPERIMENTAL VERIFICATION ................................................................................................ 20 REFERENCE ................................................................................................................................ 24 AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 3 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL 1. HFC0300 INTRODUCTION HFC0300 is a variable off-time controller which is integrated with a high voltage current source. Based on a fixed peak current technique, the controller decreases its frequency as the load becomes lighter. As a result, it offers excellent light load efficiency while optimizing the efficiency in other load conditions. When the output power falls below a given level, the controller enters the burst mode to further reduce the power loss at no load or light load condition. Internal Vcc Under Voltage Lockout (UVLO), Over Load Protection (OLP), Over Voltage Protection (OVP), Short Circuit Protection (SCP) and Thermal Shutdown (TSD) are all integrated in the IC to minimize the external component count. This paper presents practical design guidelines for an off-line flyback converter employing HFC0300. Step-by-step design procedure for off-time controlled flyback converter using HFC0300 is introduced in this application note, mainly including transformer design, output filter design and component selection. 2. VARIABLE OFF-TIME CONTROL INTRODUCTION Variable Off-Time control is one of the variable frequency control scheme for flyback converter. By implementing a fixed peak current mode control, the peak current of the switch is fixed (quasi-fixed switch on time) and the off-time duration is regulated according to the required output power. During the on time of the MOSFET, the Drain current increases. Once the Drain current reaches the internal fixed peak current level, the MOSFET turns off. The feedback loop controls the frequency or the off time based on the output condition. So as the load decreases, the off time expands and the switching frequency also decreases. As the frequency decreases at the light load, the contribution of all the frequency-dependent losses accordingly goes down (gate drive loss, switching losses, core loss), naturally improving the efficiency. Reducing the switching frequency will certainly force the converter to operate into the audible region. To prevent the transformer mechanical resonance, HFC0300 gradually reduces the peak current as the load becomes lighter. Figure 2 shows the Drain-Source voltage waveform of primary switch in an off-time control flyback converter. During the on time of MOSFET, the Drain current increases linearly until the peak current level is reached. The MOSFET then turns off. The leakage inductance in the flyback transformer rings with the parasitic capacitance and causes a high voltage spike, which should be limited by a clamp circuit. When FSET Pin voltage reaches the level of COMP (feedback PIN), the switch turns on again and starts a new switching cycle. AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 4 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL n:1 + VOUT - + Csn VBUS Rsn Dsn ID + Vds - - vds ID FSET COMP 0.6uS Figure 2― Key Waveforms of Off-Time Flyback Converter 3. DESIGN PROCEDURE A. Predetermined Input and Output Specifications - Input AC voltage range: Vac(min), Vac(max), for example 90Vac~265Vac RMS - DC bus voltage range: Vin(max), Vin(min). - Output: Vo , Io(min), Io(max), Pout - Estimated efficiency: η, It is used to estimate the power conversion efficiency to calculate the maximum input power. Generally, η is set to be 0.8~0.9 according to different output applications. Then the maximum input power can be given as: Pin = AN043 Rev. 1.1 12/29/2014 Pout η www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (1) 5 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL Figure 3 shows the typical DC bus voltage waveform. The DC input capacitor Cin is usually set as 2μF/W for the universal input condition. For 230V single range application, the capacitance can be half the value. Vin VDC(max) DC input Voltage VDC(min) AC input Voltage T1 t Figure 3― Input Voltage Waveform From the waveform above, the AC input Voltage VAC and DC input Voltage VDC can be got as: VDC ( Vac ,t ) = 2 × Vac 2 − 2 × Pin ×t Cin (2) By setting VAC=VDC, T1 where DC bus voltage reaches to its minimum value VDC(min) can be calculated as VDC(min) = VDC ( Vac(min) ,T1) (3) Then, the minimum average DC input voltage Vin(min) can be got as: Vin(min) = 2 ⋅ Vac (min) + VDC(min) 2 (4) The maximum average DC input voltage Vin(max) can be got as: Vin(max) = 2 ⋅ Vac(max) (5) B. Determine the Startup Circuitry Figure 3 shows the startup circuit. When power is on, the internal 2mA current source charges C1 through R1 connected to HV pin of HFC0300. Once VCC voltage reaches 11.7V, the internal high voltage current source (2mA) turns off and IC starts switching, then the auxiliary winding takes over the power supply. If VCC drops below 8.2V before the auxiliary winding takes over the power supply, the switching stops and the internal high voltage current source turns on again, which re-charges the VCC external capacitor C1, starting another start-up procedure(see Figure 4). AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 6 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL 90 ~265Vac input R1 HV 1 8 2 VCC C1 6 3 5 4 HFC0300 * Figure 3― The Startup Circuit with HFC0300 The auxiliary winding takes over VCCH=11.7V VCC VCCL=8.2V ON Internal Current Source OFF Driving Signal Figure 4― The Startup Waveform and VCC UVLO of HFC0300 C. Turns Ratio-N, Primary MOSFET and Secondary Rectifier Diode Selection Figure 5 shows the typical voltage waveform of the primary MOSFET and secondary rectifier diode in a flyback converter. From the waveform, the primary MOSFET Drain-Source voltage rating Vds can be got as equation (6): Vds = Vin(max) + N ⋅ (Vout + VF ) + 60V k (6) Where k is the derating factor which is typically selected as 0.9. VF is the forward voltage of the rectifier diode, 60V spike voltage is assumed here. The secondary rectifier diode voltage rating Vka can be estimated as equation (7): Vin(max) + Vout N Vka = k (7) Where k is the derating factor which is typically selected as 0.9. AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 7 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL n:1 - Vka + + VOUT - + Csn VBUS Rsn Dsn ID + Vds - - vds Spike vka Figure 5― Voltage Stress of Primary MOSFET and Secondary Rectifier Diode From equation (6) and (7), the voltage rating for primary MOSFET and secondary rectifier diode versus turns-ratio N can be calculated and shown in Figure 6. 800 140 750 130 700 120 VKA (N) VDS (N) For example, in 90Vac~265Vac input, 19V output adapter application, 650V MOSFET and 100V rectifier diode is preferred for better performance. From figure 7, N=6 is selected for the required voltage rating. 650 600 110 100 550 90 500 80 450 70 400 4 5 6 7 N 8 9 10 60 4 5 6 7 8 9 10 N Figure 6― Voltage Stress Rating of Primary MOSFET and Secondary Rectifier Diode AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 8 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL D. Current Sense Resistor The peak current level is internally set to be 0.5V, so current sense resistor sets the primary side peak current, which also determines the operation mode of the converter, such as CCM, BCM or DCM. If power supply is designed to operate at BCM at low line input, it will operate at DCM at high line and the same load condition. The magnetizing inductor current (reflected to the primary side) and the Drain-Source voltage of the primary MOSFET is shown as Figure 8. Inductor Current (A) Iprimary Isecondary/N 0.5V/Rsense VDS Tsecond Low line Inductor Current (A) Iprimary Isecondary/N 0.5V/Rsense VDS Tsecond High line T Figure 8― Inductor Current and Voltage of Primary MOSFET at Different Line AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 9 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL The time duration of secondary current can be got as equation (8). Tsec ond = Lm ∗ Ipeak N ∗ VO (8) Where Lm is primary magnetizing inductance, Ipeak is primary peak current. Since Ipeak is always the same at different input and same output conditions, so the time duration of secondary current is the same. The switching period can be calculated by equation (9). T= N ∗ Ipeak ∗ Tsec ond 2 ∗ Io (9) From (9), the switching period also keeps the same at different input and same output conditions. Since the primary side switch on time decreases with the input voltage increasing, therefore, the higher the input line voltage, the deeper DCM mode it will enter. Usually, the parameters should be designed at the minimum input condition to guarantee the converter can deliver the required output power at minimum input condition. Since N has been selected, so if the power supply is designed to operate at boundary current mode (BCM) at low line, the peak current can be calculated easily as equation (10). Ipeak _ BCM = 2Io 1− D (10) Where D is the duty ratio of the switching, it can be got as equation (11). D= (Vo + VF ) * N Vin + (Vo + VF ) * N (11) If the peak current set by current sense resistor is larger than Ipeak_BCM, the power supply will enter DCM. On the contrary, if the peak current set by current sense resistor is less than Ipeak_BCM, the power supply will enter CCM as Figure 9. Here, we define Kdepth as the depth of CCM. K depth = Ivalley Ipeak (12) IMOSFET Ipeak Ivalley Figure 9― Primary Current at CCM AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 10 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL So peak current can be got as equation (13). Ipeak = 2Io (1 − D) * (1 + K depth ) * N (13) Usually, BCM (boundary current mode) is preferred for the power level below 40W. CCM (continuous current mode) is selected when the power level is higher than 40W. The higher the power delivers, the deeper CCM should be adopted for higher efficiency and better thermal performance at full load. For example, for a 90W power supply, 0.5 could be chosen for Kdepth. So when a power supply SPEC is given, we need to determine the converter operation mode firstly, i.e. determine the Kdepth. Ipeak and Ivalley can be calculated by equation (10) to (13). And the current sense resistor could be selected by equation (14). R sense = Vpeak Ipeak (14) Where Vpeak is the peak voltage threshold of the current resistor, it is a constant 0.5V for HFC0300. The current resistor with the proper power rating should be chosen based on the power loss given in equation (15) ⎡⎛ I peak +Ivalley ⎞2 1 ⎤ 2 Psense = ⎢⎜ ⎟ + (I peak −Ivalley ) ⎥ * D * Rsense 2 ⎢⎣⎝ ⎥⎦ ⎠ 12 (15) E. Primary side Inductance Lm The power that a flyback converter can deliver is related to the energy stored in the primary side inductance Lm as given in equation (16) and (17) for CCM and DCM respectively. po _ CCM 1 * Lm * (Ipeak 2 − Ivalley 2 ) * fs = 2 η (16) po _ DCM 1 * Lm * Ipeak 2 * fs = η 2 (17) In order to regulate the delivered power to the output, we can either adjust the peak current value (conventional peak current mode control) and/or adjust the switching frequency. HFC0300 regulates the output power by adjusting the switching frequency while keeping the peak current value constant. Thus, once the peak current is selected, the feedback loop automatically sets the switching frequency to get the desired output power. Since Ipeak and Ivalley have been determined at the beginning of the design procedure, Lm can be calculated if fs is chosen. Offering a good EMI performance, a maximum frequency of 65kHz is usually a good choice because the conducted EMI noise at second harmonics (2*65kHz) is still not tested (conducted EMI frequency range:150kHz~30MHz) As mentioned in section D, the switching frequency keeps the same ideally at different input line voltage and the same output power. Actually, there is slightly difference in the practical circuit. Since the peak current will be a little bit higher at high input than that at low input due to the inevitable propagation delay though the threshold is constant, the switching frequency will reaches its maximum at low line and full load condition. So we usually choose 65kHz as the frequency at low line and full load. As a result, all the calculation is carried at lowest line. AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 11 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL F. Design of CFSET and OLP function The maximum frequency is set by the end of charge of the capacitor CFSET connected to the FSET pin as shown in Fig 10. This capacitor is charged by a constant current source shortly after the primary side switch turns on (about 0.6us), and its voltage is compared with COMP voltage from feedback loop (see Figure 10). When this capacitor voltage reaches the threshold, the capacitor is rapidly discharged down to 0V, and a new period starts. To make the voltage at FSET pin fully discharged, it is internally about 0.6μs delay before the CFSET is charged again (see Figure 11). Thus the switching frequency is regulated by the feedback loop like a VCO (voltage controlled oscillation). The capacitance connected to FSET pin is got as equation (18). 1 + 0.6us) fmax 0.88V 28uA * ( CFSET = (18) Where fmax is the maximum frequency set by the capacitor connected to FSET pin. FSET 0.6µs pulse 28µA VCC S VOFFSET 0.88V R Q _ Q Drive COMP 3.3V Figure 10― VCO (Voltage Controlled Oscillation) Operation Vfset Controlled by the COMP Voltage Minimum Frequency Pout Decrease IFSET=28µA Pout Increase Maximum Frequency Figure 11― COMP Voltage adjusts the Switching Frequency AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 12 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL As described as above section, the switching frequency reaches its maximum at low line and full load. We define this frequency as fs( 65kHz selected here). We set maximum frequency (fmax) as about 110% fs. Frequency increases with the increasing of the output power. When the frequency reaches maximum frequency which is set by CFSET, over power limitation takes place which makes output voltage can’t be maintained, thus COMP is saturated and below OLP (over load protection) threshold (0.85V). A unique digital timer method is employed in HFC0300 for over load protection (OLP). When COMP is lower than 0.85V which is considered as an error flag, the timer starts counting. If the error flag removes, the timer resets. If the timer overflows when the counting number reaches 6000, OLP will be triggered. This timer duration avoids triggering OLP function when the power supply is at start up or load transition phase. So output voltage should be established in less than 6000 switching cycles during startup. AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 13 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL G. Transformer Design G-1. Transformer Core Selection An appropriate core for certain output power at the operating frequency needs to be selected. Ferrite is usually preferred for flyback transformer. The core area product (AEAW) which is the core magnetic cross-section area multiplied by window area available for winding, is widely used for an initial estimate of core size for a given application. A rough indication of the required AEAW (cm4) is given by following equation [1]: AE ⋅ A W ⎛ Lm ⋅ Ip ⋅ Irms × 10 4 =⎜ ⎜ B ⋅K ⋅K ⋅ f ⎝ max u j s 4 ⎞ 3 4 ⎟⎟ cm ⎠ (19) Where Ku is winding factor which is usually 0.25~0.3 for an off-line transformer. Kj is the current-density coefficient (typically 400~450 for ferrite core). Ipeak and Irms is the maximum peak current and RMS current of the primary inductance, Bmax is the allowed maximum flux density in normal operation which is usually preset to be the saturation flux density of the core material (0.3T~0.4T). fs is the switching frequency at low line and full load condition. RMS current is given by following equation. Irms ⎡⎛ I peak +Ivalley ⎞2 1 2⎤ = ⎢⎜ ⎟ + (I peak −Ivalley ) ⎥ ⋅ D 2 ⎢⎣⎝ ⎥⎦ ⎠ 12 (20) For power supply at DCM, Ivalley equals to 0. G-2. Primary and Secondary Winding Turns With a given core size, equation (21) defines a minimum value of NP for the transformer primary winding to prevent the core from saturation: Np = Lm ⋅ Ipeak AE ⋅ Bmax (21) Where: Lm is the primary side inductance of the transformer Bmax is the maximum allowable flux density AE is the effective cross sectional core Ipeak is the peak current in the primary side of the transformer The maximum allowable flux density Bmax should be smaller than the saturation flux density Bsat. Since Bsat decreases as the temperature increases, which should be considered in the design. Secondary winding turns Ns is a function of N and NP, which is given by equation (22). Ns = Np N (22) G-3. Wire Size Once all the winding turns are determined, the wire size should be properly chosen to minimize the winding conduction loss and leakage inductance. The winding loss depends on the RMS current value, the length and the cross section of wire, also the transformer structure. The wire size could be determined by the RMS current of the winding. For a flyback converter, the RMS current on primary side is given by equation (23), and the RMS current on secondary side is given by equation (23). AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 14 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL ⎡⎛ I peak +Ivalley ⎞ 2⎤ 1 Isec_ rms = N * ⎢⎜ I peak −Ivalley ) ⎥ ⋅ (1 − D) ( ⎟ + 2 ⎢⎣⎝ ⎥⎦ ⎠ 12 2 (23) For flyback operated at DCM, Ivalley equals to 0. Then, the wire size required on primary and secondary side is got by equation (24) and equation (25) Spri = Ssec = Ipri _ rms (24) J Isec_ rms (25) J Here J is the current density of the wire which is 450A/cm2 typically. Due to the skin effect and proximity effect of the conductor, the diameter of the wire should be less than 2*Δd (Δd: skin effect depth): Δd = 1 * 10 3 (mm) π ⋅ fs ⋅ μ ⋅ σ (26) Where μ is the magnetic permeability of the conductor, which usually equals to the permeability of vacuum for most conductor, i.e. 4 π × 10 −7 H/m, σ is the conductivity of the wire (for copper, σ is typically 6 × 10 7 S/m at 0 deg, σ will increases as temperature increases, which means the Δd will get smaller). If the required size of the winding is larger than Δd , multiple strands of thinner wire or Litz wire is usually adopted to minimize the AC resistance. The effective cross section area of multi-strands wire or Litz wire should be large enough to meet the requirement set by the current density. After the wire sizes have been determined, it is necessary to check whether the window area with selected core can accommodate the windings calculated in the previous steps. The window area required by each winding should be calculated respectively and added together, the area for inter-winding insulation, bobbin and spaces existing between the turns should also be taken into consideration. The fill factor, means the winding area to the whole window area of the core, should be well below 1 due to these inter-winding insulation and spaces between turns. It is recommended that a fill factor no greater than about 30% be used. For transformers with multiple outputs this factor may need to be reduced further. Based on these considerations, the total required window area is then compared to the available window area of a selected core. If the required window area is larger than the selected one, either wire size must be reduced, or a larger core must be chosen. Of course, a reduction in wire size increases the copper loss of the transformer. G-4. Air Gap With the selected core and winding turns, the air gap of the core is given as equation (27): la = AN043 Rev. 1.1 12/29/2014 μ0 * Np 2 * A E Lm − lc μr www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (27) 15 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL Where AE is the cross sectional area of the selected core, μ0 is the permeability of vacuum which equals 4π × 10 −7 H/m. Lm and NP is the primary winding inductance and turns respectively, lc is the core magnetic path length and μr is the relative magnetic permeability of the core material. For Ferrite core, μ r is very large, so l a can be approximately calculated as equation (28). la = μ0 * Np 2 * A e (28) Lm H. Ramp Compensation Circuit If the power supply is designed to operate at CCM and the duty cycle is larger than 0.5, the ramp compensation circuit should be added to avoid sub-oscillation with peak current mode control. Usually, the ramp compensation rate is selected as equation (29) k = α* V0 * N * Rsense Lm (29) Where: α is the coefficient which is usually 0.5~1.0 Rsense is the value of primary sense resistor For HFC0300 application, the external ramp compensation circuit shown in Fig 12 is recommended. HV 8 2 CS VCC FSET VCC 1 DRV 510K 1K R1 HFC0300 6 3 GND 5 4 R3 33pF C1 R2 30K CS COMP Figure 12― Ramp Compensation Circuit The compensation rate added of above circuit could be got approximately as equation (28). k≈ VDRV R1 * τ R2 (30) Where: VDRV is the drive voltage τ = R3 * C1 τ should be selected to be larger than the switching period, so the ramp added is linear approximately. I. Design the RCD Snubber The voltage spikes caused by the leakage inductance Lk during switch turn-off should be suppressed to an acceptable level to protect the switch. The RCD snubber is usually adopted to suppress the spike. The RCD clamp circuit and key waveforms are shown in Figure 13 and Figure 14 respectively. The RCD snubber circuit absorbs the energy in the leakage inductor when Vds exceeds Vin+Vsn. It is assumed that AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 16 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL the snubber capacitance is large enough thus its voltage is constant during one switching period. ISEC N:1 + + - VO Vsn + C sn Rsn VBUS D sn - Lk isn ID + Vds - COSS - Figure 13― Flyback Converter with RCD Snubber ID ipeak ts isn ISEC vds vsn N*Vo vin Figure 14― Key Waveforms When the MOSFET turns off and Vds is charged to Vin+N*Vo, the secondary diode turns on at the same time. The primary current continues to flow through the snubber diode (Dsn) to Csn. The voltage stress of MOSFET is clamped to Vin+Vsn .Therefore, the voltage across Lk is Vsn-N*Vo. The slope of isn is given by equation (31). ⎛ V − N * Vo ⎞ disn = − ⎜ sn ⎟ dt Lk ⎝ ⎠ AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (31) 17 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL Where isn is the current that flows into the snubber circuit, Vsn is the voltage across the snubber capacitor Csn, Lk is the leakage inductance of the main transformer. The time ts is obtained by equation (32). ts = Lk × Ipeak Vsn − N * Vo Once Vsn is determined, the power dissipated in the snubber circuit is obtained by equation Psn = Vsn ipeak ⋅ t s 2 fs = (32) (33). Vsn 1 Lk ipeak 2 fs 2 Vsn − N * Vo (33) Where fs is the switching frequency. Vsn should be 1.5~2 times of N*Vo. Very small Vsn results in a severe loss in the snubber circuit, as indicated in equation (33). On the other hand, since the power consumed in the snubber resistor (Rsn) is Vsn2/Rsn, the resistance is obtained by: R sn = Vsn2 Vsn 1 Lk ipeak 2 fs 2 Vsn − N * Vo (34) The snubber resistor with the proper rated power should be chosen based on the power loss. The maximum ripple of the snubber capacitor voltage is obtained equation (35). ΔVsn = Vsn CsnRsn fs (35) Generally, 5~10% ripple is reasonable. Therefore, the snubber capacitance can be calculated. J. Design the Output Filters The voltage ripple at the output side can be estimated by: ΔVo = Io ⋅ (T − Tsec ond ) Co (36) Where T is switching period, Co is output filter capacitance, and Tsecond is time duration of second current. The output capacitor can be electrolytic capacitor. If the electrolytic capacitor is used, due to its high ESR and ESL, a film capacitor or ceramic capacitor is usually paralleled to the electrolytic capacitor to provide a low impendence current path for high frequency current ripple. To further reduce the output voltage ripple, a small LC filter can be inserted between the output capacitor and output terminal. 4. DESIGN SUMMARY z A detailed reference design of off-time controlled flyback converter with HFC0300 controller is shown in Figure 15. The input voltage is 90Vac to 265Vac and the output is 24V/1.5A. AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 18 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL Figure 15― Schematic of Off-Time Flyback Converter with HFC0300 z The transformer used in this design has a turn ratio of 84:14:8 (Np: Ns:Naux) with 818uH primary inductance. The core selected is EE25. The wire structure is shown as Figure 16, 17 and Table 1. PRI. SEC. 1 2 N4 10 9 N1 3 5 N3 7 6 N2 4 TEFLON TUBE Figure 16― Connection Diagram AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 19 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL Pri. Side Sec. Side 2mm 2mm Tape: 3T N4 3T N3 3T N2 1T N1 1T Figure 17― Winding Diagram Tape(T) Edge Tape Terminal Edge Tape Wire size Turns (Pri.) (start-end) (Sec.) (φ) (T) N1 2mm 3—〉2 2mm 0.3mm*1 42 N2 2mm 5—〉4 2mm 0.2mm*1 8 N3 2mm 9,10—〉6,7 2mm 0.3mm*5 14 N4 2mm 2—〉1 2mm 0.3mm*1 42 Winding 1 1 3 3 3 Table 1― Winding Order 5. EXPERIMENTAL VERIFICATION To verify design procedure presented in this application note and the performance, a prototype based in Fig 15 is built and tested with specified input/output condition(Input: 90VAC~265VAC; Output: 24V/1.5A). The converter is designed to operate at BCM at 90Vac input and full load. Figure 18 and Figure 19 shows the current and Drain voltage waveform of primary MOSFET. Figure 20 shows the Burst Mode function of the controller at light load. To minimize power dissipation at no load or light load, the HFC0300 enters burst-mode operation. As the load decreases, the COMP voltage increases. The HF0300 skips switching cycles when the COMP voltage increases over the threshold VBURH—3.2V. And the output voltage starts to drop which causes the COMP voltage to decrease again. Once the COMP voltage falls below the threshold VBURL—3.1V, the switching resumes. The COMP voltage then falls and rises repeatedly. The burst mode operation alternately enables and disables switching cycles of the MOSFET thereby reducing switching loss in the no load or light load conditions. AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 20 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL Figure 21 shows over load protection function. When COMP is low, the controller stops switching after 6000 switching cycles (about 100ms for this application) Figure 22 shows the measured efficiency. From the efficiency curve, the efficiency is still high at light load condition due to decreased switching frequency. Also the power consumption at no load is given in Table 2. Due to the burst mode operation, the power loss at no load condition is very small, even at high line input. Vds CS Figure 18― Drain Voltage and Current of MOSFET at Low Line Input (90Vac) (CH2: CS; CH3: Vds) AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 21 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL Vds CS Figure 19― Drain Voltage and Current of MOSFET at High Line Input (230Vac) (CH2: CS; CH3: Vds) COMP DRV Figure 20― Burst Mode Function of HFC0300 (CH2: COMP; CH3: DRV) AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 22 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL Vout Iout DRV COMP Figure 21― Over Load Protection of HFC0300 (CH1: Vout; CH2: COMP; CH3: DRV; CH4: Iout) 90.00% 88.00% Efficiency(%) 86.00% 84.00% 82.00% 80.00% 78.00% 76.00% 74.00% 72.00% 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Output Current Io(A) Vin=115VAC Vin=230VAC Figure 22― Measured Efficiency of the Prototype Input voltage (Vac, RMS) Power loss (mW) 90 115 230 265 74.4 77.2 110.1 121.9 Table 2― No Load Loss at Different Line Voltage AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 23 AN043 –FLYBACK CONVERTER USING VARIABLE OFF-TIME CONTROL 6. REFERENCE [1]. Lloyd H. Dixon, “Magnetics Design for Switching Power Supplies,” in Unitrode Magnetics Design Handbook, 1990. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. AN043 Rev. 1.1 12/29/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 24