SCAN18245T Non-Inverting Transceiver with TRI-STATE ® Outputs General Description Features The SCAN18245T is a high speed, low-power bidirectional line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented output enable and direction control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). n n n n n n Connection Diagram n n n n n IEEE 1149.1 (JTAG) Compliant Dual output enable control signals TRI-STATE outputs for bus-oriented applications 9-bit data busses for parity applications Reduced-swing outputs source 24 mA/sink 48 mA Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V TTL compatible inputs 25 mil pitch Cerpack package Includes CLAMP and HIGHZ instructions Available as Known Good Die Standard Microcircuit Drawing (SMD) 5962-9311501 Pin Names Description B1(0–8) Side B1 Inputs or TRI-STATE Outputs A2(0–8) Side A2 Inputs or TRI-STATE Outputs B2(0–8) Side B2 Inputs or TRI-STATE Outputs G1, G2 Output Enable Pins DIR1, DIR2 Direction of Data Flow Pins DS100320-1 Pin Names A1(0–8) Description Side A1 Inputs or TRI-STATE Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100320 www.national.com SCAN18245T Non-Inverting Transceiver with TRI-STATE Outputs September 1998 Truth Tables Inputs A1 (0–8) B1 (0–8) G1 DIR1 L L H ← H L L L ← L L H H → H L H L → H X Z Inputs L Z A2 (0–8) B2 (0–8) G2 DIR2 L L H ← H L L L ← L L H H → H L H L → H X Z L Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Functional Description ables data from A ports to B ports. The Output Enable pins (G1 and G2) when HIGH disables both A and B ports by placing them in a high impedance condition. The SCAN18245 consists of two sets of nine non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus-oriented applications. Direction pins (DIR1 and DIR2) LOW enables data from B ports to A ports, when HIGH en- Block Diagrams A1, B1, G1 and DIR1 DS100320-2 Note: BSR stands for Boundary Scan Register. www.national.com 2 Block Diagrams (Continued) Tap Controller DS100320-3 A2, B2, G2 and DIR2 DS100320-4 Note: BSR stands for Boundary Scan Register. 3 www.national.com Description of Boundary-Scan Circuitry The two least significant bits of this captured value (01) are required by IEEE Std 1149.1. The upper six bits are unique to the SCAN18245T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Figure 10–11 for a further description of scan cell TYPE1 and Figure 10–12 for a further description of scan cell TYPE2.) Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. Instruction Register Scan Chain Definition The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. DS100320-10 MSB → LSB Bypass Register Scan Chain Definition Logic 0 Instruction Code DS100320-9 The INSTRUCTION register is an eight-bit register which captures the value 00111101. www.national.com 4 Instruction 00000000 EXTEST 10000001 SAMPLE/PRELOAD 10000010 CLAMP 00000011 HIGHZ All Others BYPASS Description of Boundary-Scan Circuitry (Continued) Scan Cell TYPE1 DS100320-7 Scan Cell TYPE2 DS100320-8 5 www.national.com Description of Boundary-Scan Circuitry (Continued) Boundary-Scan Register Scan Chain Definition (80 Bits in Length) DS100320-25 www.national.com 6 Description of Boundary-Scan Circuitry (Continued) Boundary-Scan Register Definition Index Bit No. Pin Name Pin No. Pin Type 79 DIR1 3 Input 54 78 G1 77 AOE1 76 BOE1 75 DIR2 26 74 G2 31 73 AOE2 72 BOE2 71 A10 55 70 A11 69 Scan Cell Type TYPE1 Input TYPE1 Internal TYPE2 Internal TYPE2 Input TYPE1 Input TYPE1 Internal TYPE2 Internal TYPE2 Input TYPE1 53 Input TYPE1 A12 52 Input TYPE1 68 A13 50 Input TYPE1 67 A14 49 Input TYPE1 66 A15 47 Input TYPE1 65 A16 46 Input TYPE1 64 A17 44 Input TYPE1 63 A18 43 Input TYPE1 62 A20 42 Input TYPE1 61 A21 41 Input TYPE1 60 A22 39 Input TYPE1 59 A23 38 Input TYPE1 58 A24 36 Input TYPE1 57 A25 35 Input TYPE1 56 A26 33 Input TYPE1 55 A27 32 Input TYPE1 54 A28 30 Input TYPE1 53 B10 2 Output TYPE2 52 B11 4 Output TYPE2 51 B12 5 Output TYPE2 50 B13 7 Output TYPE2 49 B14 8 Output TYPE2 48 B15 10 Output TYPE2 47 B16 11 Output TYPE2 46 B17 13 Output TYPE2 45 B18 14 Output TYPE2 44 B20 15 Output TYPE2 43 B21 16 Output TYPE2 42 B22 18 Output TYPE2 41 B23 19 Output TYPE2 40 B24 21 Output TYPE2 39 B25 22 Output TYPE2 38 B26 24 Output TYPE2 37 B27 25 Output TYPE2 36 B28 27 Output TYPE2 7 Control Signals A1–in A2–in B1–out B2–out www.national.com Description of Boundary-Scan Circuitry (Continued) Boundary-Scan Register Definition Index (Continued) Bit No. Pin Name Pin No. Pin Type 35 B10 2 Input TYPE1 34 B11 4 Input TYPE1 33 B12 5 Input TYPE1 32 B13 7 Input TYPE1 31 B14 8 Input TYPE1 30 B15 10 Input TYPE1 29 B16 11 Input TYPE1 28 B17 13 Input TYPE1 27 B18 14 Input TYPE1 26 B20 15 Input TYPE1 25 B21 16 Input TYPE1 24 B22 18 Input TYPE1 23 B23 19 Input TYPE1 22 B24 21 Input TYPE1 21 B25 22 Input TYPE1 20 B26 24 Input TYPE1 19 B27 25 Input TYPE1 18 B28 27 Input TYPE1 17 A10 55 Output TYPE2 16 A11 53 Output TYPE2 15 A12 52 Output TYPE2 14 A13 50 Output TYPE2 13 A14 49 Output TYPE2 12 A15 47 Output TYPE2 11 A16 46 Output TYPE2 10 A17 44 Output TYPE2 9 A18 43 Output TYPE2 8 A20 42 Output TYPE2 7 A21 41 Output TYPE2 6 A22 39 Output TYPE2 5 A23 38 Output TYPE2 4 A24 36 Output TYPE2 3 A25 35 Output TYPE2 2 A26 33 Output TYPE2 1 A27 32 Output TYPE2 0 A28 30 Output TYPE2 www.national.com 8 Scan Cell Type B1–in B2–in A1–out A2–out Absolute Maximum Ratings (Note 1) ESD (Min) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC +0.5V DC Output Diode Current (IOK) VO = −0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current Per Output Pin Junction Temperature Cerpack Storage Temperature 2000V Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) SCAN Products Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Military Minimum Input Edge Rate dV/dt VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −20 mA +20 mA −0.5V to VCC +0.5V ± 70 mA 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of SCAN circuits outside databook specifications. ± 70 mA +175˚C −65˚C to +150˚C DC Electrical Characteristics Symbol Parameter VCC (V) Military TA = −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low 4.5 0.8 Input Voltage 5.5 0.8 Minimum High 4.5 3.15 Output Voltage 5.5 4.15 4.5 2.4 5.5 2.4 Maximum Low 4.5 0.1 Output Voltage 5.5 0.1 4.5 0.55 5.5 0.55 5.5 ± 1.0 Maximum Input V VOUT = 0.1V V or VCC −0.1V VOUT = 0.1V V or VCC −0.1V IOUT = −50 µA V V VIN = VIL or VIH IOH = −24 mA IOUT = 50 µA V VIN = VIL or VIH IOL = 48 mA µA VI = VCC, GND VI = VCC VI = GND VI = GND Leakage Current IIN TDI, TMS Maximum Input 5.5 Leakage Minimum Input 5.5 3.7 µA −385 µA −160 µA Leakage IOLD Minimum Dynamic IOHD Output Current (Note 3) IOZT Maximum I/O IOS 5.5 63 mA −27 mA VOLD = 0.8V Max VOHD = 2.0V Min VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Leakage Current 5.5 ± 11.0 µA Output Short 5.5 −100 mA (min) 5.5 168 µA VO = High µA TDI, TMS = VCC VO = High VO = 0V Circuit Current ICC Maximum Quiescent Supply Current 5.5 930 TDI, TMS = GND 9 www.national.com DC Electrical Characteristics Symbol Parameter (Continued) VCC (V) Military TA = −55˚C to +125˚C Units Conditions Guaranteed Limits ICCt Maximum ICC Per Input 5.5 2.0 mA 5.5 2.15 mA VI = VCC–2.1V VI = VCC–2.1V TDI/TMS Pin, test one with the other floating Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Noise Specifications Symbol Parameter Military TA = −55˚C to +125˚C VCC (V) Units Guaranteed Limits VOLP Maximum High 5.0 0.8 V 5.0 -0.8 V Output Noise (Notes 4, 5) VOLV Minimum Low Output Noise (Notes 4, 5) Note 4: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched LOW and one output held LOW. Note 5: Maximum number of outputs that can switch simultaneously is n. (n-1) outputs are switched HIGH and one output held HIGH. AC Electrical Characteristics Normal Operation Symbol Parameter tPLH, Propagation Delay tPHL A to B, B to A tPLZ, Disable Time Military VCC (V) (Note 7) 5.0 5.0 tPHZ tPZL, Enable Time 5.0 tPZH www.national.com Units TA = −55˚C to +125˚C CL = 50 pF 10 Min Max 1.6 10.0 1.6 11.0 1.2 10.0 1.2 9.5 1.6 13.0 1.6 11.0 ns ns ns AC Electrical Characteristics Scan Test Operation Symbol Parameter tPLH, Propagation Delay tPHL TCK to TDO tPLZ, Disable Time tPHZ TCK to TDO tPZL, Enable Time tPZH TCK to TDO tPLH, Propagation Delay tPHL TCK to Data Out Military VCC (V) (Note 7) Units TA = −55˚C to +125˚C CL = 50 pF 5.0 5.0 5.0 5.0 Min Max 2.8 15.8 2.8 15.8 2.0 12.8 2.0 12.8 2.4 16.7 2.4 16.7 4.0 21.7 4.0 21.7 ns ns ns ns During Update-DR State tPLH, Propagation Delay tPHL TCK to Data Out 4.0 21.2 5.0 4.0 21.2 5.0 4.4 23.0 4.4 23.0 3.2 19.6 3.2 19.6 2.8 20.9 2.8 20.9 2.8 21.8 2.8 21.8 4.0 22.6 4.0 22.6 3.2 23.7 3.2 23.7 3.6 24.9 3.6 24.9 ns During Update-IR State tPLH, Propagation Delay tPHL TCK to Data Out ns During Test Logic Reset State tPLZ, Propagation Delay tPHZ TCK to Data Out 5.0 ns During Update-DR State tPLZ, Propagation Delay tPHZ TCK to Data Out 5.0 ns During Update-IR State tPLZ, Propagation Delay tPHZ TCK to Data Out 5.0 ns During Test Logic Reset State tPZL, Propagation Delay tPZH TCK to Data Out 5.0 ns During Update-DR State tPZL, Propagation Delay tPZH TCK to Data Out 5.0 ns During Update-IR State tPZL, Propagation Delay tPZH TCK to Data Out 5.0 ns During Test Logic Reset State Note 6: All Propagation Delays involving TCK are measured from the falling edge of TCK. 11 www.national.com AC Operating Requirements Scan Test Operation Symbol Parameter VCC (V) (Note 7) Military TA = −55˚C to +125˚C CL = 50 pF Units Guaranteed Minimum tS Setup Time, H or L 5.0 0.0 ns 5.0 6.5 ns 5.0 0.0 ns 5.0 4.0 ns 5.0 0.0 ns 5.0 4.0 ns 5.0 1.0 ns 5.0 4.0 ns 5.0 7.0 ns 5.0 2.0 ns 5.0 1.0 ns 5.0 3.5 ns H 12.0 ns L 5.0 Data to TCK (Note 8) tH Hold Time, H or L TCK to Data (Note 8) tS Setup Time, H or L G1 , G2 to TCK (Note 9) tH Hold Time, H or L TCK to G1, G2 (Note 9) tS Setup Time, H or L DIR1, DIR2 to TCK (Note 11) tH Hold Time, H or L TCK to DIR1, DIR2 (Note 11) tS Setup Time, H or L Internal AOEn, BOEn to TCK (Note 10) tH Hold Time, H or L TCK to Internal AOEn, BOEn (Note 10) tS Setup Time, H or L TMS to TCK tH Hold Time, H or L TCK to TMS tS Setup Time, H or L TDI to TCK tH Hold Time, H or L TCK to TDI tW fmax Pulse Width Maximum TCK 5.0 5.0 25 MHz 5.0 100 ns 0.0 100 ms Clock Frequency TPU Wait Time, Power Up to TCK TDN Power Down Delay Note 7: Voltage Range 5.0 is 5.0V ± 0.5V. All Input Timing Delays involving TCK are measured from the rising edge of TCK. Note 8: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26, 27–35, 36–44, 45–53, 54–62, 63–71). Note 9: Timing pertains to BSR 74 and 78 only. Note 10: Timing pertains to BSR 72, 73, 76 and 77 only. Note 11: Timing pertains to BSR 75 and 79 only. www.national.com 12 Capacitance Symbol Parameter Typ Units 4 pF Input/Output Capacitance 20 pF Conditions VCC = 5.0V VCC = 5.0V Power Dissipation 41 pF VCC = 5.0V CIN Input Pin Capacitance CI/O CPD Capacitance Pad Diagram DS100320-24 13 www.national.com SCAN18245T Die Information Die Revision Z Die ID Y8J245 Die Size (X) 4310 µm Die Size (Y) 4310 µm Die Thickness 14 mil Substrate Bias VCC (optional) Backside Coating None Pad Locations Signal Signal Number Name 1 TMS Pad Location (Note 12) −8.58, 77.81 2 B10 −19.94, 77.81 3 DIR1 −30.50, 77.81 4 B11 −40.98, 77.81 5 B12 −53.59, 77.81 6 GND −63.73, 77.81 7 B13 −74.47, 77.81 8 B14 −79.73, 62.30 9 VCC −79.73, 51.55 10 B15 11 B16 −79.73, 27.48 12 GND −79.72, 19.46 13 B17 −79.73, 10.09 14 B18 −79.73, 3.46 15 B20 −79.73, −3.43 16 B21 −79.73, −10.06 17 GND −79.72, −19.43 18 B22 −79.73, −27.45 19 B23 −79.73, −36.02 20 VCC −79.73, −46.24 21 B24 22 B25 −74.47, −77.81 23 GND −63.73, −77.81 24 B26 −53.59, −77.81 25 B27 −40.98, −77.81 26 DIR2 −30.50, −77.81 27 B28 −19.94, −77.81 28 TDO −8.58, −77.81 29 TCK 5.54, −77.81 30 A28 19.94, −77.81 31 G2 30.50, −77.81 32 A27 40.98, −77.81 33 A26 53.59, −77.81 34 GND 63.73, −77.81 35 A25 74.47, −77.81 36 A24 79.73, −62.27 −79.73, 46.28 −79.73, 36.05 −79.73, −51.52 www.national.com −79.73, −62.27 14 Pad Locations (Continued) Signal Signal Number Name Pad Location (Note 12) 37 VCC 38 A23 39 A22 79.73, −27.40 40 GND 79.73, −19.43 41 A21 79.73, −10.06 42 A20 79.73, −3.43 43 A18 79.73, 3.46 44 A17 79.73, 10.09 45 GND 79.72, 19.46 46 A16 79.73, 27.43 47 A15 79.73, 36.05 48 VCC 79.73, 46.26 49 A14 50 A13 74.47, 77.81 51 GND 63.73, 77.81 52 A12 53.59, 77.81 53 A11 40.98, 77.81 54 G1 30.50, 77.81 55 A10 19.94, 77.81 56 TDI 5.54, 77.81 79.73, −51.50 79.73, −46.23 79.73, −36.02 79.73, 51.54 79.73, 62.30 Note 12: X, Y coordinates measured in mils from center of die. 15 www.national.com SCAN18245T Non-Inverting Transceiver with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Ceramic Flatpak (F) NS Package Number WA56A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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