NSC SCAN182245ASSCX

SCAN182245A
Non-Inverting Transceiver with
25X Series Resistor Outputs
General Description
Features
The SCAN182245A is a high performance BiCMOS bidirectional line driver featuring separate data inputs organized
into dual 9-bit bytes with byte-oriented output enable and
direction control signals. This device is compliant with
IEEE 1149.1 Standard Test Access Port and Boundary
Scan Architecture with the incorporation of the defined
boundary-scan test logic and test access port consisting of
Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK).
Y
High performance BiCMOS technology
25X series resistors in outputs eliminate the need for
external terminating resistors
Dual output enable control signals
TRI-STATEÉ outputs for bus-oriented applications
25 mil pitch SSOP (Shrink Small Outline Package)
IEEE 1149.1 (JTAG) Compliant
Includes CLAMP, IDCODE and HIGHZ instructions
Additional instructions SAMPLE-IN, SAMPLE-OUT and
EXTEST-OUT
Power Up TRI-STATE for hot insert
Member of National’s SCAN Products
Y
Y
Y
Y
Y
Y
Y
Y
Y
Connection Diagram
Pin Names
A1(0– 8)
B1(0– 8)
A2(0– 8)
B2(0– 8)
G1, G2
DIR1, DIR2
Description
Side A1 Inputs or TRI-STATE Outputs
Side B1 Inputs or TRI-STATE Outputs
Side A2 Inputs or TRI-STATE Outputs
Side B2 Inputs or TRI-STATE Outputs
Output Enable Pins (Active Low)
Direction of Data Flow Pins
Order Number
Description
SCAN182245ASSC
SCAN182245ASSCX
SCAN182245AFMQB
SSOP in Tubes
SSOP Tape and Reel
Flatpak Military
TL/F/11657 – 1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1996 National Semiconductor Corporation
TL/F/11657
RRD-B30M36/Printed in U. S. A.
http://www.national.com
SCAN182245A Transceiver with 25X Series Resistor Outputs
February 1996
Truth Tables
Functional Description
Inputs
² G1
DIR1
L
L
L
L
H
L
L
H
H
X
Inputs
H
L
X
Z
²
² G2
DIR2
L
L
L
L
H
L
L
H
H
X
e
e
e
e
e
A1(0 – 8)
H
L
H
L
Z
w
w
x
x
A2(0 – 8)
H
L
H
L
Z
The SCAN182245A consists of two sets of nine non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus-oriented applications. Direction pins (DIR1
and DIR2) LOW enables data from B ports to A ports, when
HIGH enables data from A ports to B ports. The Output
Enable pins (G1 and G2) when HIGH disables both A and B
ports by placing them in a high impedance condition.
B1(0 – 8)
H
L
H
L
Z
B2(0 – 8)
w
w
x
x
H
L
H
L
Z
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
Inactive-to-Active transition must occur to enable outputs upon
power-up.
Block Diagrams
A1, B1, G1 and DIR1
TL/F/11657 – 2
Note: BSR stands for Boundary Scan Register.
http://www.national.com
2
Block Diagrams (Continued)
Tap Controller
TL/F/11657 – 18
A2, B2, G2 and DIR2
TL/F/11657 – 3
Note: BSR stands for Boundary Scan Register.
3
http://www.national.com
Description of BOUNDARY-SCAN Circuitry
The INSTRUCTION register is an 8-bit register which captures the default value of 10000001 (SAMPLE/PRELOAD)
during the CAPTURE-IR instruction command. The benefit
of capturing SAMPLE/PRELOAD as the default instruction
during CAPTURE-IR is that the user is no longer required to
shift in the 8-bit instruction for SAMPLE/PRELOAD. The sequence of: CAPTURE-IR x EXIT1-IR x UPDATE-IR
will update the SAMPLE/PRELOAD instruction. For more
information refer to the section on instruction definitions.
The scan cells used in the BOUNDARY-SCAN register are
one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system
data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 Figure 10-11 for a
further description of scan cell TYPE1 and Figure 10-12 for
a further description of scan cell TYPE2.)
Scan cell TYPE1 is located on each system input pin while
scan cell TYPE2 is located at each system output pin as
well as at each of the two internal active-high output enable
signals. AOE controls the activity of the A-outputs while
BOE controls the activity of the B-outputs. Each will activate
their respective outputs by loading a logic high.
The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.
Instruction Register Scan Chain Definition
Bypass Register Scan Chain Definition
Logic 0
TL/F/11657 – 10
MSB
TL/F/11657–17
SCAN182245A Product IDCODE
(32-Bit Code per IEEE 1149.1)
Version Entity
0000
Part
Number
Manufacturer Required by
ID
1149.1
111111 0000000000 00000001111
MSB
http://www.national.com
1
LSB
4
x LSB
Instruction Code
Instruction
00000000
EXTEST
10000001
SAMPLE/PRELOAD
10000010
CLAMP
00000011
HIGH-Z
01000001
SAMPLE-IN
01000010
SAMPLE-OUT
00100010
EXTEST-OUT
10101010
IDCODE
11111111
BYPASS
All Others
BYPASS
Description of BOUNDARY-SCAN Circuitry (Continued)
Scan Cell TYPE1
TL/F/11657 – 11
Scan Cell TYPE2
TL/F/11657 – 12
5
http://www.national.com
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register
Scan Chain Definition (80 Bits in Length)
TL/F/11657 – 32
http://www.national.com
6
Description of BOUNDARY-SCAN Circuitry (Continued)
Input BOUNDARY-SCAN Register
Scan Chain Definition (40 Bits in Length)
When Sample In is Active
TL/F/11657 – 33
7
http://www.national.com
Description of BOUNDARY-SCAN Circuitry (Continued)
Output BOUNDARY-SCAN Register
Scan Chain Definition (40 Bits in Length)
When Sample Out and EXTEST-Out are Active
TL/F/11657 – 34
http://www.national.com
8
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register Definition Index
Bit No.
Pin Name
Pin No.
Pin Type
3
54
Input
Input
Internal
Internal
Input
Input
Internal
Internal
TYPE1
TYPE1
TYPE2
TYPE2
TYPE1
TYPE1
TYPE2
TYPE2
Control
Signals
55
53
52
50
49
47
46
44
43
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A1 –in
A20
A21
A22
A23
A24
A25
A26
A27
A28
42
41
39
38
36
35
33
32
30
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
A2 –in
53
52
51
50
49
48
47
46
45
B10
B11
B12
B13
B14
B15
B16
B17
B18
2
4
5
7
8
10
11
13
14
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
B1 – out
44
43
42
41
40
39
38
37
36
B20
B21
B22
B23
B24
B25
B26
B27
B28
15
16
18
19
21
22
24
25
27
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
B2 – out
35
34
33
32
31
30
29
28
27
B10
B11
B12
B13
B14
B15
B16
B17
B18
2
4
5
7
8
10
11
13
14
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
B1 –in
79
78
77
76
75
74
73
72
DIR1
G1
AOE1
BOE1
DIR2
G2
AOE2
BOE2
71
70
69
68
67
66
65
64
63
A10
A11
A12
A13
A14
A15
A16
A17
A18
62
61
60
59
58
57
56
55
54
26
31
9
Scan Cell Type
http://www.national.com
Description of BOUNDARY-SCAN Circuitry (Continued)
BOUNDARY-SCAN Register Definition Index (Continued)
Bit No.
Pin Name
Pin No.
Pin Type
Scan Cell Type
26
25
24
23
22
21
20
19
18
B20
B21
B22
B23
B24
B25
B26
B27
B28
15
16
18
19
21
22
24
25
27
Input
Input
Input
Input
Input
Input
Input
Input
Input
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
B2 –in
17
16
15
14
13
12
11
10
9
A10
A11
A12
A13
A14
A15
A16
A17
A18
55
53
52
50
49
47
46
44
43
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A1 – out
8
7
6
5
4
3
2
1
0
A20
A21
A22
A23
A24
A25
A26
A27
A28
42
41
39
38
36
35
33
32
30
Output
Output
Output
Output
Output
Output
Output
Output
Output
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
TYPE2
A2 – out
http://www.national.com
10
SCAN ABT Live Insertion and Power Cycling Characteristics
flip-flop. To bring the device out of high impedance, the Gn
input must receive an inactive-to-active transition, a high-tolow transition on Gn in this case to change the state of the
flip-flop. With a low on the Q output of the flip-flop, the NOR
gate is free to allow propagation of a Gn signal.
During power-down , the Power-On-Reset circuitry will become active and reset the flip-flop at approximately 1.8V
VCC. Again, the Q output of the flip-flop returns to a high and
disables the NOR gate from inputs from the Gn pin. The
device will then remain in high impedance for the remaining
ramp down from 1.8V to 0.0V VCC.
Some suggestions to help the designer with live insertion
issues:
SCAN ABT is intended to serve in Live Insertion backplane
applications. It provides 2nd Level Isolation1 which indicates
that while external circuitry to control the output enable pin
is unnecessary, there may be a need to implement differential length backplane connector pins for VCC and GND. As
well, pre-bias circuitry for backplane pins may be necessary
to avoid capacitive loading effects during live insertion.
SCAN ABT provides control of output enable pins during
power cycling via the circuit in Figure A . It essentially controls the Gn pin until VCC reaches a known level.
During power-up , when VCC ramps through the 0.0V to 0.7V
range, all internal device circuitry is inactive, leaving output
and I/O pins of the device in high impedance. From approximately 0.8V to 1.8V VCC, the Power-On-Reset circuitry,
(POR), in Figure A becomes active and maintains device
high impedance mode. The POR does this by providing a
low from its output that resets the flip-flop The output, Q, of
the flip-flop then goes high and disables the NOR gate from
an incidental low input on the Gn pin. After 1.8V VCC, the
POR circuitry becomes inactive and ceases to control the
# The Gn pin can float during power-up until the Power-OnReset circuitry becomes inactive.
# The Gn pin can float on power-down only after the Power-On-Reset has become active.
The description of the functionality of the Power-On-Reset
circuitry can best be described in the diagram of Figure B .
TL/F/11657 – 19
FIGURE A
TL/F/11657 – 20
FIGURE B
1Section 7, ‘‘Design Consideration for Fault Tolerant Backplanes’’, Application Note AN-881.
SCAN ABT includes additional power-on reset circuitry not otherwise included in ABT devices.
11
http://www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Latchup Source Current
Commercial
Military
Storage Temperature
b 65§ C to a 150§ C
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
Plastic
b 55§ C to a 125§ C
Over Voltage Latchup (I/O)
ESD (HBM) Min.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
b 0.5V to a 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
10V
2000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
b 55§ C to a 175§ C
b 55§ C to a 150§ C
VCC Pin Potential to
Ground Pin
b 500 mA
b 300 mA
Recommended Operating
Conditions
b 0.5V to a 7.0V
b 30 mA to a 5.0 mA
Free Air Ambient Temperature
Military
Commercial
b 0.5V to a 5.5V
b 0.5V to VCC
Supply Voltage
Military
Commercial
Twice the Rated IOL (mA)
b 55§ C to a 125§ C
b 40§ C to a 85§ C
a 4.5V to a 5.5V
a 4.5V to a 5.5V
Minimum Input Edge Rate
Data Input
Enable Input
(DV/Dt)
50 mV/ns
20 mV/ns
DC Electrical Characteristics
Symbol
Parameter
VCC
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VCD
Input Clamp Diode Voltage
Min
VOH
Output HIGH Voltage
Min
Mil
VOL
Typ
Max
2.0
Units
Conditions
V
Recognized HIGH Signal
0.8
V
Recognized LOW Signal
b 1.2
V
IIN e b18 mA
2.5
V
IOH e b3 mA
Min
2.0
V
IOH e b24 mA
Comm
Min
2.0
V
IOH e b32 mA
Mil
Min
0.8
V
IOL e 12 mA
Output LOW Voltage
Comm
IIH
Min
Input HIGH Current
All Others
TMS, TDI
Min
0.8
V
Max
5
mA
IOL e 15 mA
Max
5
mA
VIN e VCC
Max
5
mA
VIN e VCC
VIN e 2.7V (Note 1)
IBVI
Input HIGH Current
Breakdown Test
Max
7
mA
VIN e 7.0V
IBVIT
Input HIGH Current
Breakdown Test (I/O)
Max
100
mA
VIN e 5.5V
IIL
Input LOW Current
All Others
TMS, TDI
Max
b5
mA
VIN e 0.5V (Note 1)
Max
b5
mA
VIN e 0.0V
Max
b 385
mA
VIN e 0.0V
VID
Input Leakage Test
IIH a IOZH
Output Leakage Current
Max
50
mA
VOUT e 2.7V
IIL a IOZL
Output Leakage Current
Max
b 50
mA
VOUT e 0.5V
IOZH
Output Leakage Current
Max
50
mA
VOUT e 2.7V
IOZL
Output Leakage Current
Max
b 50
mA
VOUT e 0.5V
0.0
4.75
Note 1: Guaranteed not tested.
http://www.national.com
12
V
IID e 1.9 mA
All Other Pins Grounded
DC Electrical Characteristics (Continued)
VCC
Min
IOS
Symbol
Output Short-Circuit Current
Max
b 100
ICEX
Output HIGH Leakage Current
IZZ
Bus Drainage Test
ICCH
Power Supply Current
ICCL
ICCZ
ICCT
ICCD
Parameter
Power Supply Current
Power Supply Current
Max
Units
b 275
mA
VOUT e 0.0V
Max
50
mA
VOUT e VCC
0.0
100
mA
VOUT e 5.5V
All Others GND
Conditions
Max
250
mA
VOUT e VCC; TDI, TMS e VCC
Max
1.0
mA
VOUT e VCC; TDI, TMS e GND
Max
65
mA
VOUT e LOW; TDI, TMS e VCC
Max
65.8
mA
VOUT e LOW; TDI, TMS e GND
Max
250
mA
TDI, TMS e VCC
Max
1.0
mA
TDI, TMS e GND
Additional ICC/Input
All Other Inputs
Max
2.9
mA
VIN e VCC b 2.1V
TDI, TMS inputs
Max
3
mA
VIN e VCC b 2.1V
0.2
mA/
MHz
Outputs Open
One Bit Toggling, 50% Duty Cycle
Dynamic ICC
No Load
Max
AC Electrical Characteristics
Symbol
Typ
Parameter
VCC*
(V)
Military
Commercial
TA e b55§ C to a 125§ C
CL e 50 pF
TA e b40§ C to a 85§ C
CL e 50 pF
Min
tPLH
tPHL
Propagation Delay
A to B, B to A
tPLZ
tPHZ
Disable Time
tPZL
tPZH
Enable Time
Normal Operation
Typ
Max
Units
Min
Typ
Max
5.0
1.0
1.5
3.1
4.4
5.2
6.5
ns
5.0
1.5
1.5
4.8
5.2
8.6
8.9
ns
5.0
1.5
1.5
5.5
4.6
9.1
8.2
ns
*Voltage Range 5.0V g 0.5V
13
http://www.national.com
AC Electrical Characteristics
Symbol
Parameter
VCC*
(V)
Scan Test Operation
Military
Commercial
TA e b55§ C to a 125§ C
CL e 50 pF
TA e b40§ C to a 85§ C
CL e 50 pF
Min
Typ
Max
Min
Typ
Max
Units
tPLH
tPHL
Propagation Delay
TCK to TDO
5.0
2.9
4.2
6.1
7.7
10.2
12.1
ns
tPLZ
tPHZ
Disable Time
TCK to TDO
5.0
2.1
3.3
5.9
7.4
10.7
12.5
ns
tPZL
tPZH
Enable Time
TCK to TDO
5.0
4.6
2.8
8.7
6.8
13.7
11.5
ns
tPLH
tPHL
Propagation Delay
TCK to Data Out
during Update-DR State
5.0
2.8
4.5
6.3
8.2
10.7
13.0
ns
tPLH
tPHL
Propagation Delay
TCK to Data Out
during Update-IR State
5.0
3.3
5.0
7.2
9.3
12.2
14.8
ns
tPLH
tPHL
Propagation Delay
TCK to Data Out
during Test Logic
Reset State
8.4
10.8
14.0
17.2
ns
5.0
3.7
5.7
tPLZ
tPHZ
Disable Time
TCK to Data Out
during Update-DR State
5.0
2.8
3.5
7.6
8.4
13.9
14.5
ns
tPLZ
tPHZ
Disable Time
TCK to Data Out
during Update-IR State
5.0
3.6
3.8
8.7
9.2
15.1
15.9
ns
tPLZ
tPHZ
Disable Time
TCK to Data Out
during Test Logic
Reset State
4.0
4.2
9.8
9.9
17.1
16.6
ns
5.0
tPZL
tPZH
Enable Time
TCK to Data Out
during Update-DR State
5.0
4.4
3.0
9.3
7.5
15.5
13.3
ns
tPZL
tPZH
Enable Time
TCK to Data Out
during Update-IR State
5.0
5.2
3.9
10.7
9.0
17.4
15.4
ns
tPZL
tPZH
Enable Time
TCK to Data Out
during Test Logic
Reset State
5.7
3.0
12.0
10.2
19.8
17.6
ns
5.0
*Voltage Range 5.0V g 0.5V
All Propagation Delays involving TCK are measured from the falling edge of TCK.
http://www.national.com
14
AC Operating Requirements Scan Test Operation
Symbol
VCC*
(V)
Parameter
Military
Commercial
TA e b55§ C to a 125§ C
CL e 50 pF
TA e b40§ C to a 85§ C
CL e 50 pF
Units
Guaranteed Minimum
tS
Setup Time
Data to TCK (Note 1)
5.0
4.8
ns
tH
Hold Time
Data to TCK (Note 1)
5.0
2.5
ns
tS
Setup Time, H or L
G1, G2 to TCK (Note 2)
5.0
4.1
ns
tH
Hold Time, H or L
TCK to G1, G2 (Note 2)
5.0
1.7
ns
tS
Setup Time, H or L
DIR1, DIR2 to TCK (Note 4)
5.0
4.2
ns
tH
Hold Time, H or L
TCK to DIR1, DIR2 (Note 4)
5.0
2.3
ns
tS
Setup Time
Internal OE to TCK (Note 3)
5.0
3.8
ns
tH
Hold Time, H or L
TCK to Internal OE (Note 3)
5.0
2.3
ns
tS
Setup Time, H or L
TMS to TCK
5.0
8.7
ns
tH
Hold Time, H or L
TCK to TMS
5.0
1.5
ns
tS
Setup Time, H or L
TDI to TCK
5.0
6.7
ns
tH
Hold Time, H or L
TCK to TDI
5.0
5.0
ns
tW
Pulse Width TCK
5.0
10.2
8.5
ns
fmax
Maximum TCK
Clock Frequency
5.0
50
MHz
tPU
Wait Time,
Power Up to TCK
5.0
100
ns
tDN
Power Down Delay
0.0
100
ms
H
L
*Voltage Range 5.0V g 0.5V
All Input Timing Delays involving TCK are measured from the rising edge of TCK.
Note 1: Timing pertains to the TYPE1 BSR and TYPE2 BSR after the buffer (BSR 0–8, 9–17, 18–26, 27–35, 36–44, 45–53, 54–62, 63–71).
Note 2: Timing pertains to BSR 74 and 78 only.
Note 3: Timing pertains to BSR 72, 73, 76 and 77 only.
Note 4: Timing pertains to BSR 75 and 79 only.
Capacitance
Typ
Units
CIN
Input Capacitance
5.9
pF
Conditions, TA e 25§ C
VCC e 0.0V (Gn, DIRn)
CI/O (Note 1)
Output Capacitance
13.7
pF
VCC e 5.0V (An, Bn)
Symbol
Parameter
Note 1: CI/O is measured at frequency f e 1 MHz, per MIL-STD-883B, Method 3012.
15
http://www.national.com
Ordering Information
SCAN
18
2245
Serially Controlled Access Network
SS
C
X
Special Variations
X e Tape and Reel
QB e Military grade device with
environmental and burn-in
processing.
18-Bit Logic
Function Type
Technology Designator
T e TTL Input TTL Output CMOS Device
C e CMOS Input/Output CMOS Device
B e Bipolar TTL Device
E e ECL Device
A e BiCMOS Device
F e TTL Input/CMOS Output CMOS Device
http://www.national.com
A
Temperature Range
C e Commercial (b40§ C to
a 85§ C)
M e Military (b55§ C to a 125§ C)
Package Code
SS e 25 mil Pitch (JEDEC) SSOP
F e 25 mil Pitch Ceramic Flatpak
16
Physical Dimensions inches (millimeters)
56-Lead SSOP (0.300× Wide) (SS)
Order Number SCAN182245ASSC or SCAN182245ASSCX
NS Package Number MS56A
17
http://www.national.com
SCAN182245A Transceiver with 25X Series Resistor Outputs
Physical Dimensions inches (millimeters) (Continued)
56-Lead Ceramic Flatpak (F)
Order Number SCAN182245AFMQB
NS Package Number WA56A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
http://www.national.com
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Europe
Fax: a49 (0) 180-530 85 86
Email: europe.support @ nsc.com
Deutsch Tel: a49 (0) 180-530 85 85
English Tel: a49 (0) 180-532 78 32
Fran3ais Tel: a49 (0) 180-532 93 58
Italiano Tel: a49 (0) 180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2308
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.