APPLICATION NOTE Replacing Micron® N25Q256A with Macronix MX25U25635F 1. Introduction This application note serves as a guide to replace the Micron® N25Q256A with the Macronix MX25U25635F 1.8V 256Mb SPI flash. The document does not provide detailed information on each individual device, but highlights the similarities and differences between them. The comparison covers the general features, performance, command codes, and other differences. The devices are command compatible for basic read, program, and erase operations. The devices are essentially pin compatible if the HOLD# function is not used. There are two types of MX25U25635F products: 1. MX25U25635FxxI-10G: Supports clock frequency up to 108MHz for all protocols 2. MX25U25635FxxI-08G: Supports clock frequency up to 133MHz for all protocols The information provided in this document is based on datasheets listed in Section 9. Newer versions of the datasheets may override the contents of this document. P/N: AN0210 1 REV. 1, MAR. 14, 2013 APPLICATION NOTE 2. Feature Comparison Both flash device families have similar features and functions as shown in Table 2-1. Significant differences are highlighted in blue and may require special considerations. Table 2-1: Key Feature Comparison Micron® N25Q256A Type / Function VCC Voltage Range 1.7V-2.0V 1.65V-2.0V Fast Read (1-1-1) YES YES Dual Output (DREAD) (1-1-2) YES YES Dual I/O (2READ) (1-2-2) YES YES Dual Peripheral Interface (2-2-2) YES - Quad Output (QREAD) (1-1-4) YES YES Quad I/O (4READ) (1-4-4) YES YES Quad Peripheral Interface (QPI) (4-4-4) YES YES (1-1-1) 54MHz 108MHz(x1) 108MHz(x2) 108MHz(x4) 108MHz(x1) 108MHz(x2) 108MHz(x4) YES 55MHz 108MHz(x1) 108MHz(x2) 108MHz(x4) 133MHz(x1) [only -08G] 133MHz(x2) [only -08G] 133MHz(x4) [only -08G] - (1-1-2) YES - (1-2-2) YES - (2-2-2) YES - (1-1-4) YES - (1-4-4) YES YES (4-4-4) YES YES YES YES Normal Read Clock Frequency Fast Read Clock Frequency 2x I/O: 8dummy cycles 4x I/O: 8dummy cycles Fast Read Clock Frequency 2x I/O: 10dummy cycles 4x I/O: 10dummy cycles XIP / Performance Enhanced Mode XIP Mode Set at Power-on Sector Size 4KB/64KB 4KB/32KB/64KB Program Buffer Size 256Byte 256Byte Security OTP 64Byte 512Byte Program/Erase Suspend & Resume YES YES Read Enhance Mode YES YES Wrap Around Read Mode YES YES Configurable Dummy Cycles YES YES Adjustable Output Driver YES YES YES Available with either Hold or Reset Top/Bottom YES Top/Bottom Individual Sector/Block Protection Mode YES - Program/Erase Cycles 100K 100K S/W Reset Command HOLD# / RESET# Pin Block Protection Mode P/N: AN0210 Macronix MX25U25635F 2 Reset only REV. 1, MAR. 14, 2013 APPLICATION NOTE Table 2-1: Feature Comparison – Continued Micron® N25Q256A Macronix MX25U25635F - YES 8-WSON (8x6mm) YES YES 16-SOP (300mil) YES YES 24-TPBGA (8x6mm) YES - Packages 8-WSON (8x6mm 3.4 x4.3 EP) P/N: AN0210 3 REV. 1, MAR. 14, 2013 APPLICATION NOTE 3. Key Feature and Operational Differences This section will describe some of the key features and operational differences in depth. 3-1. Address Protocol Support Both the Macronix MX25U25635F and the Micron® N25Q256A support three different methods to access the full 256Mb memory space as shown in Table 3-1. However, there are slight differences in their implementations which are discussed in the following section. Table 3-1: 256Mb Address Methods Micron® N25Q256A Macronix MX25U25635F 4-Byte Mode YES YES Extended Address Register (EAR) YES YES 4-Byte Command Set YES YES Address Method 3-1-1. 4-Byte Mode 4-Byte mode is supported by both products. In 4-Byte mode, the legacy command set is used, but 4-bytes of address are sent during the address phase. Although both Macronix and Micron® support the same command codes to enter and exit 4-Byte Mode, the Macronix EN4B and EX4B commands do not require the WREN command to be issued first. The Macronix MX25U25635F enters 4-Byte mode by using the EN4B command and exits 4-Byte addressing Mode with the EX4B command. A Power-cycle or Reset of the MX25U25635F will also exit 4-Byte mode and return it to the default 3-Byte mode. Table 3-2 shows the status bit settings and commands required to enter and exit 4-Byte addressing mode. Table 3-2: Related Register: Configuration Register Micron® N25Q256A P/N: AN0210 Macronix MX25U25635F Related Register Nonvolatile Configuration Register Configuration Register Related Register Bit Bit [0]- Address bytes Bit [5]- 4 BYTE Bit Status 0=Enable 4-Byte Address 1=Enable 3-Byte Address(Default) 1=Enable 4-Byte Address 0=Enable 3-Byte Address(Default) Enable/Write Command ENTER 4-BYTE MODE (B7h) EN4B (B7h) Disable/Clear Command EXIT 4-BYTE MODE (E9h) EX4B (E9h) WREN Required Not Required 4 REV. 1, MAR. 14, 2013 APPLICATION NOTE 3-1-2. Extended Address Register Both products support an Extended Address Register (EAR). If the system only supports 3-Byte addressing, the Extended Address Register mode is an alternative method that can be used to access memory beyond the 128Mb limit. The EAR supplies the higher address bits to form the starting address for read operations. By setting up the Extended Address register Bit [0](A24), the user can use the original 3-byte address to access both Top and Bottom 128Mb. Please note that the default state of A24 is “0” in both products, which allows access to the Bottom 128Mb of memory. The WREAR (C5h) command can be used to change the state of A24 in either device. Both devices need to input the WREN Command before issuing the WREAR command. In addition, both products support the RDEAR (C8h) command to read the state of the EAR bit. Table 3-3: Related Register: Extended Address Register Micron® N25Q256A Related Register Related Bit Nonvolatile Configuration Register Bit [1]- 128Mb segment select 0=Top 128Mb segment Bit Status 1=Bottom 128Mb segment (Default) Macronix MX25U25635F Extended Address Register Extended Address Register Bit [0] Bit [0] 1=Top 128Mb segment 1=Top 128Mb segment 0=Bottom 128Mb segment (Default) WRITE EXTENDED ADDRESS REGISTER (C5h) 0=Bottom 128Mb segment (Default) Write Command WRITE NONVOLATILE CONFIGURATION REGISTER (B1h) Read Command READ NONVOLATILE CONFIGURATION REGISTER command (B1h) READ EXTENDED ADDRESS REGISTER (C8h) RDEAR (C8h) WREN Required Required Required WREAR (C5h) Table 3-4: Extended Address Register Bits Micron® N25Q256A -Extended Address Register Bits Default Status Type Bits Default Status Description Type Bit 7 volatile Bit 7 A31 0 volatile Bit 6 volatile Bit 6 A30 0 volatile volatile Bit 5 A29 0 volatile volatile Bit 4 A28 0 volatile volatile Bit 3 A27 0 volatile Bit 2 volatile Bit 2 A26 0 volatile Bit 1 volatile Bit 1 A25 0 volatile volatile Bit 0 A24 0 volatile Bit 5 Bit 4 Bit 3 Bit 0 P/N: AN0210 Description MX25U25635F -Extended Address Register A[31:25]; Reserved A24 0 5 REV. 1, MAR. 14, 2013 APPLICATION NOTE 3-1-3. 4-Byte Command Set The MX25U25635F and Micron® N25Q256A have additional new commands for 4-byte addressing. The operation of 4-byte address command sets are very similar to the original 3-byte address command sets. The only difference is that all of the 4-byte address commands require that the instruction code be followed by 4-bytes of address (A31-A0). The 4-Byte address command set eliminates the need to enter or exit 4-Byte addressing mode. Table 3-4: 4-Byte Command Set Instruction 4-Byte Command Set P/N: AN0210 Description Micron® N25Q256A Macronix MX25U25635F READ4B Read Data Bytes 13h 13h FAST_READ4B Read Data Bytes at Higher Speed 0Ch 0Ch DREAD4B Dual Output Fast Read 3Ch 3Ch 2READ4B Dual Input/Output Fast Read BCh BCh QREAD4B Quad Output Fast Read 6Ch 6Ch 4READ4B Quad Input/Output Fast Read ECh ECh PP4B Page Program - 12h 4PP4B Quad Page Program (1-1-4) - 3Eh SE4B Sector Erase - 21h BE4B Block Erase 64KB - DCh BE32K4B Block Erase 32KB - 5Ch 6 REV. 1, MAR. 14, 2013 APPLICATION NOTE 3-2. Status Register BP Protection Differences Both the Micron® and Macronix devices use BP[3:0] bits to select memory areas for protection. The Micron® N25Q256A Block Protection bits BP[3:0] are located in Status Register (bits 6 and [4:2]). The Top/Bottom bit is located in Status Register bit 5 and selects whether block protection starts at the top or bottom of memory. The BP[3:0] and Top/Bottom bits are nonvolatile and reprogrammable. The MX25U25635F Block Protection bits BP[3:0] are located in Status Register bits [5:2]. The top/bottom starting point is controlled by the TB bit, which is located in Configuration Register bit 3. The default setting of the TB bit starts block protection at the top of memory. If the ‘bottom’ starting point is selected, it can never be returned to the ‘top’ starting point. The BP[3:0] bits are all nonvolatile and reprogrammable. The TB bit is nonvolatile and one-time-programmable. 3-3. Individual Sector/Block Protection Differences The Micron® N25Q256A has the ability to protect individual 64KB sectors/blocks of memory independent of the nonvolatile BP bit configuration in the Status Register. The MX25U25635F does not support Individual Sector/Block Protection function. 3-4. QPI Differences Micron®’s Quad I/O mode is entered by setting a bit in the Nonvolatile Configuration Register, which remembers this mode after power cycles, or by setting a bit in the Enhanced Volatile Configuration Register and is reset after a power cycle. The MX25U25635F requires an EQIO (35h) command to enter the equivalent QPI mode. This mode can be terminated by a RSTQIO (F5h) command, a power cycle, hardware reset, or software reset. (Please note that on the 8-WSON package, hardware RESET# is disabled during QPI or Quad mode). 3-5. XIP Differences The XIP (eXecute In Place) feature (Macronix refers to this as Performance Enhance Mode) is only used during Fast Read operations and eliminates the need to input read commands prior to entering an address and reading data. This is an overhead reduction feature that reduces data latency. Both devices offer this feature, but entry and exit methods are different and not all I/O modes are supported by Macronix. As can be seen in Table 2-1 above, Macronix only supports XIP in Quad I/O (1-4-4) and QPI (4-4-4) modes. Micron® supports XIP in all Fast Read I/O modes. P/N: AN0210 7 REV. 1, MAR. 14, 2013 APPLICATION NOTE 3-5-1. Entering XIP Mode The Micron® N25Q256A can be configured to power-up in any XIP mode or entered later using the Volatile Configuration Register (depends on feature set selected by part number) and/or setting the XIP confirm bit to ‘0’ (first dummy cycle bit on DQ0 of any Fast Read command). The MX25U25635F enters XIP mode whenever all four bits of the first and second dummy cycles of a 4READ instruction are not equal. 3-5-2. Exiting XIP Mode The Micron® N25Q256A will automatically exit XIP mode after the current read operation if the XIP confirm bit is not ‘0’ (first dummy cycle bit on DQ0). The MX25U25635F will exit XIP mode if any of the bits of the first and second dummy cycles are equal. In 3-byte addressing mode, this can be accomplished by sending command FFh or 00h on SIO0 (SPI mode) and FFFFFFFFh (QPI mode). In 4-byte addressing, it can be accomplished by sending command 3FFh on SIO0 (SPI mode) and FFFFFFFFFFh (QPI mode). 3-6. Status Register and Configuration Register Differences Both devices use status and configuration registers to control device behavior and report status. The registers and bits used are not identical. Please refer to the datasheets to compare register definitions and usages. P/N: AN0210 8 REV. 1, MAR. 14, 2013 APPLICATION NOTE 4. Package and Pinout Comparison The Macronix MX25U25635F and Micron® N25Q256A are available in 16-SOP and 8-WSON packages with identical footprints. Please consult the latest Macronix datasheet for additional package options. Pinout definitions of the 16-SOP and 8-WSON packages are the same with the exceptions listed in Tables 4-1 and 4-2. On pin 1 of the 16-SOP package, Macronix has DNU/SIO3, but Micron® has either HOLD#/DQ3 or a RESET#/DQ3. If the Micron® device has RESET#/DQ3, then the devices are pin compatible. If the Micron® device has HOLD#/DQ3, but the HOLD# function is not used or pin 1 is pulled high, then the devices are also pin compatible. If Quad mode is not used, the MX25U25635F DNU/SIO3 pin should be pulled high with a resistor to VCC or left unconnected. Table 4-1: 16-SOP Pin Definition Comparison Table Micron® N25Q256A Macronix MX25U25635F HOLD#/DQ3 DNU#/SIO3 DNU NC Pin #3 RESET#/DNU RESET# Pin #9 W#/VPP/DQ2 WP#/SIO2 16-SOP (300mil) Pin #1 Pin #4, 5, 6, 11, 12, 13, & 14 Comments HOLD# not supported by Macronix. Dedicated Micron® part numbers offer RESET# instead of HOLD#. No pin conflict. RESET# is supported by both products. Dedicated Micron® part numbers offer DNU instead of RESET# Macronix does not support VPP On pin 7 of the 8-WSON package, Macronix has RESET#/SIO3, but Micron® has either HOLD#/DQ3 or RESET#/DQ3. If the Micron® device has RESET#/DQ3, then the devices are pin compatible. If the Micron® device has a HOLD#/DQ3, but the HOLD# function is not used or pin 7 is pulled high, then the devices are also pin compatible. Table 4-2: 8-WSON Pin Definition Comparison Table Micron® N25Q256A Macronix MX25U25635F Pin #3 W#/ VPP /DQ2 WP#/SIO2 Pin #7 HOLD#/DQ3 RESET#/SIO3 8-WSON (8mmx6mm) P/N: AN0210 9 Comments Macronix does not support VPP HOLD# not supported by Macronix. Dedicated Micron® part numbers offer RESET# instead of HOLD#. REV. 1, MAR. 14, 2013 APPLICATION NOTE 5. Performance Comparison Tables 5-1 and 5-2 show that the two devices have similar AC and DC performance. Table 5-1: AC Parameter Comparison Parameter Symbol Micron® Macronix Clock High Time Clock Low Time tCH tCL tCH tCL Clock Low to Output Valid tCLQV tCLQV Data In Setup Time Data In Hold Time tDVCH tCHDX tDVCH tCHDX Page Program Time (256 Bytes) tPP tPP Erase 4KB Subsector/ Sector tSSE tSE Erase 32KB Sector - tBE32 Erase 64KB Sector/Block tSE tBE Bulk Erase / Chip Erase tBE tCE Condition Micron® N25Q256A min min max @10pF max @15pF max @30pF min min typ max typ max typ max typ max typ max 4ns 4ns 5ns 7ns 2ns 3ns 0.5ms 5ms 250ms 0.8s 0.7s 3s 240s 480s Macronix MX25U25635F 4.5/3.3ns(1) 4.5/3.3ns(1) 6ns 8ns 2ns 5ns 1.2ms 3ms 60ms 0.2s 0.25s 1s 0.5s 2s 200s 320s Note1: Please note that only MX25U25635FZ4I-08G supports tCH/tCL=3.3 ns. All other products can only support 4.5ns. Table 5-2: DC Parameter Comparison Parameter Leakage Current ILI/ILO ILI/ILO Standby Current ICC1 ISB1 Deep Power Down Current ICC2 ISB2 VCC Read Current (Fast Read) VCC Program Current VCC Write Status Register Current VCC Erase Current P/N: AN0210 Symbol Micron® Macronix Condition Micron® N25Q256A Macronix MX25U25635F +/- 2uA 100uA 20uA +/- 2uA 30uA 100uA 5uA 20uA - 25mA 20mA 20mA 6mA 20mA 15mA 25mA ICC4 ICC2 max typ max typ max max @ 133MHz (4-4-4) [-08G only] max @ 108MHz (4-4-4) max @ 84MHz max @ 54MHz max ICC5 ICC3 max 20mA 20mA ICC6 ICC4, ICC5 max 20mA 25mA ICC3 ICC1 10 REV. 1, MAR. 14, 2013 APPLICATION NOTE 6. Command Code Comparison Both devices use similar basic command set, but there are a few minor differences highlighted in Table 6-1. For 4-byte address command set, please see Table 3-5. Table 6-1: Command Code Comparison Instruction Type Read ID Read Write Register P/N: AN0210 Instruction Description RDID REMS READ FAST_READ DOFR DIOFR QOFR QIOFR RDSFDP WREN WRDI PP 4PP SE BE 32K SE 64K CE RDSR RDCR WRSR RDSCUR WRSCUR RDLR WRLR RFSR CLFSR - Read Identification Read Electronic Manufacturer ID & Signature Read Data Bytes Read Data Bytes at Higher Speed Dual Output Fast Read Dual Input/Output Fast Read Quad Output Fast Read Quad Input/Output Fast Read Read Serial Flash Discoverable Parameters Write Enable Write Disable Page Program Dual Input Fast Program (1-1-2) Quad Input Fast Program (1-1-4) Quad Page Program (1-4-4) Sector Erase 4KB Block Erase 32KB Block Erase 64KB Chip Erase Read Status Register Read Configuration Register Write Status Register Read Security Register Write Security Register Read Lock Register Write Lock Register Read Flag Status Register Clear Flag Status Register Read Non-volatile Configuration Register Write Non-volatile Configuration Register Read Volatile Configuration Register Write Volatile Configuration Register Read Enhance Volatile Configuration Register Write Enhance Volatile Configuration Register 11 Micron® N25Q256A 9Eh/9Fh 03h 0Bh 3Bh BBh 6Bh EBh 5Ah 06h 04h 02h A2h 32h 12h 20h D8h C7h 05h 01h E8h E5h 70h 50h B5h B1h 85h 81h 65h 61h Macronix MX25U25635F 9Fh 90h 03h 0Bh 3Bh BBh 6Bh EBh 5Ah 06h 04h 02h 38h 20h 52h D8h 60 or C7h 05h 15h 01h 2Bh 2Fh - REV. 1, MAR. 14, 2013 APPLICATION NOTE Table 6-1: Command Code Comparison - Continued Instruction Type QPI OTP Others Instruction Description EQIO Enable QPI RSTQIO Reset (Exit) QPI Macronix Micron® N25Q256A MX25U25635F - F5h - 35h QPIID QPI ID Read AFh AFh ENSO Enter Secured OTP - B1h EXSO Exit Secured OTP - C1h ROTP Read OTP Area 4Bh - POTP PGM/ERS Suspend PGM/ERS Resume RSTEN Program OTP Area 42h - Program or Erase Suspend 75h B0h Program or Erase Resume 7Ah 30h Reset Enable 66h 66h Reset Memory 99h 99h - C0h RST (1) SBL Set Burst Length NOP No Operation - 00h DP Deep Power Down B9h B9h RDP Release From Deep Power Down ABh ABh - Release Read Enhanced - FFh Note 1: Micron® uses the Volatile Configuration Register to control the Set Burst Length function. 7. Manufacturer and Device ID Comparison Table 7-1: Manufacturer and Device ID Comparison Name Manufacture ID Device ID Unique ID P/N: AN0210 Micron® N25Q256A Macronix MX25U25635F 20h C2h Memory Type BBh 25h Memory Capacity 19h 39h 17 Bytes N/A 12 REV. 1, MAR. 14, 2013 APPLICATION NOTE 8. Summary The Macronix MX25U25635F and Micron® N25Q256A have similar commands, functions, and features. The devices are command compatible for basic read, program, and erase operations. The devices are essentially pin compatible if the HOLD# function is not used. A more detailed analysis should be done if “special” functions such as XIP, Individual Sector Write Protection, or Dual I/O (2-2-2) are used. If common features are used in standard traditional modes, the replacement may need only minimal modification. 9. References Table 9-1 shows the datasheet versions used for comparison in this application note. For the most current, detailed Macronix specification, please refer to the Macronix Website at http://www.macronix.com/. Table 9-1: Datasheet Version Datasheet Location Date Issued Version MX25U25635F Macronix Website MAR. 2013 1.1 Micron® N25Q256A Micron® Website JUL. 2012 I 10.Revision History Revision No. REV. 1 P/N: AN0210 Description Initial Release 13 Page Date ALL MAR. 14, 2013 REV. 1, MAR. 14, 2013 APPLICATION NOTE Except for customized products which have been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright© Macronix International Co., Ltd. 2013. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. P/N: AN0210 14 REV. 1, MAR. 14, 2013