a FEATURES 140 MSPS Guaranteed Conversion Rate 100 MSPS Low Cost Version Available 330 MHz Analog Bandwidth 1 V p-p Analog Input Range Internal +2.5 V Reference Differential or Single-Ended Clock Input 3.3 V/5.0 V Three-State CMOS Outputs Single or Demultiplexed Output Ports Data Clock Output Provided Low Power: 1.0 W Typical +5 V Converter Power Supply APPLICATIONS RGB Graphics Processing High Resolution Video LCD Monitors and Projectors Micromirror Projectors Plasma Display Panels Scan Converters GENERAL DESCRIPTION The AD9483 is a triple 8-bit monolithic analog-to-digital converter optimized for digitizing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full-power analog bandwidth of 330 MHz supports display resolutions of up to 1280 × 1024 at 75 Hz with sufficient input bandwidth to accurately acquire and digitize each pixel. To minimize system cost and power dissipation, the AD9483 includes an internal +2.5 V reference and track-and-hold circuit. The user provides only a +5 V power supply and an encode clock. No external reference or driver components are required for many applications. The digital outputs are threestate CMOS outputs. Separate output power supply pins support interfacing with 3.3 V or 5 V logic. Triple 8-Bit, 140 MSPS A/D Converter AD9483 FUNCTIONAL BLOCK DIAGRAM AD9483 R AIN T/H R AIN QUANTIZER 8 DRA7-0 DRB7-0 G AIN T/H G AIN QUANTIZER 8 DGA7-0 DGB7-0 B AIN T/H B AIN QUANTIZER 8 DBA7-0 DBB7-0 ENCODE ENCODE DS CLKOUT TIMING CLKOUT DS CONTROL +2.5V OMS I/P PD VREF RVREF GVREF BVREF VCC VDD GND OUT IN IN IN mode interleaves ADC data through two 8-bit channels at onehalf the clock rate. Operation in Dual Channel mode reduces the speed and cost of external digital interfaces while allowing the ADCs to be clocked to the full 140 MSPS conversion rate. In the Single Channel mode, all data is piped at the full clock rate to the Channel A outputs and the ADCs conversion rate is limited to 100 MSPS. A data clock output is provided at the Channel A output data rate for both Dual-Channel or SingleChannel output modes. Fabricated in an advanced BiCMOS process, the AD9483 is provided in a space-saving 100-lead MQFP surface mount plastic package (S-100) and is specified over the 0°C to +85°C temperature range. The AD9483’s encode input interfaces directly to TTL, CMOS, or positive-ECL logic and will operate with single-ended or differential inputs. The user may select dual channel or single channel digital outputs. The Dual Channel (demultiplexed) REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 (VCC = +5 V, VDD = +3.3 V, external reference, ENCODE = maximum conversion rate AD9483–SPECIFICATIONS differential PECL) Parameter Temperature Test Level Min RESOLUTION DC ACCURACY Differential Nonlinearity AD9483KS-140 Typ Max 8 Bits 0.8 0.8 LSB LSB LSB LSB I VI I VI VI I V Full Full +25°C Full +25°C Full +25°C +25°C Full +25°C V V I VI I VI V I VI V 35 25 REFERENCE OUTPUT Output Voltage Temperature Coefficient Full Full VI V +2.4 +2.5 110 SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth Low (tEL) Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) Data Sync Setup Time (tSDS) Data Sync Hold Time (tHDS) Data Sync Pulsewidth (tPWDS) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 Clock Valid Time (tCV)3 Clock Propagation Delay (tCPD)3 Data to Clock Skew (tV–tCV) Data to Clock Skew (tPD–tCPD) Full Full +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C Full Full Full Full Full Full VI IV IV IV V V V IV IV IV VI VI VI VI VI VI 140 DIGITAL INPUTS Input Capacitance +25°C V DIFFERENTIAL INPUTS Differential Signal Amplitude (VID) HIGH Input Voltage (VIHD) LOW Input Voltage (VILD) Common-Mode Input (VICM) HIGH Level Current (IIH) LOW Level Current (IIL) Full Full Full Full Full Full IV IV IV IV VI VI VREF IN Input Resistance +25°C V No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (With Respect to AIN) Compliance Range AIN or AIN Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Analog Bandwidth, Full Power 1.25/–1.0 1.50/–1.0 0.9 1.50/–1.50 1.75/–1.75 Guaranteed ±1 ±2 160 1.25/–1.0 1.50/–1.0 0.9 1.50/–1.50 1.75/–1.75 Guaranteed ±1 ±2 160 ± 512 1.8 ±4 ± 512 3.2 ± 16 ± 20 83 4 17 1.8 35 25 +2.6 +2.4 83 +2.5 110 +2.6 6.3 8.0 6.2 8.0 0 0 400 0.4 0 1.5 10 50 50 4.0 4.0 1.5 100 2.3 0 0.5 2.0 4.0 10 3.8 10 1.0 2.0 –1.0 –2.0 3 6.3 8.0 6.2 8.0 0 0 VCC 2.5 10 10 1.0 2.0 3 400 0.4 0 1.5 1.2 1.2 2.5 % FS ppm/°C mV p–p V mV mV kΩ kΩ pF µA µA MHz V ppm/°C MSPS MSPS ns ns ns ps ps rms ns ns ns ns ns ns ns ns ns pF VCC 1.2 1.2 –2– 36 50 100 1.5 100 2.3 –1.0 –2.0 3.2 ± 16 ± 20 330 10 50 50 2.8 2.8 3.8 ±4 4 17 36 50 330 0 0.5 2.0 4.0 Units 8 +25°C Full +25°C Full Full +25°C Full Integral Nonlinearity AD9483KS-100 Min Typ Max mV V V V mA mA kΩ REV. A AD9483 Parameter Temperature Test Level SINGLE-ENDED INPUTS HIGH Input Voltage (VIH) LOW Input Voltage (VIL) HIGH Level Current (IIH) LOW Level Current (IIL) Full Full Full Full IV IV VI VI 2.0 0 Full Full VI VI VDD – 0.05 DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage Output Coding POWER SUPPLY VCC Supply Current VDD Supply Current Total Power Dissipation4 Power-Down Supply Current Power-Down Dissipation DYNAMIC PERFORMANCE5 Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz Effective Number of Bits fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz 2nd Harmonic Distortion fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz 3rd Harmonic Distortion fIN = 19.7 MHz fIN = 49.7 MHz fIN = 69.7 MHz Crosstalk Min AD9483KS-140 Typ Max VCC 0.8 1 1 AD9483KS-100 Min Typ Max 2.0 0 Binary Full Full Full +25°C +25°C VI VI VI V V 1.0 4 20 +25°C +25°C V V 1.5 1.5 +25°C +25°C +25°C V I V 41 45 44 44 +25°C +25°C +25°C V I V 40 +25°C +25°C +25°C V I V +25°C +25°C +25°C V I V +25°C +25°C +25°C Full V I V V VCC 0.8 1 1 V V mA mA 0.05 V V 215 60 1.3 20 100 mA mA W mA mW VDD – 0.05 0.05 Units Binary 215 60 1.3 20 100 1.0 4 20 1.5 1.5 ns ns 41 45 44 44 dB dB dB 44 43 42 40 44 43 42 dB dB dB 6.4 7.0 6.8 6.8 6.4 7.0 6.8 6.8 Bits Bits Bits 50 63 58 51 50 63 58 51 dBc dBc dBc 56 54 51 55 dBc dBc dBc dB 46 56 54 51 55 46 NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference). 2 tV and t PDF are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 5 pF. 3 tCV and tCPD are measured from the threshold crossing of the ENCODE input to valid TTL levels at the digital outputs. The output ac load during test is 20 pF. 4 Measured under the following conditions: analog input is –1 dBFS at 19.7 MHz. 5 SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range. Typical thermal impedance for the S-100 (MQFP) 100-lead package: θJC = 10°C/W, θCA = 17°C/W, θJA = 27°C/W. Specifications subject to change without notice. REV. A –3– AD9483 Table I. Output Coding ABSOLUTE MAXIMUM RATINGS* VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to 0.0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . . . . 0°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . +175°C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . +150°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. Step AIN–AIN Code Binary 255 254 253 • • • 129 128 127 126 • • • 2 1 0 ≥0.512 V 0.508 V 0.504 V • • • 0.006 V 0.002 V –0.002 V –0.006 V • • • –0.504 V –0.508 V ≤–0.512 V 255 254 253 • • • 129 128 127 126 • • • 2 1 0 1111 1111 1111 1110 1111 1101 • • • 1000 0001 1000 0000 0111 1111 0111 1110 • • • 0000 0010 0000 0001 0000 0000 II – 100% production tested at +25°C and sample tested at specified temperatures. III – Periodically sample tested. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – 100% production tested at +25°C; guaranteed by design and characterization testing. ORDERING GUIDE Model Temperature Range Package Description Package Option AD9483KS-100 AD9483KS-140 AD9483/PCB 0°C to +85°C 0°C to +85°C +25°C Plastic Thin Quad Flatpack Plastic Thin Quad Flatpack Evaluation Board S-100B S-100B CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9483 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. A AD9483 PIN FUNCTION DESCRIPTIONS Pin Number Name Function 1, 6, 7, 10, 20, 30, 40, 50, 60, 70, 73, 77, 78, 80, 81, 95, 96, 100 2 3 4 5 8 9 11, 21, 31, 41, 51, 61, 71 79, 82, 83, 93, 94, 98, 99 12–19 22–29 32–39 42–49 52–59 62–69 72 74 GND ENCODE ENCODE DS DS DCO DCO VDD VCC DBB7–DBB0 DBA7–DBA0 DGB7–DGB0 DGA7–DGA0 DRB7–DRB0 DRA7–DRA0 NC OMS 75 76 84 85 86 87 88 89 90 91 92 97 I/P PD R AIN R AIN R REF IN G AIN G AIN G REF IN B AIN B AIN B REF IN REF OUT Ground Encode clock for ADC (ADC samples on rising edge of ENCODE). Encode clock complement (ADC samples on falling edge of ENCODE). Data Sync Aligns output channels in Dual-Channel mode. Data Sync complement. Data Clock Output. Clock output at Channel A data rate. Data Clock Output complement. Output Power Supply. Nominally 3.3 V. Converter Power Supply. Nominally 5.0 V. Digital Outputs of Converter “B,” Channel B. DBB7 is the MSB. Digital Outputs of Converter “B,” Channel A. DBA7 is the MSB. Digital Outputs of Converter “G,” Channel B. DGB7 is the MSB. Digital Outputs of Converter “G,” Channel A. DGA7 is the MSB. Digital Outputs of Converter “R,” Channel B. DRB7 is the MSB. Digital Outputs of Converter “R,” Channel A. DRA7 is the MSB. No Connect. Selects Single Channel or Dual Channel output mode, (HIGH = single, LOW = demuxed). Selects interleaved or parallel output mode, (HIGH = interleaved, LOW = parallel). Power-Down and Three-State Select (HIGH = power-down). Analog Input Complement for Converter “R.” Analog Input True for Converter “R.” Reference Input for Converter “R” (+2.5 V Typical, ± 10%). Analog Input Complement for Converter “G.” Analog Input True for Converter “G.” Reference Input for Converter “G” (+2.5 V Typical, ± 10%). Analog Input Complement for Converter “B.” Analog Input True for Converter “B.” Reference Input for Converter “B” (+2.5 V Typical, ± 10%). Internal Reference Output (+2.5 V Typical); Bypass with 0.01 µF to Ground. REV. A –5– AD9483 81 GND 82 VCC 83 VCC 84 R AIN 86 R REF IN 85 R AIN 87 G AIN 88 G AIN 89 G REF IN 91 B AIN 90 B AIN 92 B REF IN 93 VCC 94 VCC 96 GND 95 GND 97 REF OUT 99 VCC 98 VCC 100 GND PIN CONFIGURATION Plastic Thin Quad Flatpack (S-100B) GND 1 ENCODE 2 ENCODE 3 DS 4 77 GND DS 5 76 PD GND 6 75 I/P GND 7 74 OMS DCO 8 73 GND DCO 9 72 NC 80 GND PIN 1 IDENTIFIER 79 VCC 78 GND GND 10 VDD 11 71 VDD 70 GND D BB7 12 69 DRA 0 D BB6 13 68 DRA 1 D BB5 14 67 DRA 2 AD9483 D BB4 15 66 DRA 3 TOP VIEW (PINS DOWN) D BB3 16 D BB2 17 65 DRA 4 64 DRA 5 D BB1 18 63 DRA 6 D BB0 19 62 DRA 7 GND 20 61 VDD 60 GND VDD 21 D BA 7 22 59 DRB 0 D BA 6 23 58 DRB 1 D BA 5 24 57 DRB 2 D BA 4 25 56 DRB 3 D BA 3 26 55 DRB 4 D BA 2 27 54 DRB 5 D BA 1 28 53 DRB 6 D BA 0 29 52 DRB 7 51 VDD GND 50 DGA0 49 DGA2 47 DGA1 48 DGA4 45 DGA3 46 DGA6 43 DGA5 44 DGA7 42 VDD 41 GND 40 DGB0 39 DGB1 38 DGB2 37 DGB3 36 DGB5 34 DGB4 35 VDD 31 DGB7 32 DGB6 33 GND 30 NC = NO CONNECT –6– REV. A AD9483 TIMING SAMPLE N SAMPLE N–1 SAMPLE N+4 SAMPLE N+3 AIN SAMPLE N+1 tA t EH ENCODE t EL SAMPLE N+2 1/f S ENCODE t PD DATA N–5 D7–D0 DATA N–4 DATA N–3 DATA N–2 DATA N–1 tV DATA N t CPD t CV CLOCK OUT CLOCK OUT Figure 1. Timing—Single Channel Mode SAMPLE N–1 SAMPLE N+3 SAMPLE N SAMPLE N+5 SAMPLE N+4 AIN t EH SAMPLE N+1 tA SAMPLE N–2 t EL SAMPLE N+6 SAMPLE N+2 1/f S ENCODE ENCODE t HDS t SDS DS DS t PD tV INTERLEAVED DATA OUT PORT A D7–D0 DATA N–7 OR N–8 PORT B D7–D0 DATA N–8 OR N–7 DATA N–7 OR N–6 DATA N–6 OR N–7 INVALID IF OUT OF SYNC DATA N–4 IF IN SYNC INVALID IF OUT OF SYNC DATA N–5 IF IN SYNC DATA N DATA N–2 DATA N–3 DATA N–1 DATA N+1 PARALLEL DATA OUT PORT A D7–D0 DATA N–9 OR N–8 DATA N–7 OR N–8 DATA N–7 OR N–6 INVALID IF OUT OF SYNC DATA N–4 IF IN SYNC DATA N–2 DATA N PORT B D7–D0 DATA N–8 OR N–7 DATA N–6 OR N–7 INVALID IF OUT OF SYNC DATA N–5 IF IN SYNC DATA N–3 DATA N–1 DATA N+1 t CPD t CV CLKOUT CLKOUT Figure 2. Timing—Dual Channel Mode REV. A –7– AD9483 EQUIVALENT CIRCUITS VDD VCC AD9483 AIN AIN DIGITAL OUTPUTS AD9483 Figure 3. Equivalent Analog Input Circuit Figure 7. Equivalent Digital Output Circuit VCC VCC VREF IN VREF OUT 500V AD9483 2kV AD9483 Figure 4. Equivalent Reference Input Circuit Figure 8. Equivalent Reference Output Circuit VCC VCC AD9483 17.5kV ENCODE DS 300V AD9483 300V ENCODE DS DIGITAL INPUTS 7.5kV Figure 5. Equivalent Encode and Data Select Input Circuit Figure 9. Equivalent Digital Input Circuit VCC AD9483 DEMUX Figure 6. Equivalent DEMUX Input Circuit –8– REV. A Typical Performance Characteristics–AD9483 2.5 0 –0.5 2.48 –1 –1.5 –3dB (333MHz) NYQUIST FREQUENCY (70MHz) 2.46 VOLTS dB –2 –2.5 –3 2.44 –3.5 2.42 –4 –4.5 –5 0 50 150 100 200 250 300 350 400 2.4 –40 450 –20 0 fIN – MHz Figure 10. Frequency Response: fS = 140 MSPS 20 40 60 TEMPERATURE – 8C 80 100 Figure 13. Reference Voltage vs. Temperature 2.6 –70 –60 2.5 –50 2.4 dB VREF –40 2.3 –30 2.2 –20 2.1 –10 2 0 0 2.5 5 7.5 10 25 50 fIN – MHz 75 100 150 200 250 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 6.2 6.4 VCC – V Figure 11. Crosstalk vs. fIN: fS = 140 MSPS Figure 14. Reference Voltage vs. Power Supply Voltage –80 2.6 2.5 –75 2.4 2.3 –70 VOLTS dB 2.2 –65 2.1 2 –60 1.9 1.8 –55 1.7 –50 0 1.6 10 20 30 40 50 60 70 TEMPERATURE – 8C 80 90 100 0 Figure 12. Crosstalk vs. Temperature: fIN = 70 MHz REV. A 1 2 3 4 5 6 7 8 9 IREF – mA 10 11 12 13 14 15 Figure 15. Reference Voltage vs. Reference Load –9– AD9483–Typical Performance Characteristics 5 9 8.5 8 4 7.5 3.5 TPD 5V 7 VDD = +5V 3 TV 5V VOLTS ns 4.5 TPD 3.3V 6.5 VDD = +3.3V 2.5 2 6 TV 3.3V 5.5 1.5 5 1 4.5 0.5 0 4 5 10 15 20 LOAD CAPACITANCE – pF 25 0 30 Figure 16. Clock Output Delay vs. Capacitance 4 6 8 12 10 IOH – mA 14 16 18 20 Figure 19. Output Voltage HIGH vs. Output Current 9 2 8 1.8 7 2 1.6 TPD 1.4 6 1.2 ns VOLTS TV 5 4 1 0.8 3 0.6 2 0.4 VDD = +3.3V 1 0 3 0 3.3 3.6 3.9 4.2 4.5 VDD – V 4.75 5 5.25 0 5.5 Figure 17. Output Delay vs. VDD 15 20 600 500 7.5 400 TV 5V TPD 5V mW ns 10 IOL TPD 3.3V 8 7 5 Figure 20. Output Voltage LOW vs. Output Current 9 8.5 VDD = +5V 0.2 6.5 300 6 TV 3.3V 200 5.5 5 100 4.5 4 –40 0 0 50 TEMPERATURE – 8C 3 100 3.5 4 4.5 5 5.5 VDD – V Figure 18. Output Delay vs Temperature Figure 21. Output Power vs. VDD, CLOAD = 10 pF –10– REV. A AD9483 50 50 48 48 46 46 SNR 44 44 SINAD SNR 42 dB dB 42 40 40 38 38 36 36 34 34 32 32 30 SINAD 30 0 30 60 100 fS – MSPS 140 180 0 Figure 22. SNR vs. fS: fIN = 19.7 MHz 20 40 60 80 100 120 fS – MSPS 140 160 180 200 Figure 25. SNR vs fS: fIN = 71.7 MHz –56 –75 –54 –70 2ND HARMONIC –52 3RD HARMONIC –50 –65 dB dB –48 –60 3RD HARMONIC –46 –44 –42 2ND HARMONIC –40 –55 –38 –50 –36 0 25 50 90 fS – MSPS 130 170 Figure 23. Harmonic Distortion vs. fS: fIN = 19.7 MHz 120 fS – MSPS 155 175 0 FUNDAMENTAL = –0.5dBFS SNR = 45.8dB SINAD = 45.2dB 2ND HARMONIC = 69.8dB 3RD HARMONIC = 61.6dB –10 –20 FUNDAMENTAL = –0.5dBFS SNR = 44.6dB SINAD = 37.6dB 2ND HARMONIC = 63.1dB 3RD HARMONIC = 39.1dB –10 –20 –30 –30 –40 –40 dB dB 80 Figure 26. Harmonic Distortion vs fS: fIN = 71.7 MHz 0 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 0 10 20 30 40 50 MHz 60 70 80 90 100 0 Figure 24. Spectrum: fS = 140 MSPS, fIN = 19.57 MHz REV. A 40 0 10 20 30 40 50 MHz 60 70 80 90 100 Figure 27. Spectrum: fS = 140 MSPS, fIN = 70.3 MHz –11– AD9483 46 44 46 SNR fS = 140 MSPS fIN = 19.3MHz SNR 45 SINAD 42 SINAD 44 dB dB 40 38 43 36 42 34 41 32 30 25% 28% 2 1.8 31% 2.2 40 –25 38% 45% 52% 59% 66% 73% 76% 2.7 3.2 3.7 4.2 4.7 5.2 5.4 ENCODE DUTY CYCLE – % ENCODE PULSEWIDTH – ns Figure 28. SNR vs. Clock Pulsewidth (tPWH): fS = 140 MSPS 0 40 60 TEMPERATURE – 8C 80 100 Figure 31. SNR vs. Temperature, fS = 140 MSPS 55 –70 –65 50 NYQUIST FREQUENCY (70.0MHz) –60 dB dB 45 –55 SNR 40 –50 35 30 SINAD 0 50 100 150 fIN – MHz 200 –45 –40 –25 250 Figure 29. SNR vs. fIN: fS = 140 MSPS 0 40 60 TEMPERATURE – 8C 80 100 Figure 32. 2nd Harmonic vs. Temperature, fS = 140 MSPS –60 0 F1 = 55.0MHz F2 = 56.0MHz F1 = F2 = –7.0dBFS –10 –20 –56 –30 –52 dB dB –40 –48 –50 –60 –70 –80 –44 –90 –40 –25 –100 0 40 60 TEMPERATURE – 8C 80 100 Figure 30. 3rd Harmonic vs. Temperature, fS = 140 MSPS –12– 0 10 20 30 40 50 MHz 60 70 80 90 100 Figure 33. Two Tone Intermodulation Distortion REV. A AD9483 APPLICATION NOTES Theory of Operation The AD9483 combines Analog Devices’ patented MagAmp bitper-stage architecture with flash converter technology to create a high performance, low power ADC. For ease of use the part includes an on board reference and input logic that accepts TTL, CMOS or PECL levels. Each of the three analog input signals is buffered by a high speed differential amplifier and applied to a track-and-hold (T/H) circuit. This T/H captures the value of the input at the sampling instant and maintains it for the duration of the conversion. The sampling and conversion process is initiated by a rising edge on the ENCODE input. Once the signal is captured by the T/H, the four Most Significant Bits (MSBs) are sequentially encoded by the MagAmp string. The residue signal is then encoded by a flash comparator string to generate the four Least Significant Bits (LSBs). The comparator outputs are decoded and combined into the 8-bit result. If the user has selected Single Channel mode (OMS = HIGH) the 8-bit data word is directed to an A output bank. Data are strobed to the output on the rising edge of the ENCODE input with four pipeline delays. If the user has selected Dual Channel mode (OMS = LOW) the data are alternately directed between the A and B output banks and the data has five pipeline delays. At power-up, the N sample data can appear at either the A or B Port. To align the data in a known state, the user must strobe DATA SYNC (DS, DS) per the conditions described in the Timing section. needs to be driven, which in turn minimizes on-chip noise due to heavy current flow in the outputs. We have obtained optimum performance on our evaluation board by tying all VCC pins to a quiet analog power supply system and tying all GND pins to a quiet analog system ground. Minimum Encode Rate The minimum sampling rate for the AD9483 is 10 MHz for the 140 MSPS and 100 MSPS versions. To achieve this sampling rate, the Track/Hold circuit employs a very small hold capacitor. When operated below the minimum guaranteed sampling rate, the T/H droop becomes excessive. This is first observed as an increase in offset voltage, followed by degraded linearity at even lower frequencies. Lower effective sampling rates may be easily supported by operating the converter in Dual Port output mode and using only one output channel. A majority of the power dissipated by the AD9483 is static (not related to conversion rate), so the penalty for clocking at twice the desired rate is not high. Digital Inputs SNR performance is directly related to the sampling clock stability in A/D converters, particularly for high input frequencies and wide bandwidths. Graphics Applications The high bandwidth and low power of the AD9483 makes it very attractive for applications that require the digitization of presampled waveforms, wherein the input signal rapidly slews from one level to another, then is relatively stable for a period of time. Examples of these include digitizing the output of computer graphic display systems, and very high speed solid state imagers. These applications require the converter to process inputs with frequency components well in excess of the sampling rate (often with subnanosecond rise times), after which the A/D must settle and sample the input in well under one pixel time. The architecture of the AD9483 is vastly superior to older flash architectures, which not only exhibit excessive input capacitance (which is very hard to drive), but can make major errors when fed a very rapidly slewing signal. The AD9483’s extremely wide bandwidth Track/Hold circuit processes these signals without difficulty. ENCODE and Data Select (DS) can be driven differentially or single-ended. For single-ended operation, the complement inputs (ENCODE, DS) are internally biased to VDD/3 (~1.5 V) by a high impedance on-chip resistor divider (Figure 5), but they may be externally driven to establish an alternate threshold if desired. A 0.1 µF decoupling capacitor to ground is sufficient to maintain a threshold appropriate for TTL or CMOS logic. When driven differentially, ENCODE and DS will accommodate differential signals centered between 1.5 V and 4.5 V with a total differential swing ≥800 mV (VID ≥400 mV). Note the 6-diode clock input protection circuitry in Figure 5. This limits the differential input voltage to ± 2.1 V. When the diodes turn on, current is limited by the 300 Ω series resistor. Exceeding 2.1 V across the differential inputs will have no impact on the performance of the converter, but be aware of the clock signal distortion that may be produced by the nonlinear impedance at the converter. DRIVING DIFFERENTIAL INPUTS DIFFERENTIALLY CLOCK ENC VIH D VIC M CLOCK ENC VID VIL D Using the AD9483 Good high speed design practices must be followed when using the AD9483. Decoupling capacitors should be physically as close as possible to the chip to obtain maximum benefit. We recommend placing a 0.1 µF capacitor at each power ground pin pair (14 total) for high frequency decoupling and including one 10 µF capacitor for local low frequency decoupling. Each of the three VREF IN pins should also be decoupled by a 0.1 µF capacitor. CLOCK ENC VIN D VID VIC M 0.1mF ENC VIL D Figure 34. Input Signal Level Definitions The part should be located on a solid ground plane and output trace lengths should be short (<1 inch) to minimize transmission line effects. This will avoid the need for termination resistors on the output bus and reduces the load capacitance that REV. A DRIVING DIFFERENTIAL INPUTS SINGLE-ENDEDLY –13– AD9483 ADC Gain Control Modes of Operation Each of the three ADC channels has independent limited gain control. The full-scale signal amplitude for a given ADC is set by the dc voltage on its VREF In pin. The equation relating the full scale amplitude to VREF In is as follows: FS = (0.4) × (VREF IN). The three ADCs are optimized for a full-scale signal amplitude of 1 V, but will accommodate up to ± 10% variation. The AD9483 has three modes of operation, Single Channel output mode, and a Dual Channel output mode with two possible data formats, interleaved or parallel. Two pins control which mode of operation the chip is in, Pin 74 Output Mode Select (OMS) and Pin 75 Interleaved/Parallel Select (I/P). Table II shows the configuration required for each mode. ADC Offset Control Table II. Output Mode Selection The offset for each of the three ADCs can be independently controlled. For a single-ended analog input where the analog input is connected to a reference, offset can be adjusted simply by adjusting the dc voltage of the reference. For differential analog inputs, the user must provide the offset in their signal. Offset can be adjusted up or down as far as the common-mode input range will allow. P (VDD) = 1/2 C × V 2 × F × N Output Load Capacitance VDD Supply Voltage Encode Frequency Number of Outputs Switching Nominally, C = 10 pF, V = 3.3 V, F = 140 MSPS, and N = 26. N comes from the 24 output bits plus two clock outputs, P(VDD) = 197 mW. Power-Down The power-down function allows users to reduce power dissipation when output data is not required. A TTL/CMOS HIGH signal on pin 76, (PD), shuts down most of the chip and brings the total power dissipation to less than 100 mW. The internal bandgap voltage reference remains active during power-down mode to minimize reactivation time. If the power-down function is not desired, the PD pin should be tied to ground or held to a TTL/CMOS LOW level. Bandgap Voltage Reference The AD9483 internal reference, VREF OUT (Pin 97), provides a simple, cost effective reference for many applications. It exhibits reasonable accuracy and excellent stability over power supply and temperature variations. The reference output can be used to set the three ADCs’ gain and offset. The reference is capable of providing up to 1 mA of additional current beyond the requirements of the AD9483. As the ADC gain and offset are set by the reference inputs, some applications may require a reference with greater accuracy or temperature performance. In these cases, an external reference may be connected directly to the VREF IN pins. VREF OUT, if unused, should be left floating. Note, each of the three VREF IN pins will require up to 1 mA of current. I/P Dual Channel—Parallel Dual Channel—Interleaved Single Channel LOW LOW HIGH LOW HIGH DON’T CARE In demuxed mode, (Pin 74 OMS = LOW), the ADC output data are alternated between the two output ports (Port A and Port B). This limits the data output rate to 1/2 the rate of ENCODE, and facilitates conversion rates up to 140 MSPS. Demuxed output mode is recommended for guaranteed operation above 100 MSPS, but may be enabled at any specified conversion rate. Power dissipation for the AD9483 has two components, VCC and VDD. Power dissipation from VCC is relatively constant for a given supply voltage, whereas power dissipation from VDD can vary greatly. VCC supplies power to the analog circuity. VDD supplies power to the digital outputs and can be approximated by the following equation: = = = = OMS Demuxed Output Mode Power Dissipation C V F N MODE Two data formats are possible in Dual Channel output mode, parallel data out and interleaved data out. Pin 75 I/P should be LOW for parallel format and HIGH for interleaved format. Figures 1 and 2 show the timing requirements for each format. Note that the Data Sync input, (DS), is required in Dual Channel output mode for both formats. The section on Data Sync describes the requirements of the Data Sync input. As shown in Figures 1 and 2, when using the interleaved data format, a sample is taken on an ENCODE rising edge N. The resulting data is produced on an output port following the fifth rising edge of ENCODE after the sample was taken, (five pipeline delays). The following sample, (N+1), will be produced on the opposite port, also five pipeline delays after it was taken. The state of CLKOUT when the sample was taken will determine out of which port the data will come. If CLKOUT was LOW, the data will come out Port A. If CLKOUT was HIGH, the data will come out Port B. In order to achieve parallel data format on the two output data ports, the data is internally aligned. This is accomplished by adding an extra pipeline delay to just the A Data Port. Thus, data coming out Port A will have six pipeline delays and data coming out Port B will have five pipeline delays. As with the interleaved format, the state of Data Sync when a sample is taken will determine out of which port the data will come. If CLKOUT was LOW, the data will come out Port A. If CLKOUT was HIGH, the data will come out Port B. –14– REV. A AD9483 Data Sync The Data Sync input, DS, is required to be driven for most applications to guarantee at which output port a given sample will appear. When DS is held high, the ADC data outputs and clock outputs do not switch—they are held static. Synchronization is accomplished by the assertion (falling edge) of DS, within the timing constraints TSDS and THDS relative to an encode rising edge. (On initial synchronization THDS is not relevant.) If DS falls TSDS before a given encode rising edge N, the analog value at that point in time will be digitized and available at Port A five cycles later (interleaved mode). The very next sample, N+l, will be sampled by the next rising encode edge and available at Port B five cycles after that encode edge (interleaved mode). In dual parallel mode the A port has a six cycle latency, the B port has a five cycle latency as described in Demuxed Outputs Mode section. DS can be asserted once per video line if desired by using the horizontal sync signal (HSYNC). The start of HSYNC should occur after the end of active video by at least the chip latency. The HSYNC front porch is usually much greater than this in a typical SXGA system. If this is true in a given system then DS can be reset high by the HSYNC leading edge (the samples at that point should not be required in a typical system). DS can then be reasserted (brought low), by triggering from HSYNC trailing edge—observing TSDS of the next rising encode edge. The first pixel data (on A Port) would be available five cycles after the first rising encode after HSYNC goes high. Single Channel Outputs Mode In Single Channel mode, (Pin 74 OMS = HIGH), the timing of the AD9483 is similar to any high speed ADC (Figure 1). A sample is taken on every rising edge of ENCODE, and the resulting data is produced on the output pins following the fourth rising edge of ENCODE after the sample was taken, (four pipeline delays). The output data are valid tPD after the rising edge of ENCODE, and remain valid until at least tV after the next rising edge of ENCODE. REV. A When operating in single channel mode, all data comes out the A Ports while the B Ports are held static in a random state. Data Clock Outputs The data clock outputs will switch at two potential frequencies. In Single Channel mode, where all data comes out of Port A at the full ENCODE rate, the data clock outputs switch at the same frequency as the ENCODE. In Dual Channel mode, where the data alternates between the two ports, each of which operate at 1/2 the full ENCODE rate, the data clock outputs also switch at 1/2 the full ENCODE rate. The data clock outputs have two potential purposes. The first is to act as a latch signal for capturing output data. In order to do this, simply drive the data latches with the appropriate data clock output. The second use is in Dual Channel data mode to help determine out of which data port data will come out. Refer to Figure 2 for a complete timing diagram, but in this mode, a rising edge on data clock will correspond to data switching on data Port B. It is possible to use the phase of the data clock outputs and software programming to accommodate situations where DS is not driven. The data clock outputs (CLKOUT and CLKOUT) can be used to determine when data is valid on the output ports. In these cases DS should be grounded and DS left floating or connected to VCC. If CLKOUT was low when a given sample was taken, the digitized value will be available on Port A, five cycles later. Data Sync has no effect when Single Channel Mode is selected, it should be grounded Figure 2 shows how to use DS properly. The DS rising edge does not have any special timing requirements except that no data will come out of either port while it is held HIGH. The falling edge of DS must, however, meet a minimum setup-andhold time with respect to the rising edge of ENCODE. The maximum conversion rate in the mode should be limited to 100 MSPS. This is recommended because the guaranteed output data valid time minus the propagation delay is only 4 ns at 100 MSPS. This is about as fast as standard logic is able to capture the data with reasonable design margins. The AD9483 will operate faster in this mode if the user is able to capture the data. LAYOUT AND BYPASSING CONSIDERATIONS Proper high speed layout and bypassing techniques should be used with the AD9483. Each VCC and VDD power pin should be bypassed as close to the pin as possible with a 0.01 µF to 0.1 µF capacitor Also, one 10 µF capacitor to ground should be used per supply per board. The VREF OUT pin and each of the three VREF IN pins should also be bypassed with a 0.01 µF to 0.1 µF capacitor to ground. A single, substantial, low impedance ground plane should be place under and around the AD9483. Try to maximize the distance between the sensitive analog signals, (AIN, VREF), and the digital signals. Capacitive loading on the digital outputs should be kept to a minimum. This can be facilitated by keeping the traces short and in the case of the clock outputs by driving as few other devices as possible. Socketing the AD9483 should also be avoided. Try to match trace lengths of similar signals to avoid mismatches in propagation delays, (the encode inputs, analog inputs, digital outputs). POWER SUPPLIES At power up, VCC must come up before VDD. VCC is considered the converter supply, nominally 5.0 V (± 5.0%) VDD is consider output power supply, nominally 3.3 V (± 10%) or 5.0 V (± 5%). At power off, VDD must turn off first. Failure to observe the correct power supply sequencing many damage this device. –15– AD9483 EVALUATION BOARD Voltage Reference The AD9483 evaluation board offers an easy way to test the AD9483. It provides ac or dc biasing for the analog input, it generates the output latch clocks for Single Mode, Dual Parallel Mode and Dual Interleaved Mode. Each of the three channels has a reconstruction DAC (A Port only). The board has several different modes of operation, and is shipped in the following configuration: The AD9483 has an internal 2.5 V voltage reference (VREF OUT). This is buffered externally on board to support additional level shifting circuitry (the AD9483 VREF OUT pin can drive the three VREF IN pins in applications where level shifting is not required with no additional buffering). An external reference may be employed instead to drive each VREF IN pin independently (requires moving Jumpers W14, W15 and W16). • Single-ended ac coupled analog input (1 V p-p centered at ground) Single Channel Mode Single Channel mode sets the AD9483 to produce data on every clock cycle on output port A only. The maximum speed in Single Channel mode is 100 MSPS. • Differential clock inputs (PECL) (See ENCODE section for TTL drive) Dual Channel Modes (Outputs Clocked at 1/2 Encode Clock) Dual Channel Interleaved • Internal voltage references connected to externally buffered on-chip reference (VREF OUT) • Preset for Dual Mode Interleaved Sets the ADC to produce data alternately on Port A and Port B. the maximum speed in this mode is 140 MSPS. Analog Input Dual Channel Parallel The evaluation board accepts a 1 V p-p input signal centered at ground for ac coupled input mode (Set Jumpers W4, W5, W12, W13, W18, W17 to jump Pin 1 to Pin 2). This signal biased up to 2.5 V by the on-chip reference. Note: input signal should be bandlimited (filtered) prior to sampling to avoid aliasing. The analog inputs are terminated to ground by a 75 Ω resistor on the board. The analog inputs are ac coupled through 0.1 µF caps C2, C4, C6 on top of the board. These can be increased to accommodate lower frequency inputs if desired using test points PR1–PR6 on bottom of board. In dc coupled input mode (Set Jumpers W4, W5, W12, W13, W18, W17 to jump Pin 3 to Pin 2 ) the board accepts typical video level signal levels (0 mV to 700 mV) the signal is level shifted and amplified to 1 V p-p by the AD8055 preamp. Trimpots R98–R100 are used to adjust dc black level to 2 V at ADC inputs. Sets the ADC to produce data concurrently on Port A and Port B. Maximum speed in this mode is 140 MSPS. DAC Out The DAC output is a representation of the data on output Port A only. The DAC is terminated on the board into 75 Ω. Fullscale voltage swing at DAC output is nominally 0 mV to 800 mV when terminated into external 75 Ω (doubly terminated). Output Port B is not reconstructed. The DAC outputs are NOT filtered and will exhibit sampling noise. The DACs can be powered down at W1, W2, and W3 (jumper not installed). Data Ready Encode An output clock for latching the ADC outputs is available at Pin 1 at the 25-pin connector. Its complement is located at Pin 14. The clocks are terminated on the board by a 75 Ω Thevenin termination to VD/2. The timing on these clock outputs can be inverted at W9, W10 (jumper not installed). The AD9483 ENCODE input can be driven two ways. Schematics 1. Differential PECL (VLO = 3, VHI = 4 nominal). It is shipped in this mode. The schematics for the evaluation board follow. (Note bypass capacitors for ADC are shown in Figure 39.) 2. Single ended TTL or CMOS. (At Encode Bar–Remove 50 Ω termination resistor R10, add 0.1 µF capacitor C7) Table III. Evaluation Board Jumper Settings MODE W7 (OMS) W6 (I/P) W11 (A_LAT) W11 (B_LAT) Dual Channel/PARALLEL LOW LOW DATA_CLK_OUT (4–5) DATA_CLK_OUT (2–3) Dual Channel/INTERLEAVED LOW HIGH DATA_CLK_OUT (5–6) DATA_CLK_OUT (2–3) SINGLE HIGH DON’T CARE DATA_CLK_OUT (5–6) NC DESIGN NOTES Maximum frequency for PARALLEL is 140 MHz. Maximum frequency for INTERLEAVED is 140 MHz. Maximum frequency for SINGLE is 100 MHz. DS is tied to ground through a 50 Ω resistor. DS is left floating. –16– REV. A 62 OUTA A6 63 OUTA A5 64 OUTA A4 65 OUTA A3 66 OUTA A2 67 OUTA A1 68 OUTA A0 69 1 W7 27 OUTC A2 OUTC A2 OUTA B3 OUTC A4 OUTA B2 OUTC A5 OUTA B1 OUTC A6 OUTA B0 OUTC_A7 OUTA A7 OUTC B0 OUTA A6 OUTC B1 OUTA A5 OUTC B2 OUTA A4 OUTC B3 OUTA A3 OUTC B4 26 OUTC A3 25 OUTC A4 24 OUTC A5 23 OUTC A6 22 OUTC A7 19 OUTC B0 18 OUTC B1 17 OUTC B2 16 OUTC B3 15 OUTC B4 14 OUTC B5 OUTC B5 OUTA A1 OUTC B6 OUTA A0 OUTC B7 13 OUTC B6 12 OUTC B7 9 DATA CLK OUT R102 2 100V 75 89 91 86 C REF A REF C3 0.1mF W5 1 7 PR2 PR1 3 C4 0.1mF PR3 3 1 7 VA 2 4 3 2 –VA REF OUT R90 360V C6 0.1mF PR6 3 1 R1 75V 2 4 U16 AD8055 3 2 TRIM C R91 274V 3 1 W18 R2 75V 2 R3 75V TP3 J6 J7 BNC J5 BNC Figure 35. ADC and Preamp Section REV. A 7 VA PR5 TRIM B R88 274V TP1 BNC R105 200V W12 W4 TP2 3 6 U15 AD8055 PR4 TRIM A R87 274V 1 –17– J2 ENC 2 R6 1kV R104 200V R89 360V SMB W17 3 R5 1kV –VA J1 ENC C5 0.1mF R10 50V NOT INSTALLED SMB 6 4 2 97 W13 1 U14 AD8055 C7 0.1mF R9 50V C REF 6 VA 2 C REF REF OUT 2 3 R103 200V C2 0.1mF 92 B REF B REF 2 R4 1kV R86 360V C REF IN B REF IN AIN C B REF A REF C1 0.1mF 90 88 A REF DS 3 ENCODE 87 AIN C AIN A 85 84 A REF IN ENCODE AIN B PWR DN AIN A 76 ENCODE AIN B 3 DS 4 DS I/P DATA_CLK_OUT 5 DS 1 W6 DATA CLK OUT 8 DATA CLK OUT OMS 3 OUTC_B[0-7] OUTC_A[0-7] 33 OUTB A6 34 OUTB A5 35 OUTB A4 36 OUTB A3 37 OUTB A2 OUTB B[0-7] 39 OUTB A0 38 OUTB A1 OUTB A[0-7] 42 OUTB A7 43 OUTB A6 44 OUTB A5 45 OUTB A4 46 OUTB A3 47 OUTB A2 48 OUTB A1 32 OUTB A7 28 OUTC A1 OUTC A1 OUTC A3 AD9483 29 OUTC A0 OUTC A0 OUTA B4 OUTA A2 R101 2 100V 74 OUTB_B7 OUTA A7 OUTB_B6 59 OUTB_B5 OUTA B0 OUTB_B4 58 OUTB_B3 OUTA B1 OUTB_B2 57 OUTB_B1 OUTA B2 OUTB_B0 56 OUTB A7 OUTA B3 OUTB A6 55 OUTA B5 OUTB A5 OUTA B4 OUTA B6 OUTB A4 54 OUTB A3 OUTA B5 OUTA B7 OUTB A2 49 OUTB A0 53 OUTB A1 52 OUTA B6 OUTB A0 OUTA B7 ENCODE VDD OUTA_B[0-7] OUTA_A[0-7] AD9483 –VA –18– OUTC B [0-7] OUTB B [0-7] OUTA B [0-7] B_LAT OUTC A [0-7] OUTB A [0-7] OUTA A [0-7] A_LAT 11 15 RED B4 14 RED B5 13 RED B6 12 RED B7 OUTA B4 6 OUTA B5 7 OUTA B6 8 OUTA B7 9 74LCX574 16 RED B3 OUTA B3 5 18 RED B1 19 RED B0 17 RED B2 1D C1 OUTA B2 4 OUTA B1 3 OUTA B0 2 11 GND: 10 VD: 20 12 RED A7 OUTA A7 9 EN 13 RED A6 OUTA A6 8 GND 14 RED A5 OUTA A5 7 U9 15 RED A4 OUTA A4 6 1 16 RED A3 18 RED A1 19 RED A0 OUTA A3 5 74LCX574 GND: 10 VD: 20 17 RED A2 1D C1 EN U6 OUTA A2 4 OUTA A1 3 OUTA A0 2 GND 1 11 11 OUTB B7 9 OUTB B6 8 OUTB B5 7 OUTB B4 6 OUTB B3 5 OUTB B2 4 OUTB B1 3 OUTB B0 2 GND 1 OUTB A7 9 OUTB A6 8 OUTB A5 7 OUTB A4 6 OUTB A3 5 OUTB A2 4 OUTB A1 3 OUTB A0 2 GND 1 1D C1 EN U7 1D C1 EN U10 74LCX574 GND: 10 VD: 20 74LCX574 GND: 10 VD: 20 12 GREEN B7 13 GREEN B6 14 GREEN B5 15 GREEN B4 16 GREEN B3 17 GREEN B2 18 GREEN B1 19 GREEN B0 12 GREEN A7 13 GREEN A6 14 GREEN A5 15 GREEN A4 16 GREEN A3 17 GREEN A2 18 GREEN A1 19 GREEN A0 11 11 OUTC B7 9 OUTC B6 8 OUTC B5 7 OUTC B4 6 OUTC B3 5 OUTC B2 4 OUTC B1 3 OUTC B0 2 GND 1 OUTC A7 9 OUTC A6 8 OUTC A5 7 OUTC A4 6 OUTC A3 5 OUTC A2 4 OUTC A1 3 OUTC A0 2 GND 1 1D C1 EN U11 1D C1 EN U8 74LCX574 GND: 10 VD: 20 74LCX574 GND: 10 VD: 20 12 BLUE B7 13 BLUE B6 14 BLUE B5 15 BLUE B4 16 BLUE B3 17 BLUE B2 18 BLUE B1 19 BLUE B0 12 BLUE A7 13 BLUE A6 14 BLUE A5 15 BLUE A4 16 BLUE A3 17 BLUE A2 18 BLUE A1 19 BLUE A0 R77 301V VD R76 301V R8 301V VD R7 301V AD9483 Figure 36. Output Latches Section REV. A A0 A1 A2 A3 A4 A5 A6 A7 Figure 37. DACs and Clock Buffer Section R64 150V 23 C10 0.1mF R21 2kV VD 15 16 REF GND: 20,26 AD9760 17 18 C9 0.1mF R12 1kV I OUT B DAC CLK VD R61 150V R80 150V DR VD CLOCK LINE TERMINATIONS R19 1kV 28 CLK DB4 DB5 DB6 DB7 DB8 DB9 R62 150V R83 150V VD J10 SMB DR R24 75V R14 75V 21 19 24 27 U2 2 1 A D COMP DB0 COMP DB1 DB2 22 I OUT A DB3 W1 10 9 8 7 6 5 4 3 2 1 R85 150V DAC CLK VD RED RED RED RED RED RED RED RED VD C11 0.1mF SLEEP A0 A1 A2 A3 A4 A5 A6 A7 DAC CLK VD GREEN GREEN GREEN GREEN GREEN GREEN GREEN GREEN 23 SLEEP C12 0.1mF R22 2kV VD VD : 14 GND : 7 R79 0V DR R11 1kV 28 15 16 C13 0.1mF 17 18 R23 1kV U4 19 24 27 2 1 A D COMP DB0 COMP DB1 SMB DB2 22 I OUT A DB3 J5 R18 DB4 75V AD9760 DB5 DB6 DB7 21 DB8 I OUT B GND: 20,26 R17 DB9 75V REF CLK W3 10 9 8 7 6 5 4 3 2 1 C14 0.1mF VD W10 IO B LAT LO VD : 14 GND : 7 IO DR FSADJ W9 FSADJ U1 74LCX86 4 6 5 A0 A1 A2 A3 A4 A5 A6 A7 DAC CLK VD BLUE BLUE BLUE BLUE BLUE BLUE BLUE BLUE 23 C15 0.1mF R73 2kV VD VD : 14 GND : 7 U1 74LCX86 9 8 10 R20 1kV 28 CLK DB4 DB5 DB6 DB7 DB8 DB9 15 16 REF GND: 20,26 AD9760 17 18 C16 0.1mF R13 1kV I OUT B R15 75V R16 75V J10 SMB DAC_CLK 21 U3 19 24 27 2 1 A D DB0 COMP COMP DB1 DB2 22 I OUT A DB3 W2 10 9 8 7 6 5 4 3 2 1 C17 0.1mF VD W8 A LAT SLEEP A LAT LO –19– LO R78 0V FSADJ REV. A IO U1 74LCX86 1 3 2 AD9483 –20– BLUE_B7 BLUE_B6 BLUE_B5 BLUE_B4 BLUE_B3 BLUE_B2 BLUE_B1 BLUE_B0 BLUE_A7 BLUE_A6 BLUE_A5 BLUE_A4 BLUE_A3 BLUE_A2 BLUE_A1 BLUE_A0 RED_B7 RED_B6 RED_B5 RED_B4 RED_B3 RED_B2 RED_B1 RED_B0 RED_A7 RED_A6 RED_A5 RED_A4 RED_A3 RED_A2 RED_A1 RED_A0 R57 100V R58 100V R59 100V R64 100V R63 100V R62 100V R60 100V R61 100V R40 100V R39 100V R38 100V R33 100V R34 100V R35 100V R37 100V R36 100V R72 100V R71 100V R70 100V R65 100V R66 100V R67 100V R69 100V R68 100V R32 100V R31 100V R30 100V R29 100V R28 100V R27 100V R25 100V R26 100V BL_B7 BL_B6 BL_B5 BL_B4 BL_B3 BL_B2 BL_B1 BL_B0 BL_A7 BL_A6 BL_A5 BL_A4 BL_A3 BL_A2 BL_A1 BL_A0 R_B7 R_B6 R_B5 R_B4 R_B3 R_B2 R_B1 R_B0 R_A7 R_A6 R_A5 R_A4 R_A3 R_A2 R_A1 R_A0 ST4 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 ST8 P1 P2 P3 P4 P5 1 2 3 4 5 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 R56 100V R55 100V R54 100V R49 100V R50 100V R51 100V R53 100V R52 100V R41 100V R42 100V R43 100V R48 100V R47 100V R46 100V R44 100V R45 100V 1 2 3 4 5 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 GREEN_B7 GREEN_B6 GREEN_B5 GREEN_B4 GREEN_B3 GREEN_B2 GREEN_B1 GREEN_B0 GREEN_A7 GREEN_A6 GREEN_A5 GREEN_A4 GREEN_A3 GREEN_A2 GREEN_A1 GREEN_A0 U13 ST7 P1 P2 P3 P4 P5 GND P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 GR_B7 GR_B6 GR_B5 GR_B4 GR_B3 GR_B2 GR_B1 GR_B0 GR_A7 GR_A6 GR_A5 GR_A4 GR_A3 GR_A2 GR_A1 GR_A0 20 1 19 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 10 ST1 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P1 P2 P3 P4 P5 1 2 3 4 5 R74 50V VD: 14 GND: 7 U1 74LCX86 11 R75 50V 1 2 3 4 5 U13 ST6 P1 P2 P3 P4 P5 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 VD EXTRA GATES 13 12 C8 0.1mF 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 ST5 ST4 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 CUSTOMER WORKSPACE NOT INSTALLED DS DS P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 J3 J4 20 1 19 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 10 SMB SMB ST1 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CON-DB25HF P2 GND GR_B0 GR_B1 GR_B2 GR_B3 GR_B4 GR_B5 GR_B6 GR_B7 GND DR DR GND GR_A0 GR_A1 GR_A2 GR_A3 GR_A4 GR_A5 GR_A6 GR_A7 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 CON-DB25HF P3 GND BL_B0 BL_B1 BL_B2 BL_B3 BL_B4 BL_B5 BL_B6 BL_B7 GND DR DR GND BL_A0 BL_A1 BL_A2 BL_A3 BL_A4 BL_A5 BL_A6 BL_A7 GND TEST POINT GROUNDS GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 CON-DB25HF P1 GND R_B0 R_B1 R_B2 R_B3 R_B4 R_B5 R_B6 R_B7 GND DR DR GND R_A0 R_A1 R_A2 R_A3 R_A4 R_A5 R_A6 R_A7 GND AD9483 Figure 38. Digital Outputs Connectors and Terminations Section REV. A REV. A 8 7 6 5 4 3 2 1 POWER/DC INPUTS GND –21– 7 EXT REF C EXT REF B –VA 6 VA C54 10mF C53 10mF W16 1 2 3 W15 1 2 3 W14 1 2 3 C49 0.1mF C18 10mF AD9483 EXTERNAL REFERENCES C51 10mF 4 AD9483 EXT REF A 3 2 EXT REF C EXT REF B EXT REF A C36 0.1mF C52 10mF C37 0.1mF C27 0.1mF C48 0.1mF C47 0.1mF R99 500V R94 1.5kV R95 1.3kV REF SOURCE SELECT C35 0.1mF C46 0.1mF –VA AD9483 SUPPORT LOGIC + SUPPLY –VA AD9483 DIGITAL SUPPLY VA AD9483 ANALOG SUPPLY –VA AD9483 SUPPORT LOGIC – SUPPLY REF OUT C41 0.1mF TB1 TRIM C C REF C38 0.1mF C28 0.1mF R100 500V R97 1.5kV B REF R93 1.5kV C45 0.1mF C34 0.1mF C57 0.1mF TRIM A A REF C44 0.1mF C33 0.1mF C19 0.1mF R92 1.3kV C43 0.1mF C32 0.1mF C50 0.1mF R98 500V C42 0.1mF C31 0.1mF TRIM B C40 0.1mF C30 0.1mF R96 1.3kV C39 0.1mF C29 0.1mF BYPASS CAPS C20 0.1mF C56 10mF VD C23 0.1mF VD C63 10mF C21 0.1mF C61 0.1mF C24 0.1mF C62 0.1mF C25 0.1mF 5 4 3 6 2 1 W11 C65 0.1mF C26 0.1mF B_LAT DATA_LOCK_OUT A_LAT DATA_LOCK_OUT LATCH CLK SOURCE SELECT C60 0.1mF C22 0.1mF –VA C55 10mF VA AD9483 Figure 39. Power Connector, Decoupling Capacitors, DC Adjust Trimpot Section AD9483 PCB LAYOUT Table IV. 25-Pin Connector Pinout The PCB is designed on a four layer (1 oz. Cu) board. Components and routing are on the top layer with a ground flood for additional isolation. Test and ground points were judiciously placed to facilitate high speed probing. Each channel has a separate 25-pin connector for it’s digital outputs. A common ground plane exists on the second layer. The third layer has the 3 split power planes: 1. 5 V analog for the ADC and preamps, 2. 3.3 V (or 5 V) ADC output supply, and 3. A separate 3.3 V supply for support logic. The fourth layer contains the –5 V plane for the preamps and additional components and routing. There is additional space for two extra components on top of the board to allow for modification. –22– Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DR (Data Ready) GND A0 A1 A2 A3 A4 A5 A6 A7 GND NC (No Connect) NC (No Connect) DRB (Data Ready Bar) GND B0 B1 B2 B3 B4 B5 B6 B7 GND NC (No Connect) REV. A AD9483 Figure 40. Layer 1. Routing and Top Layer Ground Figure 41. Layer 2 Ground Plane REV. A –23– AD9483 Figure 42. Layer 3 Split Power Planes Figure 43. Layer 4 Routing and Negative 5 V –24– REV. A AD9483 EVALUATION BOARD PARTS LIST # QTY REFDES DEVICE PACKAGE PART NUMBER VALUE SUPPLIER 1 54 C1-17, C19-50, C57, C60-62, C65 CAPACITOR 0805 C0805C104K5RAC7025 0.1 µF KEMIT 2 8 C18, C51-56, C63 CAPACITOR TAJD T491C106K016AS 10 µF KEMIT 3 16 GND1-10, PR1, PR2, PR3, PR4, PR5, PR6 PART OF PCB OMIT 4 7 J1-4, J8-10 CONNECTOR SMB B51-351-000-220 ITT CANNON 5 3 J5-7 CONNECTOR BNC 227699-2 AMP 6 3 P1-3 CONNECTOR “D” 25 PINS 745783-2 AMP 7 8 9 9 R1-3, R14-18, R24 R4-6, R11-13, R19-20, R23 RESISTOR RESISTOR 1206 1206 CRCW120675R0FT CRCW12061001FT 75 Ω 1K DALE DALE 9 4 R7-8, R76-77 RESISTOR 1206 CRCW12063010FT 301 Ω DALE 10 4 R9-10, R74-75 RESISTOR 1206 CRCW120649R9FT 49.9 Ω DALE 11 3 R21-22, R73 RESISTOR 1206 CRCW12062001FT 2K DALE 12 50 R25-72, R101-102 RESISTOR 1206 CRCW12061000FT 100 Ω DALE 13 2 R78-79 RESISTOR 1206 CRCW1206000ZT 0Ω DALE 14 6 R80-85 RESISTOR 1206 CRCW12061500FT 150 Ω DALE 15 3 R86, R89-90 RESISTOR 1206 CRCW12063600FT 360 Ω DALE 16 3 R87-88, R91 RESISTOR 1206 CRCW12062740FT 274 Ω DALE 17 3 R92, R95-96 RESISTOR 1206 CRCW12061301FT 1.3K DALE 18 3 R93-94, R97 RESISTOR 1206 CRCW12061501FT 1.5K DALE 19 3 R98-100 TRIMMER VRES 3296W001501 500 Ω BOURNES 20 2 R103-105 RESISTOR 1206 CRCW12062000F 200 Ω DALE 21 4 ST1-4 PART OF PCB STRIP10 NOT INSTALLED 22 4 ST5-8 PART OF PCB STRIP5 NOT INSTALLED 23 1 TB1 POWER CONNECTOR (2 PIECE) TB8A 95F6002 50F3583 WIELAND 24 3 TP1-3 PART OF PCB TSTPT NOT INSTALLED 25 1 U1 MC74LCX86D SO14NB MC74LCX86D MOTOROLA 26 3 U2-4 AD9760AR SO28WB AD9760AR ADI 27 1 U5 AD9483KS-140/100 MQFP-100 AD9483KS-140/100 ADI 28 6 U6-11 MC74LCX574DW SO20WB MC74LCX574DW MOTOROLA 29 4 U12, U14-16 AD8055AN SO8NB AD8055AN ADI 30 2 U13, U17 DIP20 DIP20 NOT INSTALLED 31 6 W1-3, W8-10 2 PIN JUMPER JMP-2P SEE NOTE 32 11 W4-7, W12-18 3 PIN JUMPER JMP-3P SEE NOTE 33 1 W11 6 PIN JUMPER JMP_6 SEE NOTE 34 5 FEET SJ-5518 3M NOTES All resistors are surface mount (size 1206) and have a 1% tolerance. Jumpers are Samtec parts TSW-110-08-G-D and TSW-110-08-G-S. Jumpers W1, W2, W3, W9, W8, W10 are omitted. REV. A –25– AD9483 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.921 (23.4) 0.906 (23.0) 0.791 (20.10) 0.783 (19.90) 0.742 (18.85) TYP 80 81 CONDUCTIVE HEAT SINK ON BOTTOM OF PACKAGE 51 50 51 50 0.486 (12.35) TYP 0.555 (14.10) 0.547 (13.90) TOP VIEW (PINS DOWN) (PINS UP) 0.362 (9.2) 0.551 (14.0) 0.433 (11.0) 31 30 1 31 30 100 1 PIN 1 0.787 (20.0) 0.015 (0.35) 0.009 (0.25) 0.134 (3.40) MAX 0.041 (1.03) 0.031 (0.78) 80 81 BOTTOM VIEW 0.685 (17.4) 0.669 (17.0) PIN 1 100 0.029 (0.73) 0.023 (0.57) C3268a–1–12/98 100-Lead Plastic Quad Flatpack (S-100B) 0.110 (2.80) 0.102 (2.60) SEATING PLANE 0.004 0.010 (0.10) (0.25) MAX MIN PRINTED IN U.S.A. NOTE: THE AD9483KS PACKAGE USES A COPPER INSERT TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OVER THE FULL 08C TO +858C TEMPERATURE RANGE. THIS COPPER INSERT IS EXPOSED ON THE UNDERSIDE OF THE DEVICE. IT IS RECOMMENDED THAT DURING THE DESIGN OF THE PC BOARD NO THROUGHHOLES OR SIGNAL TRACES BE PLACED UNDER THE AD9483 THAT COULD COME IN CONTACT WITH THE COPPER INSERT. COMMONLY ACCEPTED BOARD LAYOUT PRACTICES FOR HIGH SPEED CONVERTERS SPECIFY THAT ONLY GROUND PLANES SHALL BE LOCATED UNDER THESE DEVICES TO MINIMIZE NOISE OR DISTORTION OF VIDEO SIGNALS. –26– REV. A