M40T Series

M40T Series
SEMICONDUCTOR
RoHS
RoHS
TRIACs, 40A
Sunbberless
FEATURES
T2
T1
High current triac
Low thermal resistance with clip bonding
G
Low thermal resistance insulation ceramic
for insulated TO-3 package
High commutation capability
Packages are RoHS compliant
APPLICATIONS
Due to their clip assembly techinque, they provide
a superior performance in surge current handling
capabilities.
By using an internal ceramic pad, the M40T series
provides voltage insulated tab (rated at 2500V RMS )
complying with UL standards.
The snubberless concept offer suppression of RC
network and it is suitable for applications such as :
Static relays
Copy machines
Solid state switches
Microwave ovens
Motor controls
Heater controls
MAIN FEATURES
SYMBOL
VALUE
UNIT
I T(RMS)
40
A
V DRM /V RRM
600 to 1200
V
I GT(Q1)
10 to 50
mA
Light dimmers
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RMS on-state current (full sine wave)
Non repetitive surge peak on-state
current (full cycle, Tj initial = 25°C)
VALUE
UNIT
Tc = 90ºC
40
A
F =50 Hz
t = 20 ms
400
F =60 Hz
t = 16.7 ms
420
SYMBOL
TEST CONDITIONS
IT(RMS)
ITSM
I t
2
t p = 10 ms
Critical rate of rise of on-state current
IG = 2xlGT, tr≤100ns
dI/dt
F =100 Hz
Peak gate current
IGM
T p =20 µs
Peak gate power dissipation (tp = 20µs)
PGM
T j =125ºC
10
PG(AV)
T j =125ºC
1
I2t Value for fusing
Average gate power dissipation
Storage temperature range
Operating junction temperature range
www.nellsemi.com
A
800
A2s
T j =125ºC
50
A/µs
T j =125ºC
4
A
W
Tstg
- 40 to + 150
Tj
- 40 to + 125
ºC
Page 1 of 5
M40T Series
SEMICONDUCTOR
RoHS
RoHS
ELECTRICAL CHARACTERISTICS (TJ= 25 ºC unless otherwise specified)
SNUBBERLESS and Logic level (3 quadrants)
Limits
SYMBOL
IGT(1)
TEST CONDITIONS
Unit
QUADRANT
BW
I - II - III
V D = 12 V, R L = 33Ω
50
mA
1.3
V
MIN.
0.2
V
MAX.
60
mA
MAX.
VGT
I - II - III
V D = V DRM , R L = 3.3KΩ
VGD
I - II - III
T j = 125°C
IH(2)
I T = 500 mA
IL
I G = 1.2 I GT
I - III
II
dV/dt(2)
(dI/dt)c(2)
80
mA
MAX.
V D = 67% V DRM , gate open ,T j = 125°C
150
1000
V/µs
20
A/ms
MIN.
Without snubber, T j = 125°C
STATIC CHARACTERISTICS
SYMBOL
VTM(2)
VALUE
UNIT
I TM = 60 A, t P = 380 µs
T j = 25°C
MAX.
1.55
V
(2)
Threshold voltage
T j = 125°C
MAX.
0.85
V
(2)
Dynamic resistance
T j = 125°C
MAX.
10
mΩ
VD = VDRM
VR = VRRM
T j = 25°C
10
µA
5
mA
Vt0
Rd
TEST CONDITIONS
IDRM
IRRM
MAX.
T j = 125°C
Note 1: Minimum lGT is guaranted at 5% of lGT max.
Note 2: For both polarities of A2 referenced to A1.
THERMAL RESISTANCE
UNIT
VALUE
SYMBOL
Rth(j-c)
Junction to case (AC)
0.8
Rth(j-a)
Junction to ambient
50
°C/W
S = Copper surface under tab.
PRODUCT SELECTOR
VOLTAGE (x x)
PART NUMBER
M40TxxA
600 V
800 V
1000 V
1200 V
V
V
V
V
SENSITIVITY
TYPE
50 mA
Snubberless
TO-3
WEIGHT
BASE Q,TY
DELIVERY MODE
23g
50
BOX
PACKAGE
ORDERING INFORMATION
ORDERING TYPE
M40TxxA
MARKING
M40TxxA
PACKAGE
TO-3
Note : xx = voltage
www.nellsemi.com
Page 2 of 5
M40T Series
SEMICONDUCTOR
RoHS
RoHS
ORDERING INFORMATION SCHEME
M 40 T
60
A
Module type
M = TO-3 Fast-on package
Current
40 = 40A
Triac series
Voltage
60 = 600V
80 = 800V
100 = 1000V
120 = 1200V
Assembly type
A = Soldering Assembly
Fig.1 Maximum power dissipation versus on-state RMS
current (full cycle)
Fig.2 On-state RMS current versus case temperature
(full cycle)
P (W)
IT(RMS) (A)
50
45
α=180°
40
40
35
30
30
25
20
20
180°
15
α
10
10
α
I T(RMS) (A)
Tc(°c)
5
0
0
0
5
10
15
20
25
30
35
40
0
Fig.3 Relative variation of thermal impedance
versus pulse duration.
25
75
50
100
125
Fig.4 On-state characteristics (maximum values).
K=[Zth/Rth]
ITM(A)
1E+00
400
Zth(j-c)
100
Tj=Tj max
1E-01
Tj=25°C
10
1E-02
VTM(V)
tp(s)
1E-03
1E-03
1E-02
www.nellsemi.com
1E-01
1E+00
Tj max.
Vto = 0.85 V
Rd = 10 mΩ
1E+01
1E+02
1E+0.3
Page 3 of 5
1
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
M40T Series
SEMICONDUCTOR
RoHS
RoHS
Fig.6 Non-repetitive surge peak on-state current
for a sinusoidal pulse and corresponding
value of l 2 t.
Fig.5 Surge peak on-state current versus number
of cycles.
ITSM(A),l2t(A2s)
ITSM(A)
10000
450
I TSM
400
t=20ms
350
One cycle
Non repetitive
300
1000
I2t
Tj initial=25°C
250
T j initial =25°C
Pulse width tp <10 ms
dl/dt limitation
50A/µs
200
Repetitive
Tc=70°C
150
100
50
tp(ms)
Number of cycles
0
10
1
100
1000
100
0.01
Fig.7 Relative variation of gate trigger, holding
and latching current versus junction
temperature.
0.10
1.00
10.00
Fig.8 Relative variation of critical rate of decrease
of main current versus (dV/dt)c (typical values).
(dI/dt)c [(dV/dt)c] / specified (dI/dt)c
l GT , l H , l L [T j ] / l GT ,l H ,l L [T j =25°C]
2.0
2.5
1.8
2.0
1.6
l GT
1.4
1.5
Typical values
1.2
lH & lL
1.0
1.0
0.8
0.5
0.6
T j (°C)
0.0
-40
-20
0
20
40
60
80
100
120
140
Fig.9 Relative variation of critical rate of decrease
of main current versus (dV/dt)c.
(dI/dt)c [Tj] / (dI/dt)c [Tj specified]
6
5
4
3
2
1
0
T j (°C)
0
(dV/dt)c (V/µs)
0.4
25
www.nellsemi.com
50
75
100
125
Page 4 of 5
0.1
1.0
10.0
100.0
M40T Series
SEMICONDUCTOR
Case Style
TO-3
2-Ø4.2±0.1
30.0±0.1
0.35±0.15
7.95±0.15
9.75±0.3
Ø1.3(G)
5-Ø1.3±0.2
3.0±0.3
All dimensions in millimeters
www.nellsemi.com
Page 5 of 5
RoHS
RoHS