FSA506 AMP506 (FSA0AC197A) FSA506 AMP506 Preliminary Specification Version 0.3 Date: 2007/06/02 Prepared by: Y.C. Lee 0 Revise History Date Version Description Owner 2007/03/08 V 0.1 Initialized Release Y.C. 2007/04/27 V 0.2 Register setting Y.C. 2007/06/02 V 0.3 General function added Y.C. 0 Revise History .............................................................. 3 1 Introduction .................................................................. 6 2 Block Diagram .............................................................. 7 3 System Organization.................................................... 8 3.1 MPU interface connection............................................................................................................8 3.1.1 68-series interface ........................................................................................................... 8 3.1.2 80-series interface ........................................................................................................... 8 3.2 Input Interface ..............................................................................................................................9 3.3 Memory Configuration.................................................................................................................9 3.4 Output 3.4.3 3.4.4 3.4.5 3.5 Internal oscillator & PLL.............................................................................................................11 3.6 POR ...............................................................................................................................................11 3.7 Pin description ............................................................................................................................12 3.7.1 Pin assignment .............................................................................................................. 12 3.7.2 Power supply ................................................................................................................. 13 3.7.3 Output pin ...................................................................................................................... 14 3.7.4 Input pin ......................................................................................................................... 15 unit..................................................................................................................................10 Output data for serial delta panel .................................................................................. 10 Output data for serial stripe panel ................................................................................. 10 Output data for parallel panel ........................................................................................ 11 4 General Description ................................................... 17 4.1 Input data transfer order...........................................................................................................17 4.2 WRITE command format ............................................................................................................17 4.2.1 Register setting command format.................................................................................. 19 4.2.2 Memory write command format ..................................................................................... 19 4.3 READ command format .............................................................................................................19 4.3.1 Read from register ......................................................................................................... 21 4.3.2 Read from internal memory ........................................................................................... 21 4.4 Display control............................................................................................................................21 5 Register Description .................................................. 22 5.1 Register Setting ..........................................................................................................................22 6 Electrical Specification .............................................. 30 6.1 DC characteristics ......................................................................................................................30 6.2 AC characteristics.......................................................................................................................31 6.2.1 80-series AC timing table............................................................................................... 31 6.2.2 80-series AC timing chart .............................................................................................. 31 6.2.3 68-series AC timing table............................................................................................... 32 6.2.4 68-series AC timing chart .............................................................................................. 32 7 Package Outline ......................................................... 33 1 Introduction AMP506 is a CPU interface based TFT LCD controller. It can support panel resolution up to 640x240 FSA506 pixels with 262144 colors depth. User can send either a full screen picture or a partial image by controlling the MPU with popular microprocessor interface, 18/16/9/8 bits 68-series or 80-series. Output data and synchronization signals will be delivered to TCON simultaneously. The integrated on-chip functions include: z Supported panel resolution - Max. 153600 pixels ( H x V ) resolution z Built-in separated RGB SRAM with 18-bits addressing space z MPU data transfer interface - 18/16/9/8-bis 68-series system - 18/16/9/8-bis 80-series system z Both delta and stripe type panel supported z Build in Images rotate and shift function z Arbitrary display memory address access z Supply voltage: 3.3v z 100 pin LQFP package 2 Block Diagram 3.3V 1.8V FD506 Regulator CPU I/F IM[5:0] CS RS RD WR Data[17:0] RESETB SRAM Output Control Input Control Latch POR SRAM Control VBG OSC VS HS DE DCLK Data[17:0] LCD Panel 3 System Organization 3.1 MPU interface connection FD506 can support both MPU interfaces with variable data bus width. User can change to different mode by configuring the input ports and related registers. These two interfaces are 68-series and 80-series z 68-series: Without address bus, data bus may be configured to 18/9/16/8 bits. z 80-series: same as 68 series but the way of controlling signals. 3.1.1 68-series interface RW (X_RD) RS(X_RS) 68--series E (X_WR) CSB(X_CS) DI[17:0] 3.1.2 80-series interface RDB(X_RD) RS(X_RS) 80--series WRB(X_WR) CSB(X_CS) DI[17:0] 3.2 Input Interface FD506 has variable interface data input including 8/9/16/18 bits and data depth (666 or 565), therefore before writing into memory it needs to be latched and normalized. The aim of this block is to normalize the input data from variable MPU interface and save them to memory in regular way. Following diagram shows the data flow in this block. 8-bits (latch) 16-bits (latch) 16-bits 8-bits MUX 18-bits 18-bits 3.3 Memory Configuration The size of SRAM of FD506 is 640x240x3x6 bits. It can be configured into 6 parts and each part has 6 bits width. 6 - b its 6 - b its 6 -b its R -S R A M -1 G -S R A M -1 B -S R A M -1 R -S R A M - 2 G -S R A M - 2 B -S R A M -2 A d d r [0 ] A d d r [1 ] A d d r [6 5 5 3 5 ] A d d r [0 ] A d d r [1 ] A d d r [8 8 0 6 3 ] 3.4 Output unit Output controller is a unit translating the parallel data to serial one and ordering the sequence of data read from memory. It has several functions including: z Control data direction of accessing memory z Translate the parallel data to serial z Generate output sync. timing z Switch data sequence to meet delta and stripe type TFT LCD panel 3.4.3 Output data for serial delta panel 1st dot out_dclk 3.4.4 odd line R1 G1 B1 R2 even line B1 R1 G1 B2 Output data for serial stripe panel 1st dot out_dclk odd line R1 G1 B1 R2 even line R1 G1 B1 R2 3.4.5 Output data for parallel panel 1st dot out_dclk 3.5 R1 R2 R3 R4 G1 G2 G3 G4 B1 B2 B3 B4 Internal oscillator & PLL Generate 80MHz clock (SYS_CLK) to all system. VBG 3.6 SYS_C LK S e lfo s c illa to r PLL POR VCC re s POR por 3.7 Pin description 3.7.1 Pin assignment 3.7.2 Power supply Pin-no Symbol I/O Description 1 R_V18 P Regulator 1.8V power out 2 VCCAH P Regulator 3.3V power in 3 GNDA_REG P Regulator ground 4 GNDA_OSC P Oscillator ground 5 GNDA_PLL P PLL ground 6 VCC18V_PLL P PLL power in 11, 18, 23, 30, 36, 43, 50, 55, 62, 70, 77, 83, 88, 95 17, 22, 29, 35, 42, 49, 61, 69, 76, 82, 87, 94, 100 27, 41, 57, 67, 79, 91 8, 46, 63, 74, 89 VCCK P Core power GNDK P Core ground VCCIO P Pad power GNDIO P Pad ground Remark 3.7.3 Output pin Pin-no Symbol I/O Description 59 X_VSYNC O V sync. output pin 60 X_HSYNC O H sync. output pin 64 X_ODE O Data enable output pin 65 X_OCLK O Clock output pin 66 DO00 O Data output pin 68 DO01 O 71 DO02 O 72 DO03 O 73 DO04 O 75 DO05 O 78 DO06 O 80 DO07 O 81 DO08 O 84 DO09 O 85 DO10 O 86 DO11 O 90 DO12 O 92 DO13 O 93 DO14 O 96 DO15 O 97 DO16 O 98 DO17 O 99 DCON O DC/DC on/off pin Remark 3.7.4 Input pin Pin-no Symbol I/O Description 10 X_TESTEN I Test mode enable pin 12 X_TIN0 I Test mode reserved 13 X_TIN1 I Test mode reserved 14 X_IM0 I 15 X_IM1 I 16 X_IM2 I 19 X_IM3 I 20 X_IM4 I 21 X_IM5 I Transport Interface selection X_IM5: Data type 0: 16-bits data (565); 1: 18-bits data (666) X_IM4: Data byte transfer order 0: LSB first; 1: MSB first X_IM[3:0] MPU interface mode 0 80 mode 18-bit bus interface 0 1 80 mode 16-bit bus interface 0 0 80 mode 9-bit bus interface 1 1 80 mode 8-bit bus interface 0 0 68 mode 18-bit bus interface 0 1 68 mode 16-bit bus interface 1 0 68 mode 9-bit bus interface 1 1 68 mode 8-bit bus interface 24 X_RS I Control signal 25 X_CS I Control signal 26 X_WR I Control signal 28 X_RD I Control signal 31 X_DI00 I/O 32 X_DI01 I/O 33 X_DI02 I/O 34 X_DI03 I/O 37 X_DI04 I/O 38 X_DI05 I/O 39 X_DI06 I/O 40 X_DI07 I/O Data Input/output pin X_IM[1:0] 00 01 10 11 Bus-type 18 bits 16 bits 9 bits 8 bits Valid data bus X_DI17 - X_DI00 X_DI15 - X_DI00 X_DI08 - X_DI00 X_DI07 - X_DI00 Remark Pin-no Symbol I/O 44 X_DI08 I/O 45 X_DI09 I/O 47 X_DI10 I/O 48 X_DI11 I/O 51 X_DI12 I/O 52 X_DI13 I/O 53 X_DI14 I/O 54 X_DI15 I/O 56 X_DI16 I/O 58 X_DI17 I/O Description Remark 4 General Description 4.1 Input data transfer order This chip supports four bus widths, 8/9/16/18, for transporting 16 (565) or 18 (666) bits data. In some setting mode of X_IM [5:0], data has to be segmented in several parts. Once transferring start, the following rule of order must be kept: 17 16 15 87 B2 B1 17 B0 98 DB1 Bus type 8-bits 9-bits 16-bits 18-bits 4.2 0 X_IM [5] = 0 (16 bits) X_IM [4] = 0 X_IM [4] = 1 B0 -> B1 B1 -> B0 Not allowed (B1, B0) Not allowed 0 DB0 X_IM [5] = 1 (18 bits) X_IM [4] = 0 X_IM [4] = 1 B0 -> B1 -> B2 B2 -> B1 -> B0 DB0 -> DB1 DB1 -> DB0 (B1, B0) -> B2 B2 -> (B1, B0) (B2, B1, B0) WRITE command format All commands have 8 bits width with each bit has its own definition. Through command issues, the coming data can be direct to register for system setting or memory for access. Following shows how to issues a command in both 80-series and 68-series mode 80-series mode issues a command 68-series mode issues a command 80-series mode writes a data 68-series mode writes a data 4.2.1 Register setting command format 7 0 6 0 Register Address EX: Write burst value 0 to 3 to register address from 7’h23 to 7’h26 command order command counting address value 1st WC 8’h23 2nd WD 23 8’h0 3rd WD 24 8’h1 4th WD 25 8’h2 5th WD 26 8’h3 where WC represents writes a command and WD represents writes a data 4.2.2 Memory write command format 7 1 6 Start 0 MEM Reserved Start : memory access start bit MEM: display memory selection EX: Write burst value 0 to 3 to display area which has been defined in register command order command counting address value 4.3 1st WC 8’hc1 2nd WD addr1 8’h0 3rd WD addr2 8’h1 4th WD addr3 8’h2 5th WD addr4 8’h3 READ command format Register value and Memory data can be read out from the chip by issue read command show below: 80-series mode reads a command 68-series mode reads a command 80-series mode reads a data 68-series mode reads a data 4.3.1 Read from register Following example shows how to read value in burst from register EX: read burst value from register address 7’h23 to 7’h26 command order command counting address value 1st WC 8’h23 2nd RD 23 8’h0 3rd RD 24 8’h1 4th RD 25 8’h2 5th RD 26 8’h3 where RD represents reads a data 4.3.2 Read from internal memory EX: read burst value from display area which has been defined in register command order command counting address value 4.4 1st WC 8’hc1 2nd RD addr1 8’h0 3rd RD addr2 8’h1 4th RD addr3 8’h2 5th RD addr4 8’h3 Display control All display areas such as panel visual period is treated as a coordinate image. Any image that smaller than or equal to this period can be transported and displayed in any place of this period which four vertexes coordinates defined. 5 Register Description 5.1 Address #00 Bit [7:0] Address #01 Bit [7:0] Address #02 Bit [7:0] Register Setting Default: 00 Description MSB of horizontal start coordinate value Default: 00 Description LSB of horizontal start coordinate value Defaults: 01 Description MSB of horizontal end coordinate value Address #03 Bit [7:0] Description LSB of horizontal end coordinate value Address #04 Bit [7:0] Description MSB of vertical start coordinate value Address #05 Bit [7:0] Address #06 Bit [7:0] Address #07 Bit [7:0] Defaults: 3F Defaults: 00 Defaults: 00 Description LSB of vertical start coordinate value Defaults: 00 Description MSB of vertical end coordinate value Defaults: EF Description LSB of vertical end coordinate value Address #08 Bit [7:2] [1:0] Address #09 Bit [7:0] Address #0A Bit [7:2] [1:0] Address #0B Bit [7:0] Address #0C Bit [7:0] Address #10 Bit [7] [6] [5:4] [3] [2] Defaults: 01 Description Reserved MSB of input image horizontal resolution Defaults: 40 Description LSB of input image horizontal resolution Defaults: 00 Description Reserved [17:16] bits of memory write start address Defaults: 00 Description [15:8] bits of memory write start address Defaults: 00 Description [7:0] bits of memory write start address Defaults: 0D Description Output data bits swap 0: Normal 1:Swap Output test mode enable 0: disable 1: enable Serial mode data out bus selection 00: X_ODATA17 ~ X_ODATA12 active , others are set to zero 01: X_ODATA11 ~ X_ODATA06 active , others are set to zero 10: X_ODATA05 ~ X_ODATA00 active , others are set to zero 11: reserved Output data blanking 0: set output data to 0 1: Normal display Parallel or serial mode selection 0: serial data out 1: parallel data output [1:0] Address #11 Bit [7] [6:4] [3] [2:0] Address #12 Bit [7:4] [3:0] Address #13 Bit [7:0] Output clock selection 00: system clock divided by 2 01: system clock divided by 4 10: system clock divided by 8 11: reserved Defaults: 00 Description Reserved Even line of serial panel data out sequence or data bus order of parallel panel 000: RGB 001: RBG 010: GRB 011: GBR 100: BRG 101: BGR Others: reserved Reversed Odd line of serial panel data out sequence 000: RGB 001: RBG 010: GRB 011: GBR 100: BRG 101: BGR Others: reserved Defaults: 00 Description Reserved MSB of output H sync. pulse start position Defaults: 00 Description LSB of output H sync. pulse start position Address #14 Bit [7:4] [3:0] Address #15 Bit [7:0] Address #16 Bit [7:4] [3:0] Address #17 Bit [7:0] Defaults: 00 Description Reserved MSB of output H sync. pulse width Defaults: 10 Description LSB of output H sync. pulse width Defaults: 00 Description Reserved MSB of output DE horizontal start position Defaults: 38 Description LSB of output DE horizontal start position Address #18 Bit [7:4] [3:0] Reserved MSB of output DE horizontal active region in pixel Address #19 Bit [7:0] Description LSB of output DE horizontal active region in pixel Address #1a Bit [7:4] [3:0] Address #1b Bit [7:0] Defaults: 01 Description Defaults: 40 Defaults: 01 Description Reserved MSB of output H total in pixel Defaults: B8 Description LSB of output H total in pixel Address #1C Bit [7:4] [3:0] Address #1D Bit [7:0] Address #1E Bit [7:4] [3:0] Address #1F Bit [7:0] Defaults: 00 Description Reserved MSB of output V sync. pulse start position Default: 00 Description LSB of output V sync. pulse start position Defaults: 00 Description Reserved MSB of output V sync. pulse width Defaults: 08 Description LSB of output V sync. pulse width Address #20 Bit [7:4] [3:0] Reserved MSB of output DE vertical start position Address #21 Bit [7:0] Description LSB of output DE vertical start position Address #22 Bit [7:4] [3:0] Address #23 Bit [7:0] Defaults: 00 Description Defaults: 12 Defaults: 00 Description Reserved MSB of output DE vertical active region in line Defaults: F0 Description LSB of output DE vertical active region in line Address #24 Bit [7:4] [3:0] Address #25 Bit [7:0] Address #26 Bit [7:2] [1:0] Address #27 Bit [7:0] Address #28 Bit [7:0] Address #29 Bit [7:1] [0] Address #2a Bit [7:6] [5:0] Address #2b Bit [7:6] [5:0] Address #2c Bit [7:6] [5:0] Defaults: 01 Description Reversed MSB of output V total in line Defaults: 09 Description LSB of output V total in line Defaults: 00 Description Reserved [17:16] bits of memory read start address Defaults: 00 Description [15:8] bits of memory read start address Defaults: 00 Description [7:0] bits of memory read start address Defaults: 00 Description Reversed Load output timing related setting (H sync., V sync. and DE) to take effect Defaults: 00 Description Reserved Output value setting R when output test mode enable (ref. register #10) Defaults: 00 Description Reserved Output value setting G when output test mode enable (ref. register #10) Defaults: 00 Description Reserved Output value setting B when output test mode enable (ref. register #10) Address #2d Bit [7:4] [3] [2] [1:0] Address #30 Bit [7:4] [3:0] Address #31 Bit [7:0] Address #32 Bit [7:4] [3:0] Address #33 Bit [7:0] Defaults: 00 Description Reserved Output pin X_DCON level control Output clock inversion 0: Normal 1: Inverse Image rotate 00: 0̓ 01: 90̓ 10: 270̓ 11: 180̓ Defaults: 00 Description Reserved MSB of image horizontal shift value Defaults: 00 Description LSB of image horizontal shift value Defaults: 00 Description Reserved MSB of image vertical shift value Defaults: 00 Description LSB of image vertical shift value Address #34 Bit [7:4] [3:0] Defaults: 01 Reserved MSB of image horizontal physical resolution in memory Address #35 Bit [7:0] Description LSB of image horizontal physical resolution in memory Description Defaults: 40 Address #36 Bit [7:4] [3:0] Address #37 Bit [7:0] Address #40 Bit [7:6] [5] [4] [3] [2:1] [0] Address #41 Bit [7:6] [5:0] Address #42 Bit [7:6] [5:0] Defaults: 01 Description Reserved MSB of image vertical physical resolution in memory Defaults: E0 Description LSB of image vertical physical resolution in memory Defaults: 12 Description Reserved PLL control pins to select out frequency range 0: 20MHz ~ 100MHz 1: 100MHz ~ 300MHz Reserved Reserved Output Driving Capability 00: 4mA 01: 8mA 10: 12mA 11: 16mA Output slew rate 0: Fast 1: Slow Defaults: 01 Description Reserved PLL Programmable pre-divider, 6bit(1~63) Defaults: 02 Description Reserved PLL Programmable loop divider, 6bit(1~63) 6 Electrical Specification 6.1 DC characteristics DC Characteristics of 3.3V with 5V Tolerance I/O Cells Symbol Parameter Condition Min Typ Max Unit VCCK Core power supply Core area 1.62 1.8 1.98 V VCC3I Power supply 3.3V I/O 2.97 3.3 3.63 V VCC3O Power supply 2.97 3.3 3.63 V Tj Junction temperature -40 25 125 к Vil Input low voltage 0.8 V Vih Input high voltage Vt Switching threshold LVTTL 1.5 V Vt- Schmitt trigger negative going threshold voltage LVTTL 0.8 1.1 Vt+ Schmitt trigger positive going threshold voltage Vol Output low voltage Iol = 2 ~ 16 mA Voh Output high voltage Ioh = -2 ~ -16 mA 2.4 Rpu Input pull-up resistance Vin = 0 40 75 190 K Rpd Input pull-down resistance Vin = VCC3I 40 75 190 K Input leakage current Vin = 5.5V or 0 Input leakage current with pull-up resistance Vin = 0 -15 -45 -85 uA Input leakage current with pull-down resistance Vin = VCC3I 15 45 85 uA Tri-state output leakage current Vin = 5.5V or 0 Iin Ioz LVTTL 2.0 V 1.6 V 2.0 V 0.4 V V ±5 ±10 uA uA 6.2 AC characteristics 6.2.1 Symbol tcycle PWHW PWLW tAS tAH tDSW tHWR tcsb-s tcsb-h 80-series AC timing table Parameter Enable cycle time Enable high-level pulse width Enable low-level pulse width RS setup time RS hold time Write data setup time Write data hold time CSB setup time CSB hold time 6.2.2 Min Typ 100 66 33 16 16 50 50 16 16 200 70 130 25 45 50 40 20 30 Max Unit ns ns ns ns ns ns ns ns ns 80-series AC timing chart RS(X_RS) tAS tAH CSB(X_CS) t csb-h t csb-s PWLW PWHW WRB(X_WR) tDSW DI[17:0] Valid Data tHWR t cycle Remark 6.2.3 Symbol tcycle PWEH PWEL tASE tAHE tDSWE tHE tcsb-s tcsb-h 68-series AC timing table Parameter Enable cycle time Enable high-level pulse width Enable low-level pulse width RS setup time RS hold time Write data setup time Write data hold time CSB setup time CSB hold time 6.2.4 68-series AC timing chart Min Typ 100 33 66 16 16 50 50 16 16 200 70 130 25 45 50 40 20 30 Max Unit ns ns ns ns ns ns ns ns ns Remark 7 Package Outline LQFP 100