FSA506 Application Note
a-Si TFT LCD Controller
640xRGBx240 Resolution
262K color
Vresion 1.0
Date:2008/01/07
Date : 2008/01/07
1
FSA506 Application Note
1
RECORD
2
FEATURES .......................................................................................................................................... 4
3
BLOCK DIAGRAM ............................................................................................................................. 5
4
PIN DESCRIPTION............................................................................................................................. 5
4.1
OF REVISION ............................................................................................................. 3
PIN ASSIGNMENT ........................................................................................................................... 5
4.1.1
Power Supply Pins ................................................................................................................... 6
4.1.2
Output Pins .............................................................................................................................. 7
4.1.3
Input Pins................................................................................................................................. 8
5
APPLICATION CIRCUIT.................................................................................................................... 9
6
JUMPER SETTING ...........................................................................................................................11
7
INTERFACE PROTOCOL ............................................................................................................... 12
7.1
18BIT-80/68-WRITE TO COMMAND REGISTER............................................................................. 12
7.2
18BIT-80/68-WRITE TO DISPLAY RAM ....................................................................................... 13
7.3
16BIT-80/68- WRITE TO COMMAND REGISTER ............................................................................ 13
7.4
16BIT-80/68-WRITE TO DISPLAY RAM ....................................................................................... 14
7.5
9BIT-80/68- WRITE TO COMMAND REGISTER .............................................................................. 15
7.6
9BIT-80/68-WRITE TO DISPLAY RAM ......................................................................................... 15
7.7
8BIT-80/68- WRITE TO COMMAND REGISTER .............................................................................. 16
7.8
8BIT-80/68-WRITE TO DISPLAY RAM ......................................................................................... 17
7.9
DATA TRANSFER ORDER SETTING ................................................................................................ 18
8
REGISTER DEPICTION .................................................................................................................. 19
9
REFERENCE INITIAL CODE : ....................................................................................................... 28
9.1
8BIT-80 INTERFACE MODE , 65K COLOR , PANEL:320XRGBX240 , LANDSCAPE .......................... 28
9.2
8BIT-80 INTERFACE MODE , 65K COLOR , PANEL:320XRGBX240 , PORTRAIT .............................. 34
Date : 2008/01/07
2
FSA506 Application Note
1
RECORD
OF REVISION
Revision Date Page
2008/1/7
-
Date : 2008/01/07
Contents
Editor
New Release
3
FSA506 Application Note
2 Features
FSA506 is a CPU interface based TFT LCD controller. It can support panel resolution up to
640x240 pixels with 262144 colors depth. User can send either a full screen picture or a
partial image by controlling the MPU with popular microprocessor interface：
z
18 bit 8080-series MPU
z
16 bit 8080-Series MPU
z
9 bit 8080-Series MPU
z
8 bit 8080-Series MPU
z
18 bit 6800-Series MPU
z
16 bit 6800-Series MPU
z
9 bit 6800-Series MPU
z
8 bit 6800-Series MPU
The integrated on-chip functions include:
z
Supported panel resolution
z
- Max. 153600 pixels ( H x V ) resolution
z
Built-in separated RGB SRAM with 18-bits addressing space
z
Both delta and stripe type panel supported
z
Build in Images rotate and shift function
z
Arbitrary display memory address access
z
Supply voltage: 3.3v
z
100 pin LQFP package
Date : 2008/01/07
4
FSA506 Application Note
3 Block Diagram
3.3V
1.8V
Regulator
SRAM
640x240x18 bits
MPU
Interface
Input
Logic
TFT
Panel
Output
Logic
SRAM Control
POR
(Power On Reset)
OSC PLL
4 Pin Description
DO05
GNDIO
DO04
DO03
DO02
VCCK
GNDK
DO01
VCC3IO
DO00
X_OCLK
X_ODE
GNDIO
VCCK
GNDK
X_HSYNC
X_VSYNC
DIO17
VCC3IO
DIO16
VCCK
DIO15
DIO14
DIO13
DIO12
X_WR
VCC3IO
X_RD
GNDK
VCCK
DIO0
DIO1
DIO2
DIO3
GNDK
VCCK
DIO4
DIO5
DIO6
DIO7
VCC3IO
GNDK
VCCK
DIO8
DIO9
GNDIO
DIO10
DIO11
GNDK
VCCK
R_V18
VCCAH
GNDA_REG
GNDA_OSC
VCCA_OSC
GNDA_PLL
VCC18V_PLL
GNDIO
X_RESETB
X_TESTEN
VCCK
X_TINT0
X_TINT1
X_IM0
X_IM1
X_IM2
GNDK
VCCK
X_IM3
X_IM4
X_IM5
GNDK
VCCK
X_RS
X_CS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GNDK
DCON
DO17
DO16
DO15
VCCK
GNDK
DO14
DO13
VCC3IO
DO12
GNDIO
VCCK
GNDK
DO11
DO10
DO09
VCCK
GNDK
DO08
DO07
VCC3IO
DO06
VCCK
GNDK
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
4.1 Pin assignment
Date : 2008/01/07
5
FSA506 Application Note
4.1.1Power Supply Pins
Pin-No
1
2
3
4
5
6
11,18,23,
30,36,43,
50,55,62,
70,77,83,
88,95
17,22,29,
35,42,49,
61,69,76,
82,87,94
100
27,41,57,
67,79,91
Symbol
R_V18
VCCAH
GNDA_REG
GNDA_ SC
GNDA_PLL
VCC18V_PLL
VCCK
I/O
P
P
P
P
P
P
P
Description
Regulator 1.8V output
Regulator 3.3V Power in
Regulator ground
Oscillator ground
PLL ground
PLL power in
Core Power input
GNDK
P
Core Power ground
VCCIO
P
I/O Power Input
8,46,63,
74,89
GNDIO
P
I/O ground
Date : 2008/01/07
Remark
6
FSA506 Application Note
4.1.2Output Pins
Pin-No Symbol
I/O
59
X_VSYNC
O
60
X_HSYNC
O
64
X_ODE
O
65
X_OCLK
O
66
DO00
O
68
DO01
O
71
DO02
O
72
DO03
O
73
DO04
O
75
DO05
O
78
DO06
O
80
DO07
O
81
DO08
O
84
DO09
O
85
DO10
O
86
DO11
O
90
DO12
O
92
DO13
O
93
DO14
O
96
DO15
O
97
DO16
O
98
DO17
O
99
DCON
Date : 2008/01/07
O
Description
Vertical sync signal output pin
Horizontal sync signal output pin
Data Enable Output Pin
Dot Clock Output Pin
Display Data Output Pin
Remark
It is the GPIO pin for control the
external DC/DC On off
7
FSA506 Application Note
4.1.3Input Pins
Pin-No
10
12
13
14
15
16
19
20
21
Symbol
I/O Description
Test mode enable Pin. Connect to ground for
X_TESTEN I
normal operation
Test mode reserved. Connect to ground for
X_TIN0
I
normal operation
Test mode reserved. Connect to ground for
X_TIN1
I
normal operation
Interface select pins
X_IM0
I
X_IM[3:0]
MPU interface mode
0 80-18bit bus interface
0
1 80-16bit bus interface
X_IM1
I
0
0 80-9bit bus interface
1
1 80-8bit bus interface
0
X_IM2
I
0 68-18bit bus interface
0
1 68-16bit bus interface
1
0 68-9bit bus interface
X_IM3
I
1
1 68-8bit bus interface
X_IM4
I Transport interface selection:
X_IM4: Data byte transfer order
0: LSB first 1:MSB first
X_IM5
I X_IM5 : Data type
0:16-bits data (565) 1:18-bits data (666)
24
25
X_RS
X_CS
26
X_WR
28
X_RD
31
32
33
34
37
38
39
40
44
45
47
48
51
52
53
54
56
58
X_DIO0
X_DIO1
X_DIO2
X_DIO3
X_DIO4
X_DIO5
X_DIO6
X_DIO7
X_DIO8
X_DIO9
X_DIO10
X_DIO11
X_DIO12
X_DIO13
X_DIO14
X_DIO15
X_DIO16
X_DIO17
Date : 2008/01/07
Remark
I
I
Register / Data select pin
Chip select low active
80mode : /WR low active
I
68mode : E signal latch on rising edge
80mode : /RD low active
I
68mode : R/W signal Hi: read, Lo:Write
I/O MCU Data Bus input pins
I/O
Valid data
I/O X_IM[1:0] Bus_type
bus
I/O
00
18-bits
X_DIO17~0
I/O
16-bits
X_DIO15~0
I/O 01
9 bits
X_DIO8~0
I/O 10
8 bits
X_DIO7~0
I/O 11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
8
FSA506 Application Note
5 Application Circuit
X_VYNC
C31
NC
CN2 {TFT PANEL Output Interface (24bit RGB)}
B4
B5
B0
B1
B2
B3
B4
B5
Panel B0
Panel B1
Panel B2
Panel B3
Panel B4
Panel B5
Panel B6
Panel B7
DGND
LCD_DCLK
DGND
LCD_DE
LCD_VS
LCD_HS
VCC33
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Panel R0
Panel R1
Panel R2
Panel R3
Panel R4
Panel R5
Panel R6
Panel R7
DGND
Panel G0
Panel G1
Panel G2
Panel G3
Panel G4
Panel G5
Panel G6
Panel G7
R14
X_DCLK
R4
R5
R0
R1
R2
R3
R4
R5
G4
G5
G0
G1
G2
G3
G4
G5
LCD_DCLK
0
C30
NC
CN1( MCU Input interface)
/RESET
/RD
/WR
/CS
RS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
VDD
DGND
65K/262K
RA5
X_DE
X_VYNC
X_HYNC
R5
8
7
6
5
4
3
2
1
LCD_DE
LCD_VS
LCD_HS
LCD_D5
RN0603 5% 8P4R 33R
RA6
R4
R3
R2
R1
8
7
6
5
4
3
2
1
LCD_D4
LCD_D3
LCD_D2
LCD_D1
HEADER 17X2
RN0603 5% 8P4R 33R
RA7
CN3{TFT PANEL Output Interface (18bit RGB)}
B0
B1
B2
B3
B4
B5
Panel B0
Panel B1
Panel B2
Panel B3
Panel B4
Panel B5
DGND
LCD_DCLK
DGND
LCD_DE
LCD_VS
LCD_HS
VCC33
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
Panel R0
Panel R1
Panel R2
Panel R3
Panel R4
Panel R5
R0
R1
R2
R3
R4
R5
DGND
Panel G0
Panel G1
Panel G2
Panel G3
Panel G4
Panel G5
G0
G1
G2
G3
G4
G5
R0
G5
G4
G3
8
7
6
5
LCD_D0
LCD_D11
LCD_D10
LCD_D9
RA8
8
7
6
5
4
3
2
1
LCD_D8
LCD_D7
LCD_D6
LCD_D17
RN0603 5% 8P4R 33R
RA9
B4
B3
B2
B1
HEADER 17X2
8
7
6
5
4
3
2
1
LCD_D16
LCD_D15
LCD_D14
LCD_D13
RN0603 5% 8P4R 33R
B0
R14
LCD_D12
33R
Date : 2008/01/07
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
HEADER 17X2
4
3
2
1
RN0603 5% 8P4R 33R
G2
G1
G0
B5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
9
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
DGND
DGND
FSA506 Application Note
VCC33
VCCK_V18
VCCK_V18
C1
0.1uF/25V
R1
10K/0603
80
1
2
0 ohm/0603 焊 1,2
3
1
REG_GND
3
VCC33
REG_GND
68
C13
1uF/25V
VCC33
1V8
R2
NC
REG_GND
R4
REG_GND
16BIT
R3
NC
IM3
R5
0 ohm/0603
4
3
2
1
R6
VCC33
REG_GND
REG_GND
R7
R8
VCC33IN
4
3
2
1
REG_GND
VCC33
VCC33
VCC33
65k COLOR
JP2
2
1
2
2K/0603 RCA03-4D
3
8BIT
1
REG_GND
3
VCC33
R9
0 ohm/0603
262K COLOR
R10
0 ohm/0603 焊 1,2
RA4
8
7
6
5
VCCK_V18
0 ohm/0603
RA3
IM0
IM1
IM4
IM5
PLL_V18
0 ohm/0603
9BIT
8
7
6
5
OSC_V18
0 ohm/0603
2K/0603 RCA03-4D
IM0
IM1
IM4
IM5
R_V18
0 ohm/0603
RA2
8
7
6
5
4
3
2
1
GNDK
DCON
DO17
DO16
DO15
VCCK
GNDK
DO14
DO13
VCC3IO
DO12
GNDIO
VCCK
GNDK
DO11
DO10
DO09
VCCK
GNDK
DO08
DO07
VCC3IO
DO06
VCCK
GNDK
REG_GND
REG_GND
REG_GND
VCC33
2K/0603 RCA03-4D
IM0
IM1
IM4
IM5
REG_GND
VCC_3V3
0 ohm/0603
VCC33
VCC33
VCC33
R11
REG_3V3
R_V18
1
REG_3V3 2
REG_GND 3
OSC_GND 4
OSC_V18 5
PLL_GND 6
PLL_V18 7
IO_GND
8
/RESET
9
TESTEN 10
VCCK_V18 11
TINT0
12
TINT1
13
IM0
14
IM1
15
IM2_68/80 16
CORE_GND 17
VCCK_V18 18
IM3
19
IM4
20
IM5
21
CORE_GND 22
VCCK_V18 23
RS
24
/CS
25
0 ohm/0603
65K/262K
R_V18
VCCAH
GNDA_REG
GNDA_OSC
VCCA_OSC
GNDA_PLL
VCC18V_PLL
GNDIO
X_RESETB
X_TESTEN
VCCK
X_TINT0
X_TINT1
X_IM0
X_IM1
X_IM2
GNDK
VCCK
X_IM3
X_IM4
X_IM5
GNDK
VCCK
X_RS
X_CS
DO05
GNDIO
DO04
DO03
DO02
VCCK
GNDK
DO01
VCC3IO
DO00
X_OCLK
X_ODE
GNDIO
VCCK
GNDK
X_HSYNC
X_VSYNC
DIO17
VCC3IO
DIO16
VCCK
DIO15
DIO14
DIO13
DIO12
X_WR
VCC3IO
X_RD
GNDK
VCCK
DIO0
DIO1
DIO2
DIO3
GNDK
VCCK
DIO4
DIO5
DIO6
DIO7
VCC3IO
GNDK
VCCK
DIO8
DIO9
GNDIO
DIO10
DIO11
GNDK
VCCK
4
3
2
1
REG_GND
VCCK_V18
C5
0.1uF/25V
VCCK_V18
C6
0.1uF/25V
REG_GND
VCCK_V18
C7
0.1uF/25V
REG_GND
VCCK_V18
C8
0.1uF/25V
REG_GND
VCCK_V18
C9
0.1uF/25V
REG_GND
VCCK_V18
C10
0.1uF/25V
REG_GND
LCD_D5
IO_GND
LCD_D4
LCD_D3
LCD_D2
VCCK_V18
CORE_GND
LCD_D1
VCC_3V3
LCD_D0
LCD_DCLK
LCD_DE
IO_GND
VCCK_V18
CORE_GND
LCD_HS
LCD_VS
DB17
VCC_3V3
DB16
VCCK_V18
DB15
DB14
DB13
DB12
VCC_3V3
VCC_3V3
C16
0.1uF/25V
TESTEN
0 ohm/0603
R13
IM5
IM4
IM3
IM2
IM1
IM0
18BIT
1
0
0
0
0 ohm/0603
0
0
R14
16BIT
0
0
0
9BIT
1
1
0
0
0
1
0
1
0
8BIT
0
1
0
0
1
1
18BIT
1
16BIT
0
0
0
1
0
0
0
0
1
0
1
9BIT
8BIT
1
1
0
1
1
0
0
1
0
1
1
1
TINT0
REG_GND
VCC_3V3
VCC_3V3
C20
0.1uF/25V
REG_GND
0 ohm/0603
R15
0 ohm/0603
C18
0.1uF/25V
C21
0.1uF/25V
FB1
REG_GND
BK2125HS102-T
FB2
OSC_GND
BK2125HS102-T
FB3
PLL_GND
BK2125HS102-T
FB4
CORE_GND
BK2125HS102-T
FB5
IO_GND
BK2125HS102-T
FB6
VCC33
C23
0.1uF/25V
VCC33
VCC33
U2
VDD
DGND
VCCK_V18
REG_3V3
C24
10uF/10V
1
2
3
VIN VOUT
GND
EN
BP
5
C25
10uF/10V
C26
(NC) 0.1uF/25V
4
3.0V LDO
IM5:
color depth a 0: 16-bits (656), 1: 18-bits (666)
IM4:
byte transfer order 0: LSB first, 1: MSB first
IM3 :
Always Low
IM2:
80/68 0: 80 MODE, 1: 68 MODE
IM1,IM0:
18,16,9,8 BIT BUS SELECTION
Date : 2008/01/07
C27
0.1uF/25V
OSC_GND
C19
0.1uF/25V
REG_GND
BK2125HS102-T
C22
10uF/10V
CORE_GND
OSC_V18
VCC_3V3
REG_GND
C28
0.1uF/25V
C29
0.1uF/25V
OSC_GND
REG_GND
1V8
U3
VDD
DGND
C30
10uF/10V
1
2
3
VIN VOUT
GND
EN
BP
(NC) 1.8V LDO
10
C15
0.1uF/25V
REG_GND
REG_GND
VCC33IN
TINT1
80 SERIES
68 SERIES
REG_GND
VCCK_V18
VCC_3V3
C17
0.1uF/25V
REG_GND
/WR
VCC_3V3
/RD
CORE_GND
VCCK_V18
DB0
DB1
DB2
DB3
CORE_GND
VCCK_V18
DB4
DB5
DB6
DB7
VCC_3V3
CORE_GND
VCCK_V18
DB8
DB9
IO_GND
DB10
DB11
CORE_GND
VCCK_V18
R12
REG_GND
U1
AMP506
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
C12
0.1uF/25V
VCCK_V18
C14
0.1uF/25V
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
2K/0603 RCA03-4D
VCCK_V18
C11
0.1uF/25V
REG_GND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RA1
8
7
6
5
REG_GND
VCCK_V18
C4
0.1uF/25V
/RESET
18BIT
IM0
IM1
IM4
IM5
REG_GND
VCCK_V18
C3
0.1uF/25V
CORE_GND
POWER_EN
LCD_D17
LCD_D16
LCD_D15
VCCK_V18
CORE_GND
LCD_D14
LCD_D13
VCC_3V3
LCD_D12
IO_GND
VCCK_V18
CORE_GND
LCD_D11
LCD_D10
LCD_D9
VCCK_V18
CORE_GND
LCD_D8
LCD_D7
VCC_3V3
LCD_D6
VCCK_V18
CORE_GND
JP1
IM2_68/80 2
VCCK_V18
C2
0.1uF/25V
5
4
C31
(NC) 0.1uF/25V
FSA506 Application Note
6
Jumper Setting
The user can select the MCU interface by change the Jumper & Resister Array.
Setting
JP1
RA1
RA2
RA3
RA4
Remark
Interface Type
80-18Bit interface
80-16Bit interface
80-9Bit interface
80-8Bit interface
68-18Bit interface
68-16Bit interface
68-9Bit interface
68-8Bit interface
Date : 2008/01/07
1,2 short
2,3 open
1,2 short
2,3 open
1,2 short
2,3 open
1,2 short
2,3 open
1,2 open
2,3 short
1,2 open
2,3 short
1,2 open
2,3 short
1,2 open
2,3 short
2K
OPEN OPEN OPEN
ohm
OPEN
2K
OPEN OPEN
ohm
OPEN OPEN
2K
OPEN
ohm
OPEN OPEN OPEN
2K
ohm
2K
OPEN OPEN OPEN
ohm
OPEN
2K
OPEN OPEN
ohm
OPEN OPEN
2K
OPEN
ohm
OPEN OPEN OPEN
2K
ohm
Default
11
FSA506 Application Note
7 Interface Protocol
7.1
18Bit-80/68-Write to Command Register
Date : 2008/01/07
12
FSA506 Application Note
7.2
18Bit-80/68-Write to Display RAM
/CS
80
mode
68
mode
/RD
/WR
E
R/W
RS
DB[17:0]
Note1
Display
RAM
Write Enable
0x000C1
Note2
Note3
Send
Data1
Send
Data2
Note4
Note5
Send
DataN
Display RAM
Write Disable
0x00080
Note1: DB[17:0] send 0x000C1 to Enable the Display RAM write.
Note2: DB[17:0] represent the writing Data1 to Display RAM
Note3: DB[17:0] represent the writing Data2 to Display RAM
Note4: DB[17:0] represent the writing DataN to Display RAM
Note5: DB[17:0] send 0x00080 to Disable the Display RAM write.
7.3
16Bit-80/68- Write to Command Register
/CS
80
mode
68
mode
/RD
/WR
E
R/W
RS
DB[15:8]
DB[7:0]
0x00
Note1
Note2
Note3
Note4
Note5
Register
address
Addr write
Setting
Register
Addr
Setting
Register
Addr+1
Setting
Register
Addr+N
Register
Write
Disable
0x80
Note1: DB[7:0] represent the the Register address Addr. DB[15:8] must be 0x00
Note2: DB[7:0] represent the the setting value of the Addr. DB[15:8] must be 0x00
Note3: DB[7:0] represent the the setting value of the Addr+1. DB[15:8] must be 0x00
Note4: DB[7:0] represent the the setting value of the Addr+N. DB[15:8] must be 0x00
Note5: DB[7:0] send 0x80 to Disable the Register write. DB[15:8] must be 0x00
Date : 2008/01/07
13
FSA506 Application Note
7.4
16Bit-80/68-Write to Display RAM
/CS
80
mode
68
mode
/RD
/WR
E
R/W
RS
DB[15:0]
Note1
Display
RAM
Write Enable
0x000C1
Note2
Send
Data1
Note3
Send
Data2
Note4
Note5
Send
DataN
Display RAM
Write Disable
0x00080
Note1: DB[15:0] send 0x000C1 to Enable the Display RAM write.
Note2: DB[15:0] represent the writing Data1 to Display RAM
Note3: DB[15:0] represent the writing Data2 to Display RAM
Note4: DB[15:0] represent the writing DataN to Display RAM
Note5: DB[15:0] send 0x00080 to Disable the Display RAM write.
Date : 2008/01/07
14
FSA506 Application Note
7.5
9Bit-80/68- Write to Command Register
/CS
80
mode
68
mode
/RD
/WR
E
R/W
RS
DB[8]
DB[7:0]
0x00
Note1
Note2
Note3
Note4
Note5
Register
address
Addr write
Setting
Register
Addr
Setting
Register
Addr+1
Setting
Register
Addr+N
Register
Write
Disable
0x80
Note1: DB[7:0] represent the the Register address Addr. DB[8] must be 0x00
Note2: DB[7:0] represent the the setting value of the Addr. DB[8] must be 0x00
Note3: DB[7:0] represent the the setting value of the Addr+1. DB[8] must be 0x00
Note4: DB[7:0] represent the the setting value of the Addr+N. DB[8] must be 0x00
Note5: DB[7:0] send 0x80 to Disable the Register write. DB[8] must be 0x00
7.6
9Bit-80/68-Write to Display RAM
/CS
80
mode
68
mode
/RD
/WR
E
R/W
RS
DB[8:0]
Note1
Display
RAM
Write Enable
0x000C1
Note2
Send
Data1
Note3
Send
Data2
Note4
Note5
Send
DataN
Display RAM
Write Disable
0x00080
Note1: DB[8:0] send 0x000C1 to Enable the Display RAM write.
Note2: DB[8:0] represent the writing Data1 to Display RAM
Note3: DB[8:0] represent the writing Data2 to Display RAM
Note4: DB[8:0] represent the writing DataN to Display RAM
Note5: DB[8:0] send 0x00080 to Disable the Display RAM write.
Date : 2008/01/07
15
FSA506 Application Note
7.7
8Bit-80/68- Write to Command Register
/CS
80
mode
68
mode
/RD
/WR
E
R/W
RS
DB[7:0]
Note1
Note2
Note3
Note4
Note5
Register
address
Addr write
Setting
Register
Addr
Setting
Register
Addr+1
Setting
Register
Addr+N
Register
Write
Disable
0x80
Note1: DB[7:0] represent the the Register address Addr.
Note2: DB[7:0] represent the the setting value of the Addr.
Note3: DB[7:0] represent the the setting value of the Addr+1.
Note4: DB[7:0] represent the the setting value of the Addr+N.
Note5: DB[7:0] send 0x80 to Disable the Register write.
Date : 2008/01/07
16
FSA506 Application Note
7.8
8Bit-80/68-Write to Display RAM
/CS
80
mode
68
mode
/RD
/WR
E
R/W
RS
DB[7:0]
Note1
Display
RAM
Write Enable
0x000C1
Note2
Send
Data1
Note3
Send
Data2
Note4
Note5
Send
DataN
Display RAM
Write Disable
0x00080
Note1: DB[7:0] send 0x000C1 to Enable the Display RAM write.
Note2: DB[7:0] represent the writing Data1 to Display RAM
Note3: DB[7:0] represent the writing Data2 to Display RAM
Note4: DB[7:0] represent the writing DataN to Display RAM
Note5: DB[7:0] send 0x00080 to Disable the Display RAM write.
Date : 2008/01/07
17
FSA506 Application Note
7.9
Data transfer order Setting
7.9.1 18 bit interface 262K color only (IM5: Pin 65K/262K =High)
DB 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
R5
DB
R4
R3
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
7.9.2 16 bit interface 65K color (IM5: Pin 65K/262K =Low)
15 14 13 12 11 10 9 8 7 6 5 4
R4
DB
R2
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B4
1
0
B3
B2
B1
B0
3
2
1
0
B3
B2
B1
B0
7.9.3 16 bit interface 262K color (IM5: Pin 65K/262K =High, IM4=Low)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
1st data
2nd data
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
B1
R5
B0
R4
7.9.4 9 bit interface 262K color only (IM5: Pin 65K/262K =High)
DB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1st data
X X X X X X X R5 R4 R3 R2 R1 R0 G5 G4 G3
2nd data
X X X X X X X G2 G1 G0 B5 B4 B3 B2 B1 B0
7.9.5 8 bit interface 65K color (IM5: Pin 65K/262K =Low)
DB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
st
1 data
X X X X X X X X R4 R3 R2 R1 R0 G5 G4 G3
2nd data
X X X X X X X X G2 G1 G0 B4 B3 B2 B1 B0
7.9.6 8 bit interface 262K color (IM5: Pin 65K/262K =High)
DB
15 14 13 12 11 10 9 8 7 6 5 4 3 2
1st data
X X X X X X X X
2nd data
X X X X X X X X R3 R2 R1 R0 G5 G4
3rd data
X X X X X X X X G1 G0 B5 B4 B3 B2
Date : 2008/01/07
1
0
R5
G3
B1
R4
G2
B0
18
FSA506 Application Note
8 Register Depiction
Register
Address
(Hex)
00
Description
Register
Address
(Hex)
01
Description
Register
Address
(Hex)
02
Description
Register
Address
(Hex)
03
Description
Register
Address
(Hex)
04
Description
Register
Address
(Hex)
05
Description
Register
Address
(Hex)
06
Description
Register
Address
(Hex)
07
Description
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of X-axis start position
00
set the horizontals start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of X-axis start position
00
set the horizontals start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of X-axis end position
01
set the horizontals end position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of X-axis end position
3F
set the horizontals end position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of Y-axis start position
00
set the vertical start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of Y-axis start position
00
Set the vertical start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of Y-axis end position
00
set the vertical end position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of Y-axis end position
EF
Set the vertical end position of display active region
To simplify the address control of display RAM access, the window area address
function
allows for writing data only within a window area of display RAM specified by
Date : 2008/01/07
19
FSA506 Application Note
registers REG[00]~REG[07] .
After writing data to the display RAM, the Address counter will be increased within
setting window address-range which is specified by
MIN X address (REG[0] & REG[1])
MAX X address (REG[2] & REG[3])
MIN Y address (REG[4] & REG[5])
MAX Y address (REG[6] & REG[7])
Therefore, data can be written consecutively without thinking the data address.
Date : 2008/01/07
20
FSA506 Application Note
Register
Address
(Hex)
08
Default
DB7 DB6 DB5 DB4
(Hex)
01
X
X
X
X
DB3
DB2
X
X
DB1
DB0
Remark
_PanelXSize
H_Byte[1:0]
Description Set the panel X size
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1
(Hex)
(Hex)
09
40
_PanelXSize L_Byte[7:0]
Description Set the panel X size
DB0
Remark
The register REG[08] and REG[09] is use to calculate the RAM address. If you
want to use the TFT as Landscape mode (320x240), the REG[08] & RGE[09 must
set to 320. If you want to use the TFT as Portrait mode (240x320), the REG[08] &
RGE[09] must set to 240.
Register
Address
(Hex)
Default
(Hex)
0A
00
DB7 DB6 DB5 DB4
X
X
X
X
DB3
X
DB2 DB1
DB0
[17:16] bits of
memory write start
address
Description Memory write start address
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[15:8] bits of memory write start address
0B
00
Description Memory write start address
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[7:0] bits of memory write start address
0C
00
Description Memory write start address
Date : 2008/01/07
Remark
Remark
Remark
21
FSA506 Application Note
Register
Address
(Hex)
0x10
Default
(Hex)
DB7
DB6
DB5 DB4
DB3
DB2
DB1 DB0 Remark
BUS_SEL
Blanking P/S_SEL
CLK_SEL
0x0D Bit_SWAP OUT_TEST
"0x10_Clk_sel[1:0]" : The TFT controller built-in 40Mhz PLL clock. These bits
are for select the TFT panel dot clock frequency.
00 : 20Mhz 01: 10Mhz 02: 5 Mhz
"0x10_ps_sel[2]" : The TFT controller support parallel and serial RGB
interface. These bits are for select the output timing.
0 : serial Panel 1: Parallel panel
"0x10_blanking_tmp[3]"
0 : OFF (blanking) 1: ON ( normal operation)
Description
"0x10_bus_sel[5:4]" : It only for serial Panel
00=R , 01=G , 10=B
"0x10_out_test[6]" : Self test
0 : normal operation 1: for test (don’t use for normal operation)
When set the bit to “1” , the Rout=(Reg 2a[6:0]) Gout=(Reg 2b[6:0])
Bout=(Reg 2c[6:0])
"0x10_bit_swap[7]" : 0-normal
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7
DB6
DB5 DB4 DB3
DB2 DB1 DB0 Remark
(Hex)
(Hex)
X
X
EVEN
_ODD
0x11
00
" Even line of serial panel data out sequence or data bus order of parallel
panel
000: RGB
001: RBG
010: GRB
011: GBR
100: BRG
101: BGR
Others: reserved
Description
Odd line of serial panel data out sequence
000: RGB
001: RBG
010: GRB
011: GBR
100: BRG
101: BGR
Others: reserved
Must Set to 0x05
Date : 2008/01/07
22
FSA506 Application Note
Register
Address
(Hex)
0x12
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00
Hsync_stH_Byte[3:0]
For TFT output timing adjust:
Description
Hsync start position H-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x13
00
Hsync_stL_Byte[7:0]
For TFT output timing adjust:
Description
Hsync start position L-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x14
00
Hsync_pwH_Byte[3:0]
For TFT output timing adjust:
Description
Hsync pulse width H-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x15
10
Hsync_pwL_Byte[7:0]
For TFT output timing adjust:
Description
Hsync pulse width L-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x16
00
Hact_stH_Byte[3:0]
For TFT output timing adjust:
Description
DE pulse start position H-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x17
38
Hact_stL_Byte[7:0]
For TFT output timing adjust:
Description
DE pulse start position L-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x18
01
Hact_pwH_Byte[3:0]
For TFT output timing adjust:
Description
DE pulse width H-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x19
40
Hact_pwL_Byte[7:0]
For TFT output timing adjust:
Description
DE pulse width L-Byte
Date : 2008/01/07
Remark
Remark
Remark
Remark
Remark
Remark
Remark
Remark
23
FSA506 Application Note
Register
Address
(Hex)
0x1A
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
01
HtotalH_Byte[3:0]
For TFT output timing adjust:
Description
Hsync total clocks H-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x1B
B8
HtotalL_Byte[7:0]
For TFT output timing adjust:
Description
Hsync total clocks H-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x1C
00
Vsync_stH_Byte[3:0]
For TFT output timing adjust:
Description
Vsync start position H-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x1D
00
Vsync_stL_Byte[7:0]
For TFT output timing adjust:
Description
Vsync start position L-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x1E
00
Vsync_pwH_Byte[3:0]
For TFT output timing adjust:
Description
Vsync pulse width H-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x1F
08
Vsync_pwL_Byte[7:0]
For TFT output timing adjust:
Description
Vsync pulse width L-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x20
00
Vact_stH_Byte[3:0]
For TFT output timing adjust:
Description
Vertical DE pulse start position H-Byte
Date : 2008/01/07
Remark
Remark
Remark
Remark
Remark
Remark
Remark
24
FSA506 Application Note
Register
Address
(Hex)
0x21
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
12
Vact_stL_Byte[7:0]
For TFT output timing adjust:
Description
Vertical DE pulse start position L-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x22
00
Vact_pwH_Byte[3:0]
For TFT output timing adjust:
Description
Vertical Active width H-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x23
F0
Vact_pwL_Byte[7:0]
For TFT output timing adjust:
Description
Vertical Active width H-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x24
01
VtotalH_Byte[3:0]
For TFT output timing adjust:
Description
Vertical total width H-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
0x25
09
VtotalL_Byte[7:0]
For TFT output timing adjust:
Description
Vertical total width L-Byte
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[17:16] bits of
memory read start
26
00
X
X
X
X
X
address
Description Memory read start address
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[15:8] bits of memory write start address
27
00
Description Memory read start address
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
[7:0] bits of memory write start address
28
00
Description Memory read start address
Date : 2008/01/07
Remark
Remark
Remark
Remark
Remark
Remark
Remark
Remark
25
FSA506 Application Note
Register
Address
(Hex)
29
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1
DB0
Remark
[7:1] Reversed
00
[0] Load output timing related setting (H sync., V sync. and DE) to take
Description
effect
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x2A
00
X
TestPatternRout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ;
Description
The Rout data equal to TestPatternRout[6:0]
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x2B
00
X
TestPatternGout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ;
Description
The Gout data equal to TestPatternGout[6:0]
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x2C
00
X
TestPatternBout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ;
Description
The Bout data equal to TestPatternBout[6:0]
If you set the " REG[0x10]_out_test[6]" : Self test =1 , the TFT controller will skip
the connect of the display RAM. The Output port will send the
REG[2A] ,REG[2B],REG[2C] data.
Date : 2008/01/07
26
FSA506 Application Note
Register
Address
(Hex)
Default
DB7 DB6 DB5 DB4 DB3
(Hex)
DB2
DB1 DB0 Remark
Rising/falling
_rotate
edge[2]
[1:0]
[3] Output pin X_DCON level control ; TFT Power ON/OFF control
0: TFT POWER circuit OFF
1: TFT POWER circuit ON
Rising/falling edge[2] :
0: The RGB out put data are on the Rising edge of the DCLK.
Description 1: The RGB out put data are on the Falling edge of the DCLK.
_rotate [1:0]:
00 : rotate 0 degree
01 : rotate90 degree
10 : rotate 270 degree
11 : rotate 180 degree
0x2D
00
Register
Address
(Hex)
Default
(Hex)
30
00
X
X
X
X
DB7 DB6 DB5 DB4
X
X
X
X
[3]
DB3
DB2 DB1 DB0
X
_H byte
H-Offset[3:0]
Description Set the Horizontal offset
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
31
00
_L byte H-Offset[7:0]
Description Set the Horizontal offset
Register
Address
(Hex)
Default
(Hex)
32
00
DB7 DB6 DB5 DB4
X
X
X
X
DB3
DB2 DB1 DB0
X
_H byte
V-Offset[3:0]
Description Set the Vertical offset
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
33
00
_L byte V-Offset[7:0]
Description Set the Vertical offset
Register
Address
(Hex)
34
Description
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1 DB0
Remark
Remark
Remark
Remark
Remark
_H byte
H-def[3:0]
[3:0] MSB of image horizontal physical resolution in memory
00
Date : 2008/01/07
[7:4] Reserved
27
FSA506 Application Note
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
35
40
_L byte H-def[7:0]
Description [7:0] LSB of image horizontal physical resolution in memory
Register
Address
(Hex)
36
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1 DB0
Remark
Remark
_H byte
V-def[3:0]
[3:0] MSB of image vertical physical resolution in memory
01
[7:4] Reserved
Description
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
37
E0
_L byte V-def[7:0]
Description [7:0] LSB of image vertical physical resolution in memory
Remark
The total RAM size is 640x240x18bit. The user can arrange the Horizontal ram
size by REG[34],REG[35] and the Vertical ram size by REG[36],REG[37].
EX: 320x480x18bit REG[34]=0x01 , REG[35]=0x40 , REG[36]=0x01 ,
REG[37]=0xE0
EX: 640x240x18bit. REG[34]=0x02 , REG[35]=0x80 , REG[36]=0x00 ,
REG[37]=0xF0
9 Reference Initial code :
9.1
8bit-80 interface mode , 65K color , Panel:320xRGBx240 , LandScape
void main(void)
{
Initial_FSA506 ( );
Full_386SCR(0xf800);
Full_386SCR(0x07e0);
Full_386SCR(0x001f);
}
Date : 2008/01/07
28
FSA506 Application Note
void FSA506_80Mode_Command_SendAddress(BYTE Addr)
{
SET_nRD;
// /RD=1
CLR_RS;
// RS=0
CLR_CS1;
// /CS=0
CLR_nWRL;
// /WR=0
DB8OUT(Addr);
// Data Bus OUT
SET_nWRL;
///WR=1
SET_RS;
// RS=1
SET_CS1;
/
// CS=1
}
void FSA506_80Mode_Command_SendData(BYTE Data)
{
SET_nRD;
SET_RS;
CLR_CS1;
CLR_nWRL;
DB8OUT(Data);
SET_nWRL;
SET_RS;
SET_CS1;
}
void FSA506_Command_Write(uint8 CMD_Address,uint8 CMD_Value)
{
FSA506_80Mode_Command_SendAddress(CMD_Address);
FSA506_80Mode_Command_SendData(CMD_Value);
}
void FSA506_80Mode_16Bit_Memory_SendData(uint16 Dat16bit)
{
SET_nRD;
SET_RS;
CLR_CS1;
Date : 2008/01/07
29
FSA506 Application Note
CLR_nWRL;
DB8OUT(Dat16bit>>8);
SET_nWRL;
// Low to High Latch Data to FSA506 Buffer
SET_CS1;
SET_nRD;
SET_RS;
CLR_CS1;
CLR_nWRL;
DB8OUT(Dat16bit);
SET_nWRL;
// Low to High Latch Data to FSA506 Buffer
SET_CS1;
}
void Initial_FSA506(void)
{
FSA506_Command_Write(0x40,0x12);
/*[7:6] Reserved
[5] PLL control pins to select out frequency range
0: 20MHz ~ 100MHz 1: 100MHz ~ 300MHz
[4] Reserved [3] Reserved
[2:1] Output Driving Capability
00: 4mA 01: 8mA 10: 12mA 11: 16mA
[0] Output slew rate
0: Fast 1: Slow
*/
FSA506_Command_Write(0x41,0x01);
FSA506_Command_Write(0x42,0x01);
//Set PLL=40Mhz * (0x42) / (0x41)
//0x41 [7:6] Reserved [5:0] PLL Programmable
pre-divider, 6bit(1~63)
//0x42 [7:6] Reserved [5:0] PLL Programmable loop
divider, 6bit(1~63)
FSA506_Command_Write(0x00,0x00);
FSA506_Command_Write(0x01,0x00);
// MSB of horizontal start coordinate value
// LSB of horizontal start coordinate value
FSA506_Command_Write(0x02,0x01);
// MSB of horizontal end coordinate value
FSA506_Command_Write(0x03,0x3F);
// LSB of horizontal end coordinate value
FSA506_Command_Write(0x04,0x00);
// MSB of vertical start coordinate value
FSA506_Command_Write(0x05,0x00);
FSA506_Command_Write(0x06,0x01);
Date : 2008/01/07
// LSB of vertical start coordinate value
// MSB of vertical end coordinate value
30
FSA506 Application Note
FSA506_Command_Write(0x07,0x3F);
// LSB of vertical end coordinate value
FSA506_Command_Write(0x08,0x01);
// MSB of input image horizontal resolution
FSA506_Command_Write(0x09,0x40);
// LSB of input image horizontal resolution
FSA506_Command_Write(0x0a,0x00);
//[17:16] bits of memory write start address
FSA506_Command_Write(0x0b,0x00);
//[15:8] bits of memory write start address
FSA506_Command_Write(0x0c,0x00);
//[7:0] bits of memory write start address
FSA506_Command_Write(0x10,0x0D); /*[7] Output data bits swap
0: Normal 1:Swap
[6] Output test mode enable 0: disable 1: enable
[5:4] Serial mode data out bus selection
00: X_ODATA17 ~ X_ODATA12 active ,others are set to 0
01: X_ODATA11 ~ X_ODATA06 active ,others are set to 0
10: X_ODATA05 ~ X_ODATA00 active ,others are set to 0
11: reserved
[3] Output data blanking
0: set output data to 0
1: Normal display
[2] Parallel or serial mode selection
0: serial data out
1: parallel data output
[1:0] Output clock selection
00: system clock divided by 2
01: system clock divided by 4
10: system clock divided by 8
11: reserved */
FSA506_Command_Write(0x11,0x05);
/*[7] Reserved
[6:4] Even line of serial panel data out sequence or data bus order of parallel panel
000: RGB
001: RBG
010: GRB
011: GBR 100: BRG 101: BGR
Others: reserved
[3] Reversed
[2:0] Odd line of serial panel data out sequence
000: RGB
001: RBG
Others: reserved
010: GRB
011: GBR 100: BRG
101: BGR
*/
FSA506_Command_Write(0x12,0x00);
// [3:0] MSB of output H sync. pulse start position
FSA506_Command_Write(0x13,0x00);
//[7:0] LSB of output H sync. pulse start position
FSA506_Command_Write(0x14,0x00);
// [3:0] MSB of output H sync. pulse width
FSA506_Command_Write(0x15,0x10);
//[7:0] LSB of output H sync. pulse width
FSA506_Command_Write(0x16,0x00);
//[3:0] MSB of output DE horizontal start position
Date : 2008/01/07
31
FSA506 Application Note
FSA506_Command_Write(0x17,0x38);
//[7:0] LSB of output DE horizontal start position
FSA506_Command_Write(0x18,0x01); //[3:0] MSB of output DE horizontal active region in pixel
FSA506_Command_Write(0x19,0x40); //[7:0] LSB of output DE horizontal active region in pixel
FSA506_Command_Write(0x1a,0x01); //[7:4] Reserved [3:0] MSB of output H total in pixel
FSA506_Command_Write(0x1b,0xb8); //[7:0] LSB of output H total in pixel
FSA506_Command_Write(0x1c,0x00); //[3:0] MSB of output V sync. pulse start position
FSA506_Command_Write(0x1d,0x00); //[7:0] of output V sync. pulse start position
FSA506_Command_Write(0x1e,0x00); //[7:4] Reserved [3:0] MSB of output V sync. pulse width
FSA506_Command_Write(0x1f,0x08);
//[7:0] LSB of output V sync. pulse width
FSA506_Command_Write(0x20,0x00);
// [3:0] MSB of output DE vertical start position
FSA506_Command_Write(0x21,0x12);
//[7:0] LSB of output DE vertical start position
FSA506_Command_Write(0x22,0x00);
// [3:0] MSB of output DE vertical active region in line
FSA506_Command_Write(0x23,0xf0);
//[7:0] LSB of output DE vertical active region in line
FSA506_Command_Write(0x24,0x01);
//[7:4] Reversed [3:0] MSB of output V total in line
FSA506_Command_Write(0x25,0x09);
//[7:0] LSB of output V total in line
FSA506_Command_Write(0x26,0x00);
// [17:16] bits of memory read start address
FSA506_Command_Write(0x27,0x00); //[7:0] [15:8] bits of memory read start address
FSA506_Command_Write(0x28,0x00); //[7:0] [7:0] bits of memory read start address
FSA506_Command_Write(0x29,0x01);
//[7:1] Reversed [0] Load output timing related setting (H sync., V sync. and DE) to take effect
FSA506_Command_Write(0x2d,0x08);
/* [7:4] Reserved
[3] Output pin X_DCON level control
[2] Output clock inversion
0: Normal 1: Inverse
[1:0] Image rotate
00: 0° 01: 90° 10: 270° 11: 180°
*/
FSA506_Command_Write(0x30,0x00); //[7:4] Reserved [3:0] MSB of image horizontal shift value
FSA506_Command_Write(0x31,0x00); //[7:0] LSB of image horizontal shift value
FSA506_Command_Write(0x32,0x00); //[7:4] Reserved [3:0] MSB of image vertical shift value
FSA506_Command_Write(0x33,0x00); //[7:0] LSB of image vertical shift value
FSA506_Command_Write(0x34,0x01);
// [3:0] MSB of image horizontal physical Resolution in memory
FSA506_Command_Write(0x35,0x40);
//[7:0] LSB of image horizontal physical resolution in memory
FSA506_Command_Write(0x36,0x01);
//[7:4] Reserved [3:0] MSB of image vertical physical resolution in memory
FSA506_Command_Write(0x37,0xe0);
Date : 2008/01/07
32
FSA506 Application Note
//[7:0] LSB of image vertical physical resolution in memory
}
void FSA506_WindowSet(uint16 S_X,uint16 S_Y,uint16 E_X,uint16 E_Y)
{
FSA506_80Mode_Command_SendAddress(0x00);
FSA506_80Mode_Command_SendData((S_X)>>8);
FSA506_80Mode_Command_SendData(S_X);
FSA506_80Mode_Command_SendData((E_X-1)>>8);
FSA506_80Mode_Command_SendData(E_X-1);
FSA506_80Mode_Command_SendData(S_Y>>8);
FSA506_80Mode_Command_SendData(S_Y);
FSA506_80Mode_Command_SendData((E_Y-1)>>8);
FSA506_80Mode_Command_SendData(E_Y-1);
}
void Full_386SCR(uint16 Dat16bit)
{
int32 k,l;
FSA506_WindowSet(0,0,Resolution_X,Resolution_Y);
FSA506_80Mode_Command_SendAddress(0xc1); //_DisplayRAM_WriteEnable_
for(k=0;k<240*2;k++)
{
for(l=0;l<320;l++)
{
FSA506_80Mode_16Bit_Memory_SendData(Dat16bit);
}
}
FSA506_80Mode_Command_SendAddress(0x80); // DisplayRAM_WriteDisable _
}
Date : 2008/01/07
33
FSA506 Application Note
9.2
8bit-80 interface mode , 65K color , Panel:320xRGBx240 , Portrait
void Initial_FSA506_90(void)
{
FSA506_Command_Write(0x40,0x12);
/*[7:6] Reserved
[5] PLL control pins to select out frequency range
0: 20MHz ~ 100MHz 1: 100MHz ~ 300MHz
[4] Reserved [3] Reserved
[2:1] Output Driving Capability
00: 4mA 01: 8mA 10: 12mA 11: 16mA
[0] Output slew rate
0: Fast 1: Slow
*/
FSA506_Command_Write(0x41,0x01);
//Set PLL=40Mhz * (0x42) / (0x41)
FSA506_Command_Write(0x42,0x01);
//0x41 [7:6] Reserved [5:0] PLL Programmable pre-divider, 6bit(1~63)
//0x42 [7:6] Reserved [5:0] PLL Programmable loop divider, 6bit(1~63)
FSA506_Command_Write(0x00,0x00);
// MSB of horizontal start coordinate value
FSA506_Command_Write(0x01,0x00);
// LSB of horizontal start coordinate value
FSA506_Command_Write(0x02,0x01);
// MSB of horizontal end coordinate value
FSA506_Command_Write(0x03,0x3F);
// LSB of horizontal end coordinate value
FSA506_Command_Write(0x04,0x00);
// MSB of vertical start coordinate value
FSA506_Command_Write(0x05,0x00);
// LSB of vertical start coordinate value
FSA506_Command_Write(0x06,0x01);
// MSB of vertical end coordinate value
FSA506_Command_Write(0x07,0x3F);
// LSB of vertical end coordinate value
FSA506_Command_Write(0x08,0x00);
// MSB of input image horizontal resolution
FSA506_Command_Write(0x09,0xf0);
// LSB of input image horizontal resolution Portrait X=240
FSA506_Command_Write(0x0a,0x00);
//[17:16] bits of memory write start address
FSA506_Command_Write(0x0b,0x00);
//[15:8] bits of memory write start address
FSA506_Command_Write(0x0c,0x00);
//[7:0] bits of memory write start address
FSA506_Command_Write(0x10,0x0D);
Date : 2008/01/07
34
FSA506 Application Note
/*[7] Output data bits swap
0: Normal 1:Swap
[6] Output test mode enable 0: disable 1: enable
[5:4] Serial mode data out bus selection
00: X_ODATA17 ~ X_ODATA12 active , others are set to zero
01: X_ODATA11 ~ X_ODATA06 active , others are set to zero
10: X_ODATA05 ~ X_ODATA00 active , others are set to zero
11: reserved
[3] Output data blanking
0: set output data to 0
1: Normal display
[2] Parallel or serial mode selection
0: serial data out
1: parallel data output[7:0] bits of memory write start address
[1:0] Output clock selection
00: system clock divided by 2
01: system clock divided by 4
10: system clock divided by 8
11: reserved */
FSA506_Command_Write(0x11,0x05);
/*[7] Reserved
[6:4] Even line of serial panel data out sequence or data bus order of parallel panel
000: RGB
001: RBG
010: GRB
011: GBR
100: BRG
101: BGR
Others: reserved
[3] Reversed
[2:0] Odd line of serial panel data out sequence
000: RGB
001: RBG
010: GRB
011: GBR
100: BRG
101: BGR
Others: reserved
*/
FSA506_Command_Write(0x12,0x00);
//[7:4] Reserved [3:0] MSB of output H sync. pulse start position
FSA506_Command_Write(0x13,0x00); //[7:0] LSB of output H sync. pulse start position
Date : 2008/01/07
35
FSA506 Application Note
FSA506_Command_Write(0x14,0x00); //[7:4] Reserved [3:0] MSB of output H sync. pulse width
FSA506_Command_Write(0x15,0x10);
//[7:0] LSB of output H sync. pulse width
FSA506_Command_Write(0x16,0x00);
//[7:4] Reserved [3:0] MSB of output DE horizontal start position
FSA506_Command_Write(0x17,0x38);
//[7:0] LSB of output DE horizontal start position
FSA506_Command_Write(0x18,0x01);
//[7:4] Reserved [3:0] MSB of output DE horizontal active region in pixel
FSA506_Command_Write(0x19,0x40);
//[7:0] LSB of output DE horizontal active region in pixel
FSA506_Command_Write(0x1a,0x01);
//[7:4] Reserved [3:0] MSB of output H total in pixel
FSA506_Command_Write(0x1b,0xb8);
//[7:0] LSB of output H total in pixel
FSA506_Command_Write(0x1c,0x00);
//[7:4] Reserved [3:0] MSB of output V sync. pulse start position
FSA506_Command_Write(0x1d,0x00);
//[7:0] of output V sync. pulse start position
FSA506_Command_Write(0x1e,0x00);
//[7:4] Reserved [3:0] MSB of output V sync. pulse
width
FSA506_Command_Write(0x1f,0x08);
//[7:0] LSB of output V sync. pulse width
FSA506_Command_Write(0x20,0x00);
//[7:4] Reserved [3:0] MSB of output DE vertical start position
FSA506_Command_Write(0x21,0x12);
//[7:0] LSB of output DE vertical start position
FSA506_Command_Write(0x22,0x00);
//[7:4] Reserved [3:0] MSB of output DE vertical
active region in line
FSA506_Command_Write(0x23,0xf0);
//[7:0] LSB of output DE vertical active region in line
FSA506_Command_Write(0x24,0x01);
//[7:4] Reversed [3:0] MSB of output V total in line
FSA506_Command_Write(0x25,0x09);
//[7:0] LSB of output V total in line
FSA506_Command_Write(0x26,0x00);
//[7:2] Reserved [1:0] [17:16] bits of memory read start address
FSA506_Command_Write(0x27,0x00);
//[7:0] [15:8] bits of memory read start address
FSA506_Command_Write(0x28,0x00);
//[7:0] [7:0] bits of memory read start address
FSA506_Command_Write(0x29,0x01);
//[7:1] Reversed [0] Load output timing related setting (H sync., V sync. and DE) to take effect
FSA506_Command_Write(0x2d,0x09);
/* [7:4] Reserved
[3] Output pin X_DCON level control
Date : 2008/01/07
36
FSA506 Application Note
[2] Output clock inversion
0: Normal 1: Inverse
[1:0] Image rotate
00: 0° 01: 90° 10: 270° 11: 180°
*/
FSA506_Command_Write(0x30,0x00); //[7:4] Reserved [3:0] MSB of image horizontal shift value
FSA506_Command_Write(0x31,0x00); //[7:0] LSB of image horizontal shift value
FSA506_Command_Write(0x32,0x00); //[7:4] Reserved [3:0] MSB of image vertical shift value
FSA506_Command_Write(0x33,0x00); //[7:0] LSB of image vertical shift value
FSA506_Command_Write(0x34,0x00);
//[7:4] Reserved [3:0] MSB of image horizontal physical resolution in memory
FSA506_Command_Write(0x35,0xf0);
//[7:0] LSB of image horizontal physical resolution in memory
FSA506_Command_Write(0x36,0x02);
//[7:4] Reserved [3:0] MSB of image vertical physical resolution in memory
FSA506_Command_Write(0x37,0x80);
//[7:0] LSB of image vertical physical resolution in memory
}
Date : 2008/01/07
37
FSA506 Application Note
The TFT LCD controller default value is for 320xRGBx240 already. So we can
start to write our data in a few steps:
Target: To write a 640x240 data to Display RAM and scroll the display data by
change the Horizontal offset register.
9.3 Step 1: Make sure the interface Protocol.
9.4 Step 2: Define the Horizontal ram seize = 640 and Vertical ram size =240
640x240x18bit. REG[34]=0x02 , REG[35]=0x80 , REG[36]=0x00 ,
REG[37]=0xF0
9.5 Step 3: Define the Panel X Size = 320
REG[8]=0x01 , REG[9]=0x40
9.6 Step4: Define the Write window. Start=(0,0) End=(619,239)
REG[0]=0x00 , REG[1]=0x00 , REG[2]=0x02 , REG[3]=0x6B , // Start X , End
X
REG[4]=0x00 , REG[5]=0x00 , REG[6]=0x00 , REG[7]=0xEF , // Star Y ,End Y
Date : 2008/01/07
38
FSA506 Application Note
9.7 Step5: Write the 640x240x18 bit data consecutively
9.8 Step6: The display will show the following image.
9.9 Step7: Change the Horizontal offset to switch or scroll the display data.
Set the Horizontal offset = 160 , REG[30]=00 REG[31]=A0 . You will see
Date : 2008/01/07
39
FSA506 Application Note
9.10 Step8: Change the Horizontal offset to switch or scroll the display data.
Set the Horizontal offset = 320 , REG[30]=01 REG[31]=40 . You will see
Date : 2008/01/07
40