R2J20701NP
Peak Current Mode Synchronous Buck Controller
with Power MOS FETs
REJ03G1459-0400
Rev.4.00
Jun 30, 2008
Description
This all-in-one SiP for POL (point-of-load) applications is a multi-chip module incorporating a high-side MOS FET,
low-side MOS FET, and PWM controller in a single QFN package. The on and off timing of the power MOS FET is
optimized by the built-in driver circuit, making this device suitable for large-current high-efficiency buck converters.
In a simple peak-current mode topology, stable operation is obtained in a closed power loop, and a fast converter is
easily realized with the addition of simple components. Furthermore, the same topology can be applied to realize
converters for parallel synchronized operation with current sharing, and two-phase operation.
The package also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external
SBD for this purpose.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Three chips in one package for high-efficiency and space saving
Large average output current (35 A)
Wide input voltage range: 8 to 14 V
0.6 V reference voltage accurate to within 1%
Wide programmable switching frequency: 200 kHz to 1 MHz
Fast response by peak-current-mode topology.
Simple current sharing (up to five modules in parallel)
Two-phase operation in parallel operation
Built-in SBD for boot strapping
On/off control
Hiccup operation under over load condition
Tracking function
Thin small package: 56-pin QFN (8 mm × 8 mm)
Pb-free
Applications
•
•
•
•
Network equipment
Telecommunications equipment
Servers
POL modules
Typical Characteristic Curve
Efficiency (%)
95
90
VIN = 12 V
VOUT = 1.8 V
L = 440 nH
CO = 600 µF
Frequency = 500 kHz
No airflow
Ta = 27°C
85
80
75
0
5
10
15
20
Iout (A)
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 1 of 27
25
30
35
R2J20701NP
Application Circuit Example
REG5
VIN
BOOT
VCIN
DRV5
REG5
SYNC
ON/OFF
CT
IREF
VIN (8 V to 14 V)
VOUT (1.8 V)
SW
TRK-SS
Controller Chip
PGND
CS
SGND
RAMP
EO
Ishare
FB
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REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 3 of 27
VOUT
TRK-SS
FB
REG5
EO
SYNC
CT
IREF
Ishare
50 k
50 k
ON/OFF
REG GOOD
OCP
REG5
Q
Q
R
S
0.1 V
Current
sense
comparator
50 ns
REG GOOD
Supervisor
RAMP
Max. Duty
RES
RES
Max. Duty
ON/OFF
Pulse generator
Error Amp.
SGND
0.6 V (1%)
(Bi-lateral)
OSC
Reference
current
generator
ON/OFF
CS
490 µA
BOOT
UVLO
SBD
(1024 pulses blank)
Gate drive
logic
circuit
OCP comparator
1.5 V
OCP
hiccup
control
OCP
PWM
ON/OFF
REG GOOD
5.25 V (4%)
Regulator
DRV5
Idh
18500
55 ns
Blanking
Active
current
sensing
5 V (4%)
Regulator
REG5
DRV5
VCIN
Idh
PGND
SW
VOUT
8 V to 14 V
VIN
R2J20701NP
Block Diagram
R2J20701NP
VIN
VIN
VIN
VIN
VIN
SW
BOOT
VCIN
SGND
REG5
IREF
EO
Ishare
FB
Pin Arrangement
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VIN 15
56
TRK-SS
VIN 16
55
CT
54
RAMP
VIN 18
53
CS
VIN 19
52
SGND
VIN 20
51
DRV5
SW 21
50
ON/OFF
PGND 22
49
SYNC
PGND 23
48
SW
47
SW
PGND 25
46
SW
PGND 26
45
SW
PGND 27
44
SW
PGND 28
43
SW
VIN 17
VIN
SGND
PGND 24
PGND
PGND
PGND
37
38
39
40
41
42
SW
PGND
36
SW
PGND
35
SW
34
PGND
33
PGND
32
PGND
31
PGND
30
PGND
29
PGND
SW
(Top view)
Package: 56-pin QFN (8 mm × 8 mm, 0.5-mm pin pitch)
Note: All die-pads (three pads in total) should be soldered to PCB.
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
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R2J20701NP
Pin Description
Pin Name
Pin No.
VIN
10 to 20
SW
9, 21, 40 to 48
Description
Remarks
Input voltage for the buck converter.
Switching node. Connect a choke coil between the
SW pin and dc output node of the converter.
PGND
22 to 39
Ground of the power stage.
Should be externally connected to
SGND.
SGND
6, 52
Ground of the IC chip.
Should be externally connected to
PGND.
VCIN
7
Input voltage for the control circuit.
Should be externally connected to VIN.
BOOT
8
Bootstrap voltage pin. A bootstrap capacitor should
be connected between the BOOT and SW pin.
To be supplied +5 V through the
internal SBD.
REG5
5
+5 V logic power-supply output.
Requires decoupling from the GND
plane by a capacitance 0.1 µF.
ON/OFF
50
Signal disable pin.
Disabled when ON/OFF pin is in the
low state.
IREF
4
Reference current generator for the IC.
Should be connected via 27 kΩ to the
SGND pin.
CT
55
Timing capacitor pin for the oscillator. This pin has a
select function for operation in slave mode.
If the pin voltage is <1 V or >4 V, the IC
operates in slave mode.
SYNC
49
I/O pin for synchronous operation.
TRK-SS
56
Start-up timing control input.
FB
1
Feedback voltage input for the closed loop.
EO
3
Error amplifier output pin.
Requires connection to an RC circuit
for loop compensation.
Ishare
2
For current-sharing bus.
Simply connect the Ishare pins of all
devices to get balanced current.
RAMP
54
RAMP signal input pin for peak current mode PWM
control.
CS
53
Current output pin of active current sensing circuit.
Appropriate resistance is required
between CS and the GND plane.
DRV5
51
+5.25 V generator output for driving power MOS
FETs.
Requires decoupling from the GND
plane by a capacitance from 0.1 µF to
1.0 µF.
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R2J20701NP
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Power dissipation
ON/OFF pin voltage
SYNC pin voltage
Voltage on other pins
REG5 current
Ishare current
TRK-SS dc current
IREF current
EO sink current
Pt(25)
Pt(100)
Iout
Vin (dc), Vcin (dc)
Vin (ac), Vcin (ac)
Vsw (dc)
Vsw (ac)
Vboot (dc)
Vboot (ac)
Von/off
Vsync
Vic
Ireg5
Ishare
Itrk
Iref
Ieo
Operating junction temperature
Storage temperature
Tj-opr
Tstg
Average output current
Input voltage
Switch node voltage
BOOT pin voltage
Notes: 1.
2.
3.
4.
Rating
25
8
35
–0.3 to +16
20
16
20
22
25
–0.3 to VIN
–0.3 to +5.5
–0.3 to (REG5 + 0.3)
–10 to 0
–500 to 0
0 to 1
–120 to 0
0 to 2
Unit
W
–40 to +150
–55 to +150
°C
°C
A
V
V
V
V
V
V
mA
µA
mA
µA
mA
Pt(25) represents a PCB temperature of 25°C, and Pt(100) represents 100°C.
Rated voltages are relative to voltages on the SGND and PGND pins.
For rated current, (+) indicates inflow to the chip and (–) indicates outflow.
Ratings for which “ac” is indicated are limited to within 100 ns.
Safe Operating Area
Average Output Current (A)
40
35
30
25
20
15
10
VIN = 12 V
VOUT = 1.3 V
5
0
0
25
50
75
100
125
PCB Temperature (°C)
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
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150
175
Note
1
1
2
2, 4
2
2, 4
2
2, 4
2
2
2
3
3
3
3
3
R2J20701NP
Electrical Characteristics
(Ta = 25°C, VIN = VCIN = 12 V, unless otherwise specified)
Supply
5-V
regulator
5.25-V
regulator
Remote
On/off
Reference
current
generator
Oscillator
SYNC and
pulse
generator
Error
amplifier
Item
VIN start threshold
VIN shutdown threshold
UVLO hysteresis
Input bias current
Symbol
VH
VL
dUVL
Iin
Min
6.8
6.45
—
36
Typ
7.2
6.85
0.35 *1
73
Max
7.6
7.25
—
110
Unit
V
V
V
mA
Input shutdown current
Isd
3.0
4.5
6.0
mA
CT = 68 pF,
Duty cycle = 50%
On/off = 0 V
Output voltage
Line regulation
Vreg
Vreg-line
4.8
–5
5.0
0
5.2
+5
V
mV
VIN = 10 to 16 V
Load regulation
Output voltage
Vreg-load
Vdrv
–8
5.04
–3
5.25
+2
5.46
mV
V
Disable threshold
Enable threshold
Voff
Von
1.0
2.0
1.3
2.5
1.6
3.0
V
V
Input current
IREF pin voltage
Ion/off
VIref
0.5
2.6
2.0
2.7
5.0
2.8
µA
V
Von/off = 1 V
Riref = 27 kΩ
CT oscillating frequency
SW switching frequency
CT higher trip voltage
CT lower trip voltage
CT source current
CT sink current
Fct
Fsw
Vhct
Vlct
Ict-src
Ict-snk
—
418
—
—
–170
150
930 *1
465
3 *1
2 *1
–160
160
—
512
—
—
–150
170
kHz
kHz
V
V
µA
µA
CT = 68 pF
CT = 68 pF
CT = 68 pF
CT = 68 pF
CT = 1.5 V
CT = 3.5 V
CT threshold for twophase operation
Vct-two
3.6
4.0
4.4
V
CT threshold for
synchronous operation
SYNC frequency
SYNC high voltage
SYNC low voltage
SYNC input threshold
Vct-one
0.8
1.0
1.2
V
Fsync
Vh-sync
Vl-sync
Vsync
418
4.0
0
1.0
465
5.0
—
2.0
512
—
1.0
3.0
kHz
V
V
V
CT = 68 pF
Rsync = 51 kΩ to GND
Rsync = 51 kΩ to REG5
CT = 0 V or 5 V
Feedback voltage
Input bias current
Output source current
Vfb
Ifb
Io-src
594
–0.1
150
600
0
200
606
+0.1
250
mV
µA
µA
TRK-SS = 1 V
FB = 0.6 V
EO = 4 V, FB = 0 V
Output sink transient
current
Voltage gain
Band width
Io-snk
5.0
10.6
19.0
mA
EO = 1 V, FB = 1 V
Av
BW
—
—
80 *1
15 *1
—
—
dB
MHz
Rshare
70
100
130
kΩ
Resistance connected to
the Ishare pin
Note:
1. These are reference values for design and have not been 100% tested in production.
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 7 of 27
Test Conditions
Ireg = 0 to 10 mA
EO = 0 V. Ishare = 1 V
R2J20701NP
(Ta = 25°C, VIN = VCIN = 12 V, unless otherwise specified)
Current
sense
Note:
Item
CS current ratio
Symbol
Idh/Ics
Min
—
Typ
18500 *1
Leading edge blanking
time
Max
—
—
Unit
—
ns
TLD
—
55 *
CS comparator delay to
output
Td-cs
—
50 *
—
ns
OCP comparator
threshold on CS pin
Hiccup interval
RAMP offset voltage
Vocp
1.43
1.5
1.57
V
Tocp
Vramp-dc
1.98
77
2.20
92
—
490 *
2.42
107
—
ms
mV
µA
CS offset current
Ics-dc
1
1
1
1. These are reference values for design and have not been 100% tested in production.
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
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Test Conditions
CT = 68 pF
CS = 0 V
R2J20701NP
Description of Operation
Peak Current Control
The control IC operates in a current-programmed control mode, in which the output of the converter is controlled by the
choice of the peak current from the high-side MOS FET. The current from this MOS FET is sensed by an active
current-sensing circuit (ACS), the output current of which is 1/18500 (54 ppm) of the MOS FET current. The ACS
current is then converted to a certain voltage by the external resistor on the CS pin. The CS voltage is fed to the RAMP
pin by an external connection, then compared with the current-control signal which is determined from the error
amplifier output voltage (EO) via an NPN transistor and resistor network.
To start with, the RES pulse from the pulse generator resets a latch, then the high-side MOS FET is turned on. The
latch output (Q bar) is toggled when the voltage on RAMP reaches the level of the current-control signal on EO, the
high-side MOS FET is turned off, and the low-side MOS FET is turned off after a certain dead-time interval. The IC
remains in this state until the arrival of the next RES pulse.
Since current information is used in the control loop, loop compensation design for the converter is simple and easy.
Maximum Duty-Cycle Limitation
If the current-sense comparator output is not toggled 50-ns prior to the arrival of the next RES pulse, an internal
maximum duty pulse is generated and forces toggling of the SR latch. So, the duty cycle of the high-side MOS FET is
limited by the maximum duty period.
The maximum duty period of the high-side MOS FET depends on its switching frequency.
Maximum duty period = 1 – 50 ns × Fsw
OCP Hiccup Operation
Once the voltage of CS exceeds 1.5 V, OCP hiccup circuit disables switching operation of the IC and MOS FETs.
Internal circuitry also pulls the TRK-SS pin down to SGND. The IC is turned off for a period of 1024 RES pulses; after
this has elapsed, switching operation of the IC is restarted from the soft-start state.
UVLO and On/off Control
When VIN (=Vcin) is below the start-up voltage, that is, is in the UVLO condition, functioning of the IC is disabled.
The oscillator is turned off, both high- and low-side MOS FETs are turned off, and the TRK-SS pin is pulled down.
Furthermore, if the ON/OFF pin is in the low state or left open, functioning of the IC is disabled and both MOS FETs
are turned off.
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R2J20701NP
Oscillator and Pulse Generator
The frequency of oscillation is set by the value of the external capacitor connected to the CT pin. This frequency is
twice as high as the actual switching frequency. The frequencies are determined by the following equations:
Oscillator frequency; Fct = 160 µA / {2 × (CT(F) + 18 pF) × 1 V}
Switching frequency; Fsw = 0.5 × Fct
(in Hz)
(Hz)
When the chip is operating in standalone mode or as the master chip for parallel operation, it requires a capacitor on the
CT pin. In this case, the SYNC pin outputs a synchronization signal with a frequency of Fsw.
In operation as a slave chip, the CT pin must be connected to SGND or REG5, after which it acts as an input pin for the
synchronized operation by external clock. The internal circuit is synchronized its rising edge when CT<0.8 V, falling
edge when CT>4.4 V. In two-phase operation in parallel configuration, the CT pin should be at a voltage over 4.4 V.
Mode
Item
Standalone
Master
Slave –0°
Slave –180°
CT pin
SYNC pin
Synchronizing trigger
Has a cap.
Output mode
—
Has a cap.
Output mode
—
< 0.8 V
Input mode
Rising
> 4.4 V
Input mode
Falling
The internal RES pulse and maximum duty-cycle-control pulses are produced from the signal at half the oscillator
frequency in standalone and master operating modes. In slave mode, internal pulses are produced from the externally
supplied input signal on the SYNC pin.
Current Sharing
It is easy to obtain balanced-current operation in a parallel configuration due to the application of peak current control.
To obtain current-sharing operation, simply tie the buffered error-amplifier outputs of all of the devices (Ishare pins)
together.
No more than five devices can operate in parallel.
Soft Start
Both simple soft starting and tracking start-up can be realized with the setup of the TRK-SS pin provided for soft-starts.
The error amplifier has three inputs, two of which are designed to give priority to low-level non-inverting inputs for the
amplifier. All that is required to realize soft-start operation is to simply attach an RC charging circuit to the TRK-SS
pin.
The soft-start period is determined by the following equation, with C and R as the values for the RC charging circuit
attached to the TRK-SS pin.
Tss = –C · R · Ln (1 – 0.6 V / REG5)
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 10 of 27
(s)
R2J20701NP
Application Example
Start-up Settings
Case 1)
Standalone or master chip in parallel operation
With the RC network on the TRK-SS pin, the voltage on the pin should ramp up slowly.
ON/OFF
REG5
R
0.6 V
TRK-SS
TRK-SS
C
Vout
TSS = − CR × Ln (1 − 0.6 V / 5 V)
Case 2)
(s)
Coincident tracking
The TRS-SS signal for channel two is the voltage from Vout1 after division by a resistor network. Vout1
must be greater than Vout2. Cross-talk is not generated between the channels.
REG5
R
Channel 1
Vout1
SW
TRK-SS
C
R1
FB
Vout1 (nominal) = 0.6 V × (R1 + R2) / R2
R2
From Vout1
REG5
R3
Channel 2
R4
Vout2
SW
TRK-SS
FB
R3
Vout2 (nominal) = 0.6 V × (R3 + R4) / R4
R4
Vout1
Output
voltage
Vout2
Time
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R2J20701NP
Case 3)
Retiometric tracking
The TRS-SS of channel two is tied to TRK-SS of channel 1.
No cross talk is observed between the channels.
REG5
R
Channel 1
Vout1
SW
TRK-SS
C
R1
FB
Vout1 (nominal) = 0.6 V × (R1 + R2) / R2
R2
REG5
R
Channel 1
Vout2
SW
TRK-SS
C
FB
R3
Vout2 (nominal) = 0.6 V × (R3 + R4) / R4
R4
Vout1
Output
voltage
Vout2
Time
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Page 12 of 27
R2J20701NP
Case 4)
R
C
Current sharing or two-phase operation
In the case of master–slave operation, the TRK-SS pin on the master device should be attached to an RC
network for soft starts. TRK-SS pins of slave devices should be tied to the master’s TRK-SS pin. The error
amplifiers on the slave devices can be disabled by pulling up the corresponding FB pins to REG5, and the
slave devices do not require loop-compensation networks.
REG5
Channel 1
(Master)
SW
TRK-SS
Ishare
FB
CT
Vout1
R1
Vout (nominal) = 0.6 V × (R1 + R2) / R2
R2
R
C
REG5
Channel 2
(Slave)
SW
TRK-SS
Ishare
CT
FB
To SGND (for current sharing and synchronized operation)
To REG5 (for current sharing and two-phase operation)
Choice of The Resistance of CS Pin
The CS pin is a current-output pin. A current 1/18500 of that of the high-side MOS FET flows through this pin, which
also has a dc current offset of 490 µA. The converter’s maximum current is determined by the voltage on the CS pin,
i.e. 1.5 V, and by the value of the external resistor attached to this pin. The resistance is determined as shown below.
Specification: L = 360 nH, Vin = 12 V, Vout = 1.8 V, Fsw = 500 kHz, Iout(max) = 25 A
Current through the choke coil is
ILpp = (Vin – Vout) × Vout / (L × Vin × Fsw) = 8.5 A (p-p)
Peak choke current is the current when Io is at its maximum, i.e.
Ilmax = Io(max) + 0.5 × ILpp = 25A + 4.25A = 29.25 A
Maximum CS pin output current is;
Icsmax = Ilmax / 18500 + Ics-dc = 29.25 A / 18500 + 490 µA = 2.071 mA
The ideal resistance for attachment to the CS pin is
RCS = Vcl / Icsmax =1.5 V / 2.071 mA = 724 Ω
Therefore choose 750 Ω as the value of the resistor for attachment to the CS pin.
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R2J20701NP
Output Voltage Setting
The error amplifier of the device has an accurate 0.6 V reference voltage. Feedback thus leads to a voltage of about 0.6
V on the FB pin once the converter system has stabilized, so the output voltage is
Vout = 0.6 V × (R1 + R2) / R2
REG5
R
Vout
SW
TRK-SS
C
CT
R1
FB
R2
Loop Compensation
Peak-current control makes design in terms of phase margins easier than is the case with voltage control. This is
because of differences between the characteristics of the PWM modulator and power stage in the two methods.
Figures 1 and 2 show the behavior of the PWM modulator and power stage in the cases of voltage control and peak
current control, respectively.
−40 dB/dec
Gain
(dB)
−20 dB/dec
Gain
(dB)
freq. (Hz)
freq. (Hz)
0
0
Phase
(deg) −90
Phase
(deg)
−180
−180
freq. (Hz)
Figure 1 Bode Plot of Modulator + Power Stage
(Voltage Mode)
freq. (Hz)
Figure 2 Bode Plot of Modulator + Power Stage
(Peak Curent Mode)
Feed-forward current to the modulator in the case of peak-current control means that the system is single pole, so we
see a –20 dB/decade cutoff and phase margin of 90° in the Bode plot. In voltage control, the system configures a twopole pole system. That is why rather complicated loop compensation of the error amplifier is required, such as type-III
compensation.
The design of effective compensation is thus much simpler in the case of peak-current control (refer to figure 3).
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
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R2J20701NP
Rf
Vout
Cf
EO
R1
FB
R2
0.6 V reference
50 kΩ
Amplifier output: to current-sense comparator
50 kΩ
Figure 3 Error Amplifier Compensation
Design example
Specification: L = 360 nH, Co = 600 µF, Fsw = 500 kHz, Vin = 12 V, Vout = 1.8 V, R1 = 2 kΩ, R2 = 1 kΩ,
RCS = 750 Ω
1. Flat-band gain of error amplifier
The flat-band gain is; Af = Rf / (R1 // R2) / 2 × {R2 / (R1 + R2)}
Hence, Rf = 2 × Af × R1 ……(1)
In the Bode plot, the total gain should be less than 1 (0 dB) at the switching frequency.
The total gain at Fsw (= Asw) depends on the flat-band gain, so Af should be expressed as follows.
Af = Asw × 2 π × Fsw × Co × RCS / Nt ……(2)
Here, Nt = Idh / Ics = 18500
In the typical way, the value chosen for Asw is in the range from 0.1 to 0.5, since this produces a stable control loop.
The transient response will be faster if a larger Asw is adopted ,but the system might be unstable.
We choose 0.2 for Asw in the example below.
Af = 0.2 × 2 π × 500 kHz × 600 µF × 750 Ω / 18500 = 15.283
Rf = 2 × 15.283 × 2 kΩ = 61.132 kΩ
Therefore, we select a value of 62 kΩ for Rf.
2. Selecting the Cf value to determine the frequency of the zero
The frequency of the zero established by Cf and Rf is about ten times the frequency of the pole for the power stage
and modulator.
We must start with the dc gain of the power stage and modulator.
A0 =
2 × Nt / RCS × L × Vin × Fsw
SQRT
{Vin2
− 8 × L × Vin × Fsw × (VCS0 × Nt / RCS) }
……(3)
Here VCS0 is the peak ac voltage on the CS pin when the load current is zero, thus
VCS0 = 0.5 × RCS × (Vin – Vout) × Vout / (L × Vin × Fsw) / 18500 ……(4)
= 0.5 × 750 Ω × (12 V – 1.8 V) × 1.8 V / (360 nH × 12 V × 500 kHz) / 18500
= 0.172 V
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R2J20701NP
Equation (3)
A0 =
=
=
2 × Nt / RCS × L × Vin × Fsw
SQRT
{Vin2
− 8 × L × Vin × Fsw × (VCS0 × Nt / RCS) }
……(3)
2 × 18500 / 750 Ω × 360 nH × 12 V × 500 kHz
SQRT {12 V2 − 8 × 360 nH × 12 V × 500 kHz × (0.172 V × 18500 / 750 Ω) }
106.56
SQRT {70.687}
= 12.674
The frequency of the pole established by the power stage and modulator is
F0 = Nt / (2 π × Co × RCS × A0) ……(5)
Thus,
F0 = 18500 / (2 π × 600 µF × 750 Ω × 12.674) = 516 Hz
Therefore, the frequency of the zero established by Cf and Rf is
Fzero = 10 × F0 = 5.16 kHz
Cf = (2 π × Fzero × Rf)–1 = (2 π × 5.16 kHz × 62 kΩ)–1 = 497 pF
Therefore, we select the value 510 pF for Cf.
Basically, the transient response is faster when Cf is smaller, but too small a value will make the system-loop
unstable.
Open loop converter
Gain (dB)
−20 dB/dec
−40 dB/dec
W/ error amp. compensation
BW/Af
A0
Error amp. unity gain
frequency
Af
−20 dB/dec
F0
Freq. (Hz)
Asw
Fzero
Fsw
Power stage and modulator
Figure 4
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 16 of 27
BW
R2J20701NP
Study of Vout Accuracy
The nominal output voltage is calculated as
Vout = VFB × (R1 + R2) / R2 ……(6)
Here, the typical feedback voltage is 0.6 V.
REG5
R
Vout
SW
TRK-SS
C
CT
R1
FB
R2
The accuracy of Vout is strongly dependent on the variation of VFB, R1 and R2. VFB has a variation of 1% and
resistance intrinsically has a certain variation. When we take the variation in resistance into account, equation (6) is
extended to produce equation (7).
Vout =
=
R1 × K1 + R2 × K2
R2 × K2
R1 × K1 / K2 + R2
R2
× VFB
× VFB ……(7)
Here, K1 and K2 are coefficients. Both are 1.00 in the ideal case.
By equation (6), R1 is chosen as
R1 =
Vout (typical)
VFB (typical)
−1
× R2
……(8)
Substituting this expression for R1 into equation (7) yields the following.
Vout (typical)
Vout = VFB ×
VFB (typical)
−1
×
K1
K2
+1
……(9)
Therefore, variation in Vout is expressed as
Vout
Vout (typical)
=
VFB
Vout (typical)
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 17 of 27
×
Vout (typical)
VFB (typical)
−1
×
K1
K2
+1
−1
× 100 (%) …… (10)
R2J20701NP
The accuracy of Vout can be estimated by using equation (10).
For example, if Vout (typical) = 1.8 V, resistance variation is 1% (i.e. K1, K2 = 1.01 and 0.99),
and VFB = 594 mV to 606 mV:
Vout
Vout (typical)
=
VFB
Vout (typical)
606 mV
=
×
×
1.8 V
Vout (typical)
VFB (typical)
1.8 V
600 mV
−1
×
−1
×
−1
×
K1
K2
1.01
0.99
+1
−1
× 100 (%) …… (10)
+1
−1
× 100 (%)
+1
−1
× 100 (%)
= 2.36%
or
594 mV
=
×
1.8 V
1.8 V
600 mV
0.99
1.01
= −2.31%
Therefore, the output accuracy will be ±2.3% under the above conditions.
Figure 5 shows the relationship between the accuracy of the resistance and the accuracy of the output voltage. The
resistor value must have an accuracy of 0.5% if the variation in output voltage from the system is to be kept within two
percent across the voltage range from 0.6 to 3.3 V.
3
Vout accuracy (%)
2
1
R = ±0.5%
0
R = ±1%
−1
−2
−3
0.5
1.0
1.5
2.0
2.5
3.0
Vout (typical)
Figure 5 Vout Accuracy vs. Vout Set Voltage
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 18 of 27
3.5
R2J20701NP
Current Sharing
Simply tie the Ishare pins together
VOUT
SYNC
Device 1
Ishare
CT
REG5
CT
REG5
CT
REG5
SYNC
Device 2
Device N
(up to 5)
Ishare
SYNC
Ishare
External Synchronization
Simply tie the CT pin to GND
External clock
5V
0V
VOUT
SYNC
Ishare
External clock;
Frequency range: 200 kHz to 1 MHz
Minimum pulse width: 100 ns
Maximum pulse duty cycle: 90%
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 19 of 27
CT
REG5
R2J20701NP
Current Sharing and Synchronization
Tie the Ishare and SYNC pins together
VOUT
SYNC
Device 1
(Master)
Ishare
CT
REG5
CT
REG5
CT
REG5
SYNC
Device 2
Ishare
SYNC
Device N
(up to 5)
Ishare
Two-Phase Operation
Tie the Ishare and SYNC pins together.
Device 1
(Master)
IL1
SYNC
Ishare
VOUT
CT
REG5
IL2
Device 2
(Slave)
SYNC
Ishare
CT
REG5
2.4 kΩ
IL1
IL2
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 20 of 27
R2J20701NP
Timing Chart
Peak Current Control
Max. Duty
(Internal signal)
RES
(Internal signal)
50 ns (typ.)
TLD
50 ns (typ.)
EO
(EO-Vbe) / 2
(Internal signal)
RAMP
0V
VIN
SW
0V
The high-side MOS FET is turned
off by the max. duty signal.
To obtain stable operation, settings should be such that the level on the switching node is
Note: Propagation delay is ignored.
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 21 of 27
high for at least 80 ns.
R2J20701NP
Oscillator and Pulse Generator
1. Standalone operation or operation as the master chip in a parallel configuration with other chips.
3V
CT
2V
5V
SYNC
0V
Max. Duty
(Internal signal)
50 ns (typ.)
RES
(Internal signal)
Note: Propagation delay is ignored.
Frequency of oscillation for CT:
Fct =
160 µA
2 × (CT(F) + 18 pF) × 1 V
(Hz)
Switching frequency
Fsw = 0.5 × Fct
(Hz)
Frequency setting range (for Fsw): 200 kHz to 1 MHz (i.e. 400 kHz to 2 MHz for Fct)
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 22 of 27
R2J20701NP
2. Operation as a slave chip (simple synchronous operation)
Should be pulled down to or below 0.8 V.
0.8 V
CT
0V
5V
SYNC
(Input)
0V
Max. Duty
(Internal signal)
50 ns (typ.)
RES
(Internal signal)
SYNC frequency range: 200 kHz to 1 MHz
Note: Propagation delay is ignored.
3. Operation as a slave chip in a parallel configuration (two-phase operation)
Should be pulled up to at least 4.4 V.
5V
CT
4.4 V
5V
SYNC
(Input)
0V
Max. Duty
(Internal signal)
50 ns (typ.)
RES
(Internal signal)
SYNC frequency range: 200 kHz to 1 MHz
Note: Propagation delay is ignored.
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 23 of 27
R2J20701NP
Hiccup Operation when the Over-Current Limit (OCL) is Reached
TRK-SS
Detected OCL
1.5 V
CS
1024 pulses skipped
1024 pulses skipped
0V
Normal operation
Note: Propagation delay is ignored.
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 24 of 27
R2J20701NP
Main Characteristics
VL vs. Temperature
VH vs. Temperature
7.7
7.3
7.6
7.2
7.5
7.1
7.0
7.3
VL (V)
VH (V)
7.4
7.2
7.1
6.9
6.8
6.7
7.0
6.9
6.6
6.8
6.5
6.7
–50 –25
0
25
50
6.4
–50 –25
75 100 125 150
0
25
50
75 100 125 150
Temperature (°C)
Temperature (°C)
Vreg vs. Temperature
Vfb vs. Temperature
610
5.10
608
606
5.05
Vfb (mV)
Vreg (V)
604
5.00
602
600
598
596
4.95
594
592
4.90
–50 –25
0
25
50
75 100 125 150
Temperature (°C)
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 25 of 27
590
–50 –25
0
25
50
75 100 125 150
Temperature (°C)
R2J20701NP
Fsync vs. Temperature
Von vs. Temperature
500
2.70
CT = 68 pF
2.65
490
2.60
Von (V)
Fsync (kHz)
480
470
460
2.55
2.50
2.45
450
2.40
440
430
–50 –25
2.35
0
25
50
2.30
–50 –25
75 100 125 150
0
25
50
75 100 125 150
Temperature (°C)
Temperature (°C)
Voff vs. Temperature
Fsync vs. CT
1.45
2000
1.40
1.35
Fsync (kHz)
Voff (V)
1000
1.30
1.25
1.20
1.15
1.10
1.05
–50 –25
0
25
50
75 100 125 150
Temperature (°C)
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 26 of 27
100
10
100
CT (pF)
500
R2J20701NP
Package Dimensions
RENESAS Code
PWQN0056KB-A
Previous Code
—
D
42
A
MASS[Typ.]
0.17g
B
1.00
29
0.55
2.05
28
1.00
42
43
28
2.00
0.65
E
3.35
43
3.40
29
1.00
JEITA Package Code
—
2×
56
15
15
56
C
14
14
56×
b
e
1
×M C A B
Reference Dimension in Millimeters
Symbol
C
42
3.25
3.60
29
3.60
3.25
43
28
c
C
A1
y
A
y1 C
0.85
0.50
3.60
3.25
2×
t
C
1
56×
Lp
t
1.00
C0.4
0.45
0.80
3.25
56
3.60
15
14
e
Standard Foot Print
REJ03G1459-0400 Rev.4.00 Jun 30, 2008
Page 27 of 27
0.30
0.70
1
D
E
A2
A
A1
b
b1
e
Lp
x
y
y1
t
HD
HE
ZD
ZE
c
c1
Min Nom Max
7.90 8.00 8.10
7.90 8.00 8.10
0.80
0
0.05
0.18 0.23 0.28
0.50
0.30 0.40 0.50
0.10
0.08
0.10
0.15
0.20
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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