FDS8958B Dual N & P-Channel PowerTrench® MOSFET Q1-N-Channel: 30 V, 6.4 A, 26 mΩ Q2-P-Channel: -30 V, -4.5 A, 51 mΩ Features General Description Q1: N-Channel These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild Semiconductor's advanced PowerTrench® process th at has been especially tailored to minimize on-state resistan ce and yet maintain superior switching performance. Max rDS(on) = 26 mΩ at VGS = 10 V, ID = 6.4 A Max rDS(on) = 39 mΩ at VGS = 4.5 V, ID = 5.2 A Q2: P-Channel These devices are well suite d for low voltage and battery powered applications where low in-line power loss and fast switching are required. Max rDS(on) = 51 mΩ at VGS = -10 V, ID = -4.5 A Max rDS(on) = 80 mΩ at VGS = -4.5 V, ID = -3.3 A Application HBM ESD protection level > 3.5 kV (Note 3) DC-DC Conversion RoHS Compliant BLU and motor drive inverter D2 D2 D1 D1 S1 Pin 1 G1 S2 G2 D2 5 D2 6 D1 7 D1 8 Q2 Q1 4 G2 3 S2 2 G1 1 S1 SO-8 MOSFET Maximum Ratings TC = 25 °C unless otherwise noted Symbol VDS VGS ID Parameter Q1 30 Drain to Source Voltage Gate to Source Voltage Drain Current - Continuous TA = 25 °C - Pulsed Q2 -30 Units V ±20 ±25 V 6.4 -4.5 30 -30 Power Dissipation for Dual Operation PD Power Dissipation for Single Operation EAS Single Pulse Avalanche Energy TJ, TSTG A 2.0 TA = 25 °C TA = 25 °C (Note 1a) 1.6 (Note 1b) 0.9 (Note 4) Operating and Storage Junction Temperature Range 18 W 5 -55 to +150 mJ °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient (Note 1) 40 (Note 1a) 78 °C/W Package Marking and Ordering Information Device Marking FDS8958B Device FDS8958B ©2008 Fairchild Semiconductor Corporation FDS8958B Rev.C Package SO-8 1 Reel Size 13 ” Tape Width 12 mm Quantity 2500 units www.fairchildsemi.com FDS8958B Dual N & P-Channel PowerTrench® MOSFET November 2013 Symbol Parameter Test Conditions Type Min Q1 Q2 30 -30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ∆BVDSS ∆TJ Breakdown Voltage Temperature Coefficient IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250 µA, VGS = 0 V ID = -250 µA, VGS = 0 V ID = 250 µA, referenced to 25 °C ID = -250 µA, referenced to 25 °C VDS = 24 V, VGS = 0 V VDS = -24 V, VGS = 0 V Q1 Q2 V 24 -21 mV/°C Q1 Q2 1 -1 µA VGS = ±20 V, VDS = 0 V VGS = ±25 V, VDS = 0 V Q1 Q2 ±100 ±10 nA µA VGS = VDS, ID = 250 µA VGS = VDS, ID = -250 µA Q1 Q2 3.0 -3.0 V On Characteristics VGS(th) Gate to Source Threshold Voltage ∆VGS(th) ∆TJ Gate to Source Threshold Voltage Temperature Coefficient rDS(on) gFS Static Drain to Source On Resistance Forward Transconductance 1.0 -1.0 2.0 -1.9 Q1 Q2 -6 5 Q1 21 29 31 26 39 39 Q2 38 60 53 51 80 72 VDD = 5 V, ID = 6.4 A VDD = -5 V, ID = -4.5 A Q1 Q2 20 10 Q1 VDS = 15 V, VGS = 0 V, f = 1 MHZ Q1 Q2 405 570 540 760 pF Q1 Q2 75 115 100 155 pF Q1 Q2 55 100 80 150 pF Q1 Q2 2.4 4.4 Q1 Q2 4.3 6.0 10 12 ns Q1 Q2 2.0 6.0 10 12 ns Q2 VDD = -15 V, ID = -4.5 A, VGS = -10 V, RGEN = 6 Ω Q1 Q2 12 17 22 30 ns Q1 Q2 2.0 7.0 10 14 ns VGS = 10 V VGS = -10 V Q1 Q2 8.3 14 12 19 nC Q1 Q2 4.1 7.0 5.8 9.6 nC Q1 Q2 1.3 1.9 nC Q1 Q2 1.7 3.6 nC ID = 250 µA, referenced to 25 °C ID = -250 µA, referenced to 25 °C VGS = 10 V, ID = 6.4 A VGS = 4.5 V, ID = 5.2 A VGS = 10 V, ID = 6.4A, TJ = 125 °C VGS = -10 V, ID = -4.5 A VGS = -4.5 V, ID = -3.3 A VGS = -10 V, ID = -4.5 A, TJ = 125 °C mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance Q2 VDS = -15 V, VGS = 0 V, f = 1 MHZ Ω Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) Total Gate Charge Qg(TOT) Total Gate Charge Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge ©2008 Fairchild Semiconductor Corporation FDS8958B Rev.C Q1 VDD = 15 V, ID = 6.4 A, VGS = 10 V, RGEN = 6 Ω VGS = 4.5 V VGS = -4.5 V Q1 VDD = 15 V, ID = 6.4 A Q2 VDD = -15 V, ID = -4.5 A 2 www.fairchildsemi.com FDS8958B Dual N & P-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 0.8 -0.8 1.2 -1.2 V Q1 Q2 17 20 30 36 ns Q1 Q2 6 8 12 16 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 1.3 A VGS = 0 V, IS = -1.3 A (Note 2) (Note 2) Q1 IF = 6.4 A, di/dt = 100 A/µs Q2 IF = -4.5 A, di/dt = 100 A/µs NOTES: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 78 °C/W when mounted on a 1 in2 pad of 2 oz copper b) 135 °C/W when mounted on a minimun pad 2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%. 3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. 4. UIL condition: Starting TJ = 25 °C, L = 1 mH, IAS = 6 A, VDD = 27 V, VGS = 10 V . (Q1) Starting TJ = 25 °C, L = 1 mH, IAS = -4 A, VDD = -27 V, VGS = -10 V. (Q2) ©2008 Fairchild Semiconductor Corporation FDS8958B Rev.C 3 www.fairchildsemi.com FDS8958B Dual N & P-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 3.0 VGS = 10 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 30 VGS = 6 V 24 VGS = 4.5 V VGS = 4 V 18 12 VGS = 3.5 V 6 0 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 0 0.5 1.0 1.5 2.0 2.5 3.0 VGS = 3.5 V VGS = 4.5 V 2.0 1.5 VGS = 6 V 1.0 0.5 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 0 6 Figure 1. On Region Characteristics rDS(on), DRAIN TO 1.0 0.8 0.6 -25 0 25 50 75 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.2 -50 100 125 150 45 TJ = 125 oC 30 TJ = 25 oC 2 30 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX VDS = 5 V 10 TJ = 125 oC TJ = 25 oC 5 TJ = -55 oC 1 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) 6 8 10 VGS = 0 V 10 TJ = 125 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.2 6 0.4 0.6 0.8 1.0 1.2 1.4 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2008 Fairchild Semiconductor Corporation FDS8958B Rev.C 4 Figure 4. On-Resistance vs Gate to Source Voltage IS, REVERSE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) ID = 3.2 A VGS, GATE TO SOURCE VOLTAGE (V) 15 0 60 TJ, JUNCTION TEMPERATURE (oC) 30 20 30 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 15 Figure 3. Normalized On Resistance vs Junction Temperature 25 24 75 1.4 0.4 -75 18 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage ID = 6.4 A VGS = 10 V 1.6 12 VGS = 10 V ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) 1.8 VGS = 4 V 2.5 Figure 6. Source to Drain Diode Forward Voltage vs Source Current 4 www.fairchildsemi.com FDS8958B Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted 1000 ID = 6.4 A Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 10 V 6 VDD = 15 V 4 VDD = 20 V 2 0 0 2 4 6 8 Coss 100 Crss f = 1 MHz VGS = 0 V 10 0.1 10 1 Qg, GATE CHARGE (nC) ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 100 9 8 7 6 5 TJ = 25 oC 3 2 TJ = 125 oC THIS AREA IS LIMITED BY rDS(on) 10 0.1 ms 1 ms 1 0.1 10 ms 100 ms SINGLE PULSE TJ = MAX RATED 1s RθJA = 135 oC/W 10 s DC TA = 25 oC 1 0.001 0.01 0.1 30 Figure 8. Capacitance vs Drain to Source Voltage Figure 7. Gate Charge Characteristics 4 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 1 10 0.01 0.01 100 tAV, TIME IN AVALANCHE (ms) 0.1 1 10 100 VDS, DRAIN to SOURCE VOLTAGE (V) Figure 9. Unclamped Inductive Switching Capability Figure 10. Forward Bias Safe Operating Area P(PK), PEAK TRANSIENT POWER (W) 500 VGS = 10 V 100 SINGLE PULSE o RθJA = 135 C/W o TA = 25 C 10 1 0.5 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 11. Single Pulse Maximum Power Dissipation ©2008 Fairchild Semiconductor Corporation FDS8958B Rev.C 5 www.fairchildsemi.com FDS8958B Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 135 C/W 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve ©2008 Fairchild Semiconductor Corporation FDS8958B Rev.C 6 www.fairchildsemi.com FDS8958B Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted VGS = -10 V 4.5 VGS = -6 V 24 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE -ID, DRAIN CURRENT (A) 30 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 18 VGS = -4.5 V 12 VGS = -4 V 6 VGS = -3.5 V 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VGS = -3.5 V 4.0 3.5 VGS = -4.5 V 3.0 PULSE DURATION = 80 µs DUTY CYCLE = 0.5%MAX 2.5 2.0 VGS = -6 V 1.5 1.0 0.5 VGS = -10 V 0 6 rDS(on), DRAIN TO 1.2 1.0 0.8 -50 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 200 ID = -4.5 A VGS = -10 V 0.6 -75 80 TJ = 125 oC 40 TJ = 25 oC 0 2 TJ = -55 oC TJ = 25 oC 10 5 1 2 3 4 5 8 10 VGS = 0 V 10 TJ = 125 oC TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.2 6 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -VSD, BODY DIODE FORWARD VOLTAGE (V) -VGS, GATE TO SOURCE VOLTAGE (V) Figure 20. Source to Drain Diode Forward Voltage vs Source Current Figure 19. Transfer Characteristics ©2008 Fairchild Semiconductor Corporation FDS8958B Rev.C 6 Figure 18. On-Resistance vs Gate to Source Voltage TJ = 125 oC 15 4 -VGS, GATE TO SOURCE VOLTAGE (V) -IS , REVERSE DRAIN CURRENT (A) -ID , DRAIN CURRENT (A) 20 0 ID = -2.3 A 30 VDS = -5 V 30 120 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 25 24 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 160 Figure 17. Normalized On-Resistance vs Junction Temperature 30 18 Figure 16. Normalized on-Resistance vs Drain Current and Gate Voltage Figure 15. On- Region Characteristics 1.4 12 -ID, DRAIN CURRENT (A) -VDS, DRAIN TO SOURCE VOLTAGE (V) 1.6 VGS = -4 V 7 www.fairchildsemi.com FDS8958B Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted -VGS, GATE TO SOURCE VOLTAGE (V) 10 2000 ID = -4.5 A 1000 8 6 CAPACITANCE (pF) VDD = -10 V VDD = -15 V 4 VDD = -20 V 2 0 0 3 6 9 12 Ciss Coss 100 30 0.1 15 1 -2 10 4 TJ -Ig, GATE LEAKAGE CURRENT(A) -IAS, AVALANCHE CURRENT (A) 30 Figure 22. Capacitance vs Drain to Source Voltage 8 7 6 5 = 25 oC 3 2 TJ = 125 oC VGS = 0V -3 10 -4 10 -5 10 TJ = 125oC -6 10 -7 10 TJ = 25oC -8 10 -9 1 0.01 0.1 1 10 10 0 5 tAV, TIME IN AVALANCHE (ms) 10 15 20 25 30 35 -VGS, GATE TO SOURCE VOLTAGE(V) Figure 23. Unclamped Inductive Switching Capability Figure 24. Ig vs Vgs 100 200 P(PK), PEAK TRANSIENT POWER (W) -ID, DRAIN CURRENT (A) 10 -VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 21. Gate Charge Characteristics 10 Crss f = 1 MHz VGS = 0 V THIS AREA IS LIMITED BY rDS(on) 0.1 ms 1 ms 1 0.1 10 ms 100 ms SINGLE PULSE TJ = MAX RATED 1s RθJA = 135 oC/W 10 s DC TA = 25 oC 0.01 0.01 0.1 1 10 100 -VDS, DRAIN to SOURCE VOLTAGE (V) Figure 25. Forward Bias Safe Operating Area ©2008 Fairchild Semiconductor Corporation FDS8958B Rev.C VGS = -10 V 100 SINGLE PULSE RθJA = 135 oC/W TA = 25 oC 10 1 0.5 -4 10 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) 10 100 1000 Figure 26. Single Pulse Maximum Power Dissipation 8 www.fairchildsemi.com FDS8958B Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 135 C/W 0.002 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 27. Junction-to-Ambient Transient Thermal Response Curve ©2008 Fairchild Semiconductor Corporation FDS8958B Rev.C 9 www.fairchildsemi.com FDS8958B Dual N & P-Channel PowerTrench® MOSFET Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted 0.65 A 4.90±0.10 (0.635) 8 5 B 1.75 6.00±0.20 1 PIN ONE INDICATOR 5.60 3.90±0.10 4 1.27 1.27 0.25 C B A LAND PATTERN RECOMMENDATION SEE DETAIL A 0.175±0.75 0.22±0.30 C 1.75 MAX 0.10 0.42±0.09 OPTION A - BEVEL EDGE (0.86) x 45° R0.10 GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08Arev15 F) FAIRCHILD SEMICONDUCTOR. SEATING PLANE 0.65±0.25 (1.04) DETAIL A SCALE: 2:1 Figure 16. 8-Lead, SOIC,JEDEC MS-012, .150-inch Narrow Body Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/M0/M08A.pdf. © 2008 Fairchild Semiconductor Corporation FDS8958B • Rev. C www.fairchildsemi.com 10 FDS8958B — Dual N & P-Channel PowerTrench® MOSFET Physical Dimensions FDS8958B — Dual N & P-Channel PowerTrench® MOSFET © 2008 Fairchild Semiconductor Corporation FDS8958B • Rev. C www.fairchildsemi.com 11