FDMC7200 Dual N-Channel PowerTrench® MOSFET 30 V, 12 mΩ and 23.5 mΩ Features General Description Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a Max rDS(on) = 23.5 mΩ at VGS = 10 V, ID = 6 A dual Power33 (3mm x 3mm MLP) package. The switch node has been internally connected to enable easy placement and Max rDS(on) = 38 mΩ at VGS = 4.5 V, ID = 5 A routing of synchronous buck converters. The control Q2: N-Channel MOSFET (Q1) and synchronous MOSFET (Q2) have been Max rDS(on) = 12 mΩ at VGS = 10 V, ID = 8 A designed to provide optimal power efficiency. Max rDS(on) = 18 mΩ at VGS = 4.5 V, ID = 7 A Applications RoHS Compliant Mobile Computing Mobile Internet Devices General Purpose Point of Load Pin 1 G1 D1 D1 D1 G HS D1 V IN V IN V IN H ITC SW D2/S1 G2 V IN S2 S2 DE NO S2 G LS D GN ND DG GN Q2 4 D1 S2 5 S2 6 3 D1 S2 7 2 D1 G2 8 Q1 1 G1 BOTTOM BOTTOM Power 33 MOSFET Maximum Ratings TC = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage (Note 3) Drain Current - Continuous (Package limited) TC = 25 °C Units V ±20 ±20 V 8 8 TC = 25 °C 20 40 - Continuous TA = 25 °C 6 1a 8 1b 40 40 Power Dissipation TA = 25 °C 1.9 1a 2.2 1b Power Dissipation TA = 25 °C 0.7 1c 0.9 1d - Pulsed TJ, TSTG Q2 30 - Continuous (Silicon limited) ID PD Q1 30 Operating and Storage Junction Temperature Range A -55 to +150 W °C Thermal Characteristics RθJA 65 1a Thermal Resistance, Junction to Ambient RθJA Thermal Resistance, Junction to Ambient RθJC Thermal Resistance, Junction to Case 180 1c 7.5 55 1b 145 1d °C/W 4 Package Marking and Ordering Information Device Marking FDMC7200 Device FDMC7200 ©2009 Fairchild Semiconductor Corporation FDMC7200 Rev.D1 Package Power 33 1 Reel Size 13 ” Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMC7200 Dual N-Channel PowerTrench® MOSFET June 2009 Symbol Parameter Test Conditions Type Min 30 30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 µA, VGS = 0 V ID = 250 µA, VGS = 0 V Q1 Q2 ∆BVDSS ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, referenced to 25 °C ID = 250 µA, referenced to 25 °C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V VDS = 24 V, VGS = 0 V Q1 Q2 1 1 µA IGSS Gate to Source Leakage Current VDS = 20 V, VGS = 0 V Q1 Q2 100 100 nA nA 3.0 3.0 V V 14 14 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 µA VGS = VDS, ID = 250 µA Q1 Q2 ∆VGS(th) ∆TJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 µA, referenced to 25 °C ID = 250 µA, referenced to 25 °C Q1 Q2 -5 -6 VGS = 10 V, ID = 6 A VGS = 4.5 V, ID = 5 A VGS = 10 V, ID = 6 A, TJ = 125 °C Q1 19 28 29 23.5 38 35.5 VGS = 10 V, ID = 8 A VGS = 4.5 V, ID = 7 A VGS = 10 V, ID = 8 A, TJ = 125 °C Q2 10 13 15 12 18 18 VDD = 5 V, ID = 6 A VDD = 5 V, ID = 8 A Q1 Q2 29 56 Q1 Q2 495 1180 660 1570 pF Q1 Q2 145 330 195 440 pF 30 45 pF rDS(on) gFS Static Drain to Source On Resistance Forward Transconductance 1.0 1.0 2.3 2.3 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Q1 Q2 20 30 Rg Gate Resistance Q1 Q2 1.4 1.4 Q1 Q2 11 13 20 23 ns Q1 Q2 3.1 4 10 10 ns Q1 Q2 35 38 56 60 ns Q1 Q2 1.3 6 10 12 ns Q1 Q2 7.3 16 10 22 nC Q1 Q2 3.1 7 4.3 10 nC Q1 Q2 1.8 4.1 nC Q1 Q2 1 1.5 nC VDS = 15 V, VGS = 0 V, f = 1 MHZ Ω Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) Total Gate Charge Qg(TOT) Total Gate Charge Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge ©2009 Fairchild Semiconductor Corporation FDMC7200 Rev.D1 Q1 VDD = 15 V, ID = 1 A, VGS = 10 V, RGEN = 6 Ω Q2 VDD = 15 V, ID = 1 A, VGS = 10 V, RGEN = 6 Ω VGS = 0 V to 10 V Q1: VDD = 15 V, VGS = 0 V to 4.5 V ID = 6 A, Q2: VDD = 15 V, ID = 8 A, 2 www.fairchildsemi.com FDMC7200 Dual N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 0.8 0.8 1.2 1.2 V Q1 Q2 13 21 24 34 ns Q1 Q2 2.3 5.6 10 12 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 6 A VGS = 0 V, IS = 8 A trr Reverse Recovery Time Qrr Reverse Recovery Charge Q1 IF = 6 A, di/dt = 100 A/s Q2 IF = 8 A, di/dt = 100 A/s (Note 2) (Note 2) Notes: 1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a.65 °C/W when mounted on a 1 in2 pad of 2 oz copper b.55 °C/W when mounted on a 1 in2 pad of 2 oz copper c. 180 °C/W when mounted on a minimum pad of 2 oz copper d. 145 °C/W when mounted on a minimum pad of 2 oz copper 2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%. 3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied. ©2009 Fairchild Semiconductor Corporation FDMC7200 Rev.D1 3 www.fairchildsemi.com FDMC7200 Dual N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 40 4 ID, DRAIN CURRENT (A) VGS = 6 V 30 VGS = 4.5 V 20 VGS = 4 V 10 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX VGS = 3.5 V 0 0.0 0.5 1.0 1.5 2.0 2.5 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V 3 VGS = 3.5 V VGS = 4 V 2 VGS = 4.5 V 1 0 3.0 0 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 30 40 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 100 ID = 6 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 -75 -50 -25 0 25 50 75 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 20 ID, DRAIN CURRENT (A) Figure 1. On Region Characteristics PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 80 ID = 6 A 60 TJ = 125 oC 40 20 TJ = 25 oC 0 100 125 150 2 TJ, JUNCTION TEMPERATURE (oC) 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 40 40 IS, REVERSE DRAIN CURRENT (A) PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) VGS = 10 V VGS = 6 V 30 VDS = 5 V 20 TJ = 150 oC TJ = 25 oC 10 TJ = -55 oC 0 2.0 2.5 3.0 3.5 4.0 1 TJ = 150 oC 0.1 TJ = 25 oC 0.01 TJ = -55 oC 0.001 0.2 4.5 VGS, GATE TO SOURCE VOLTAGE (V) 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2009 Fairchild Semiconductor Corporation FDMC7200 Rev.D1 VGS = 0 V 10 Figure 6. Source to Drain Diode Forward Voltage vs Source Current 4 www.fairchildsemi.com FDMC7200 Dual N-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted 10 1000 VGS, GATE TO SOURCE VOLTAGE (V) ID = 6 A Ciss CAPACITANCE (pF) 8 VDD = 20 V VDD = 15 V 6 VDD = 10 V 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 2 4 6 10 0.1 8 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 100 25 o 10 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) RθJC = 7.5 C/W 100 us 1 ms 1 10 ms THIS AREA IS LIMITED BY rDS(on) 0.1 100 ms 1s 10 s DC SINGLE PULSE TJ = MAX RATED 0.01 RθJA = 180 oC/W VGS = 10 V 20 15 VGS = 4.5 V 10 5 Limited by Package o TC = 25 C 0.001 0.01 0.1 1 10 0 25 100200 50 75 100 125 150 o Tc, CASE TEMPERATURE ( C) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 9. Forward Bias Safe Operating Area Figure 10. Maximum Continuous Drain Current vs Case Temperature 300 P(PK), PEAK TRANSIENT POWER (W) SINGLE PULSE o RθJA = 180 C/W 100 o TA = 25 C 10 1 0.5 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (s) Figure 11. Single Pulse Maximum Power Dissipation ©2009 Fairchild Semiconductor Corporation FDMC7200 Rev.D1 5 www.fairchildsemi.com FDMC7200 Dual N-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE 0.01 o RθJA = 180 C/W 0.003 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 12. Junction-to-Ambient Transient Thermal Response Curve ©2009 Fairchild Semiconductor Corporation FDMC7200 Rev.D1 6 www.fairchildsemi.com FDMC7200 Dual N-Channel PowerTrench® MOSFET Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted 6 40 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V 30 VGS = 4.5 V VGS = 4 V 20 VGS = 3.5 V 10 0 0.0 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX VGS = 3 V 0.5 1.0 1.5 2.0 2.5 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 5 VGS = 3 V 4 VGS = 3.5 V 3 VGS = 4 V 2 1 VGS = 10 V 0 3.0 0 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 30 40 Figure 14. Normalized on-Resistance vs Drain Current and Gate Voltage 1.6 60 ID = 8 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 20 ID, DRAIN CURRENT (A) Figure 13. On-Region Characteristics PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 50 ID = 8 A 40 30 TJ = 125 oC 20 10 TJ = 25 oC 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 16. On-Resistance vs Gate to Source Voltage Figure 15. Normalized On-Resistance vs Junction Temperature 40 IS, REVERSE DRAIN CURRENT (A) 40 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) VGS = 4.5 V 30 VDS = 5 V 20 TJ = 150 oC TJ = 25 oC 10 TJ = -55 oC 0 1.5 2.0 2.5 3.0 3.5 TJ = 150 oC 1 TJ = 25 oC 0.1 0.01 TJ = -55 oC 0.001 0.0 4.0 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 18. Source to Drain Diode Forward Voltage vs Source Current Figure 17. Transfer Characteristics ©2009 Fairchild Semiconductor Corporation FDMC7200 Rev.D1 VGS = 0 V 10 7 www.fairchildsemi.com FDMC7200 Dual N-Channel PowerTrench® MOSFET Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted 2000 Ciss ID = 8 A 1000 8 VDD = 15 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 10 V VDD = 20 V 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 3 6 9 12 15 10 0.1 18 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 19. Gate Charge Characteristics Figure 20. Capacitance vs Drain to Source Voltage 100 50 o ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) RθJC = 4 C/W 100 us 10 1 ms 1 10 ms THIS AREA IS LIMITED BY rDS(on) 100 ms SINGLE PULSE TJ = MAX RATED 0.1 1s RθJA = 145 oC/W 10 s DC o TC = 25 C 0.01 0.01 0.1 1 10 40 VGS = 10 V 30 VGS = 4.5 V 20 10 0 25 100200 Limited by Package 50 75 100 125 150 o Tc, CASE TEMPERATURE ( C) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 21. Forward Bias Safe Operating Area Figure 22. Maximum Continuous Drain Current vs Case Temperature 1000 P(PK), PEAK TRANSIENT POWER (W) SINGLE PULSE o RθJA = 145 C/W o TA = 25 C 100 10 1 0.5 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (s) Figure 22. Single Pulse Maximum Power Dissipation ©2009 Fairchild Semiconductor Corporation FDMC7200 Rev.D1 8 www.fairchildsemi.com FDMC7200 Dual N-Channel PowerTrench® MOSFET Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 145 C/W 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 23. Junction-to-Ambient Transient Thermal Response Curve ©2009 Fairchild Semiconductor Corporation FDMC7200 Rev.D1 9 www.fairchildsemi.com FDMC7200 Dual N-Channel PowerTrench® MOSFET Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted FDMC7200 Dual N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2009 Fairchild Semiconductor Corporation FDMC7200 Rev.D1 10 www.fairchildsemi.com tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I40 ©2009 Fairchild Semiconductor Corporation FDMC7200 Rev.D1 11 www.fairchildsemi.com FDMC7200 Dual N-Channel PowerTrench® MOSFET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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