FDMC8032L Dual N-Channel PowerTrench® MOSFET 40 V, 7 A, 20 mΩ Features General Description Max rDS(on) = 20 mΩ at VGS = 10 V, ID = 7 A This device includes two 40V N-Channel MOSFETs in a dual Power 33 (3 mm X 3 mm MLP) package. The package is enhanced for exceptional thermal performance. Max rDS(on) = 27 mΩ at VGS = 4.5 V, ID = 6 A Low Inductance Packaging Shortens Rise/Fall Times Lower Switching Losses Applications 100% Rg Tested Battery Protection Termination is Lead-free and RoHS Compliant Load Switching Point of Load Pin 1 Pin 1 G1 S1 S1 S1 G1 G2 S1 S2 S1 S2 S1 S2 D1 D2 G2 S2 S2 S2 Power 33 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID -Continuous TC = 25 °C -Continuous TA = 25 °C -Pulsed Single Pulse Avalanche Energy EAS PD TJ, TSTG TC = 25 °C Power Dissipation TA = 25 °C Units V ±20 V 20 (Note 1a) 7 (Note 4) 50 (Note 3) Power Dissipation Ratings 40 13 12 (Note 1a) Operating and Storage Junction Temperature Range 1.9 -55 to +150 A mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient 9.7 (Note 1a) 65 °C/W Package Marking and Ordering Information Device Marking FDMC8032L Device FDMC8032L ©2013 Fairchild Semiconductor Corporation FDMC8032L Rev. C1 Package Power 33 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMC8032L Dual N-Channel PowerTrench® MOSFET October 2013 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 32 V, VGS = 0 V IGSS Gate to Source Leakage Current, Forward VGS = ±20 V, VDS = 0 V 40 V 23 mV/°C 1 μA 100 nA 3.0 V On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C VGS = 10 V, ID = 7 A 16 20 Static Drain to Source On Resistance VGS = 4.5 V, ID = 6 A 21 27 VGS = 10 V, ID = 7 A TJ = 125 °C 23 29 VDD = 5 V, ID = 7 A 27 rDS(on) gFS Forward Transconductance 1.0 1.8 -5 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 20 V, VGS = 0 V f = 1MHz 0.1 513 720 pF 137 195 pF 9.3 15 pF 2.6 3.6 Ω Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) VDD = 20 V, ID = 7 A VGS = 10 V, RGEN = 6 Ω 5.5 11 ns 1.2 10 ns 13 24 ns 1.3 10 ns nC Total Gate Charge VGS = 0 V to 10 V 7.6 11 Total Gate Charge VGS = 0 V to 4.5 V VDD = 20 V ID = 7 A 3.6 5.1 Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge nC 1.5 nC 1.0 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 7 A (Note 2) 0.85 1.3 VGS = 0 V, IS = 1.4 A (Note 2) 0.75 1.2 IF = 7 A, di/dt = 100 A/μs V 16 29 ns 3.9 10 nC NOTES: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. b. 155 °C/W when mounted on a minimum pad of 2 oz copper a. 65 °C/W when mounted on a 1 in2 pad of 2 oz copper SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 3. EAS of 13 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 3 A, VDD = 40 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 11 A. 4. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area. ©2013 Fairchild Semiconductor Corporation FDMC8032L Rev. C1 2 www.fairchildsemi.com FDMC8032L Dual N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 50 VGS = 6 V 40 VGS = 4.5 V 30 VGS = 4 V 20 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3.5 V 0 0 1 2 5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V 4 VGS = 3.5 V 3 VGS = 4 V 2 VGS = 4.5 V 1 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 3 0 10 VDS, DRAIN TO SOURCE VOLTAGE (V) rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 80 ID = 7 A VGS = 10 V -50 30 40 50 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 0.6 -75 VGS = 10 V ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX ID = 7 A 60 40 TJ = 125 oC 20 TJ = 25 oC 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On- Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 50 IS, REVERSE DRAIN CURRENT (A) 50 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 40 ID, DRAIN CURRENT (A) 20 VGS = 6 V VDS = 5 V 30 TJ = 150 oC 20 TJ = 25 oC 10 TJ = -55 oC 0 1 2 3 4 5 VGS = 0 V 10 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 6 0.2 0.4 0.6 0.8 1.0 1.2 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2013 Fairchild Semiconductor Corporation FDMC8032L Rev. C1 3 1.4 www.fairchildsemi.com FDMC8032L Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 1000 ID = 7 A VDD = 15 V Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 20 V 6 VDD = 25 V 4 100 Coss 10 Crss f = 1 MHz VGS = 0 V 2 0 0 2 4 6 1 0.1 8 1 Figure 7. Gate Charge Characteristics 24 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 40 Figure 8. Capacitance vs Drain to Source Voltage 20 10 TJ = 25 oC TJ = 100 oC TJ = 125 oC 20 16 VGS = 10 V 12 Limited by Package 8 VGS = 4.5 V 4 o RθJC = 9.7 C/W 1 0.001 0.01 0.1 1 0 25 10 50 150 2000 P(PK), PEAK TRANSIENT POWER (W) 100 SINGLE PULSE 1000 10 μs 10 100 μs THIS AREA IS LIMITED BY rDS(on) 1 ms SINGLE PULSE TJ = MAX RATED 10 ms DC RθJC = 9.7 oC/W 0.01 0.1 125 Figure 10. Maximum Continuous Drain Current vs Case Temperature 300 0.1 100 TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability 1 75 o tAV, TIME IN AVALANCHE (ms) ID, DRAIN CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) TC = 25 oC CURVE BENT TO MEASURED DATA 1 10 o TC = 25 C 100 10 -5 10 100 -4 10 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 12. Single Pulse Maximum Power Dissipation Figure 11. Forward Bias Safe Operating Area ©2013 Fairchild Semiconductor Corporation FDMC8032L Rev. C1 o RθJC = 9.7 C/W 4 www.fairchildsemi.com FDMC8032L Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: ZθJC(t) = r(t) x RθJC SINGLE PULSE 0.001 -5 10 RθJC = 9.7 °C/W Peak TJ = PDM x ZθJC(t) + TC Duty Cycle, D = t1 / t2 -4 10 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation FDMC8032L Rev. C1 5 www.fairchildsemi.com FDMC8032L Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted FDMC8032L Dual N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout ©2013 Fairchild Semiconductor Corporation FDMC8032L Rev. C1 6 www.fairchildsemi.com tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I66 ©2013 Fairchild Semiconductor Corporation FDMC8032L Rev. C1 7 www.fairchildsemi.com FDMC8032L Dual N-Channel PowerTrench® MOSFET TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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