TIP110 / TIP111 / TIP112 NPN Epitaxial Silicon Darlington Transistor Equivalent Circuit Features C • Monolithic Construction with Built-in Base-Emitter Shunt Resistors • Complementary to TIP115 / TIP116 / TIP117 • High DC Current Gain: hFE = 1000 @ VCE = 4 V, IC = 1 A (Minimum) • Low Collector-Emitter Saturation Voltage • Industrial Use B 1 TO-220 R1 1.Base 2.Collector 3.Emitter R2 R1 ≅ 10kΩ R2 ≅ 0.6kΩ E Ordering Information Part Number Top Mark Package Packing Method TIP110 TIP110 TO-220 3L (Single Gauge) Bulk TIP110TU TIP110 TO-220 3L (Single Gauge) Rail TIP111TU TIP111 TO-220 3L (Single Gauge) Rail TIP112 TIP112 TO-220 3L (Single Gauge) Bulk TIP112TU TIP112 TO-220 3L (Single Gauge) Rail Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Values are at TC = 25°C unless otherwise noted. Symbol Parameter Value TIP110 VCBO VCEO Collector-Base Voltage Collector-Emitter Voltage Unit 60 TIP111 80 TIP112 100 TIP110 60 TIP111 80 TIP112 100 VEBO Emitter-Base Voltage 5 V V V IC Collector Current (DC) 2 A ICP Collector Current (Pulse) 4 A IB Base Current (DC) 50 mA TJ Junction Temperature 150 °C -65 to 150 °C TSTG Storage Temperature Range © 2001 Fairchild Semiconductor Corporation TIP110 / TIP111 / TIP112 Rev. 1.1.0 www.fairchildsemi.com TIP110 / TIP111 / TIP112 — NPN Epitaxial Silicon Darlington Transistor November 2014 Values are at TC = 25°C unless otherwise noted. Symbol PC Parameter Value Collector Dissipation (TA = 25°C) 2 Collector Dissipation (TC = 25°C) 50 Unit W Electrical Characteristics(1) Values are at TC = 25°C unless otherwise noted. Symbol Parameter Conditions TIP110 VCEO(sus) Collector-Emitter Sustaining Voltage ICBO Collector Cut-Off Current Collector Cut-Off Current IEBO Emitter Cut-Off Current hFE DC Current Gain Max. Unit 60 TIP111 IC = 30 mA, IB = 0 TIP112 ICEO Min. 80 V 100 TIP110 VCE = 30 V, IB = 0 2 TIP111 VCE = 40 V, IB = 0 2 TIP112 VCE = 50 V, IB = 0 2 TIP110 VCB = 60 V, IE = 0 1 TIP111 VCB = 80 V, IE = 0 1 TIP112 VCB = 100 V, IE = 0 1 VEB = 5 V, IC = 0 2 mA IC = 2 A, IB = 8 mA 2.5 V VCE = 4 V, IC = 1 A 1000 VCE = 4 V, IC = 2 A 500 mA mA VCE(sat) Collector-Emitter Saturation Voltage VBE(on) Base-Emitter On Voltage VCE = 4 V, IC = 2 A 2.8 V Output Capacitance VCB = 10 V, IE = 0, f = 0.1 MHz 100 pF Cob Note: 1. Pulse test: pw ≤ 300 μs, duty cycle ≤ 2%. © 2001 Fairchild Semiconductor Corporation TIP110 / TIP111 / TIP112 Rev. 1.1.0 www.fairchildsemi.com 2 TIP110 / TIP111 / TIP112 — NPN Epitaxial Silicon Darlington Transistor Thermal Characteristics 10000 IB = 500μA 1.8 IB = 450μA 1.6 IB = 400μA μA 350 I B= 00μA IB = 3 VCE = 4V 0μA I B = 25 hFE, DC CURRENT GAIN IC[A], COLLECTOR CURRENT 2.0 1.4 1.2 IB = 200μA 1.0 0.8 0.6 IB = 150μA 0.4 1000 100 0.2 10 0.01 0.0 0 1 2 3 4 5 0.1 VCE[V], COLLECTOR-EMITTER VOLTAGE Figure 1. Static Characteristic 10 Figure 2. DC Current Gain 1000 100 IC = 500 IB f = 0.1 MHz Cob[pF], CAPACITANCE VBE(sat), VCE(sat)[V], SATURATION VOLTAGE 1 IC[A], COLLECTOR CURRENT 10 VBE(sat) 1 VCE(sat) 0.1 0.01 0.1 1 100 10 1 0.01 10 IC[A], COLLECTOR CURRENT 0.1 1 10 100 VCB[V], COLLECTOR-BASE VOLTAGE Figure 3. Base-Emitter Saturation Voltage and Collector-Emitter Saturation Voltage Figure 4. Collector Output Capacitance 80 10 PC[W], POWER DISSIPATION 1mS 5mS IC[A], COLLECTOR CURRENT 70 DC 1 TIP 110 TIP 111 TIP 112 0.1 1 10 50 40 30 20 10 0 0 100 VCE[V], COLLECTOR-EMITTER VOLTAGE 25 50 75 100 125 150 175 o TC[ C], CASE TEMPERATURE Figure 5. Safe Operating Area © 2001 Fairchild Semiconductor Corporation TIP110 / TIP111 / TIP112 Rev. 1.1.0 60 Figure 6. Power Derating www.fairchildsemi.com 3 TIP110 / TIP111 / TIP112 — NPN Epitaxial Silicon Darlington Transistor Typical Performance Characteristics TIP110 / TIP111 / TIP112 — NPN Epitaxial Silicon Darlington Transistor Physical Dimensions Figure 7. TO-220, MOLDED, 3LEAD, JEDEC VARIATION AB © 2001 Fairchild Semiconductor Corporation TIP110 / TIP111 / TIP112 Rev. 1.1.0 www.fairchildsemi.com 4 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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