SANYO LC875164A

Ordering number : ENN*6715
CMOS IC
LC875164A/48A/32A
8-Bit Single Chip Microcontroller with
64/48/32K-Byte ROM and 1024-Byte RAM On Chip
Preliminary
Overview
The LC875164A/48A/32A microcontroller is 8-bit single chip microcontroller with the following on-chip functional blocks:
- CPU: Operable at a minimum bus cycle time of 100ns
- 64K/48K/32K bytes ROM
- 1024 byte RAM
- two high performance 16 bit timer/counters (can be divided into 8 bit units)
- two 8 bit timers with prescalers
- timer for use as date/time clock
- two synchronous serial I/O ports (with automatic block transmit/receive function)
- one asynchronous/synchronous serial I/O port
- 12-bit PWM × 2
- 8-channel × 8-bit AD converter
- high speed 8-bit parallel interface
- 19-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Features
(1) Read Only Memory
- 65536 × 8 bits (LC875164A)
- 49151 × 8 bits (LC875148A)
- 32512 × 8 bits (LC875132A)
Ver.1.03
O3098
91400 RM (IM) HK / SY No.6715-1/25
LC875164A/48A/32A
(2) Bus Cycle Time
- 100ns (10MHz)
Note: The bus cycle time indicates ROM read time.
(3) Minimum Instruction Cycle Time
: 300ns (10MHz)
(4) Ports
- Input/output ports
Each bit data direction programmable
Nibble data direction programmable
- Input ports
- PWM Output ports
- Oscillator pins
- Reset pin
- Power supply
59
8
2
2
2
1
6
(P1n,P2n,P3n,P70 to P73,P8n,PAn,PBn,PCn,S2Pn)
(P0n)
(XT1,XT2)
(PWM0,PWM1)
(CF1,CF2)
( RES )
(VSS1 to 3,VDD1 to 3)
(5) Timers
- Timer0: 16 bit timer/counter with capture register
Mode 0: 2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8 bit
capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register
- Timer1: PWM/16 bit timer/counter (with toggle output)
Mode 0: 8 bit timer (with toggle output) + 8 bit timer counter (with toggle output)
Mode 1: 2 channel 8 bit PWM
Mode 2: 16 bit timer/counter (with toggle output)
Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output.
- Timer4: 8-bit timer with 6-bit prescaler
- Timer5: 8-bit timer with 6-bit prescaler
- Base timer
1. The clock signal can be selected from any of the following: sub-clock (32.768kHz crystal oscillator), system
clock, and prescaler output for timer 0.
2. Interrupts can be selected to occur at one of five different times.
(6) SIO
- SIO0: 8 bit synchronous serial interface
1. LSB first/MSB first function available
2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 TCYC)
3. Continuous automatic data communications (1 - 256 bits)
- SIO1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 T CYC)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 - 2048 TCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 TCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
- SIO2: 8 bit synchronous serial interface
1. LSB-first
2. Built in 8-bit baud-rate generator (Maximum clock period 4/3 TCYC)
3. Continuous automatic data communication (1 - 32 bytes)
(7) AD converter
- 8-bits × 8-channels
(8) PWM
- 2 channel synchronous variable 12 bit PWM
(9) Parallel interface
- RS, RD , WR , CS0 - CS2 Outputs (reversible polarity)
- read/write possible in 1 TCYC
No.6715-2/25
LC875164A/48A/32A
(10) Remote control receiver circuit (connected to P73/INT3/T0IN terminal)
- Noise rejection function (noise rejection filter time constant can selected from 1/32/128 TCYC)
(11) Watchdog timer
- The watchdog timer period set by external RC.
- Watchdog timer can be set to produce interrupt, system reset
(12) Interrupts
- 19-source, 10-vectored interrupts:
1. Three level (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or
lower level interrupt request is refused.
2. If interrupt requests to two or more vector addresses occur at once, the higher level interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
1
2
3
4
5
6
7
8
9
10
Vector
00003H
0000BH
00013H
0001BH
00023H
0002BH
00033H
0003BH
00043H
0004BH
Selectable Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt signal
INT0
INT1
INT2/T0L/INT4
INT3/INT5/Base timer
T0H
T1L/T1H
SIO0
SIO1/SIO2
ADC
Port 0/T4/T5/PWM0, 1
• Priority Level : X > H > L
• For equal priority levels, vector with lowest address takes precedence.
(13) Subroutine stack levels
- 512 levels max. Stack is located in RAM
(14) Multiplication and division
- 16 bit × 8 bit
(executed in 5 cycles)
- 24 bit × 16 bit
(12 cycles )
- 16 bit ÷ 8 bit
(8 cycles)
- 24 bit ÷ 16 bit
(12 cycles)
(15) Oscillation circuits
- On-chip RC oscillation circuit used for system clock
- On-chip CF oscillation circuit used for system clock
- On-chip Crystal oscillation circuit used for system clock and time-base clock
(16) Standby function
- HALT mode
HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate.
1. Oscillation circuits are not stopped automatically
2. Release on system reset
- HOLD mode
HOLD mode is used to reduce the power dissipation. Both program execution and peripheral circuits are stopped.
1. CF, RC and crystal oscillation circuits stop automatically
2. Release occurs on any of the following conditions
•input to the reset pin goes low
•a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5
•an interrupt condition arises at port 0
No.6715-3/25
LC875164A/48A/32A
- X’tal HOLD mode
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits
except the base timer are stopped.
1. CF and RC oscillation circuits stop automatically
2. Crystal oscillator is maintained in its state at HOLD mode inception.
3. Release occurs on any of the following conditions
•input to the reset pin goes low
•a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5
•an interrupt condition arises at port 0
•an interrupt condition arises at the base-timer
(17) Factory shipment
- delivery form QIP80E
- delivery form SQFP80
(18) Development Tools
- Evaluation chip
- Emulator
: LC876099
: EVA87000 + ECB875100 (Evaluation chip board) + POD875100 (POD)
No.6715-4/25
LC875164A/48A/32A
SI2P3/SCK20
PWM1
PWM0
VDD2
VSS2
P00
P01
P02
P03
P04
P05
P06
P07
P20/INT4/T1IN
P21/INT4/T1IN
P22/INT4/T1IN
P23/INT4/T1IN
P24/INT5/T1IN
P25/INT5/T1IN
P26/INT5/T1IN
P27/INT5/T1IN
PB7/D7
PB6/D6
PB5/D5
Pin Assignment
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PB4/D4
65
40
SI2P2/SCK2
PB3/D3
66
39
SI2P1/S12/SB2
PB2/D2
67
38
SI2P0/SO2
PB1/D1
68
37
P17/T1PWMH/BUZ
PB0/D0
69
36
P16/T1PWML
VSS3
70
35
P15/SCK1
VDD3
71
34
P14/SI1/SB1
PC7/A7
72
33
P13/SO1
PC6/A6
73
32
P12/SCK0
PC5/A5
74
31
P11/SI0/SB0
PC4/A4
75
30
P10/SO0
PC3/A3
76
29
P34
PC2/A2
77
28
P33
PC1/A1
78
27
P32
PC0/A0
79
26
P31
PA0/CS2#
80
25
P30
P72/INT2/T0IN
P73/INT3/T0IN
P87/AN7
P71/INT1/T0HCP
P86/AN6
P70/INT0/T0LCP
P85/AN5
PA5/RS
P84/AN4
PA4/RD#
P83/AN3
PA3/WR#
P82/AN2
PA1/CS1#
P81/AN1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
P80/AN0
8
VDD1
7
CF2
6
CF1
5
VSS1
4
XT2
3
XT1
2
RES#
1
PA2/CS0#
LC875164A/48A/32A
QIP80
Package Dimension
(unit : mm)
3174
SANYO : QIP-80E
No.6715-5/25
LC875164A/48A/32A
PWM0
VDD2
VSS2
P00
P01
P02
P03
P04
P05
P06
P07
P20/INT4/T1IN
P21/INT4/T1IN
P22/INT4/T1IN
P23/INT4/T1IN
P24/INT5/T1IN
P25/INT5/T1IN
P26/INT5/T1IN
P27/INT5/T1IN
PB7/D7
Pin Assignment
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PB6/D6
61
40
PWM1
PB5/D5
62
39
SI2P3/SCK20
PB4/D4
63
38
SI2P2/SCK2
PB3/D3
64
37
SI2P1/SI2/SB2
PB2/D2
65
36
SI2P0/SO2
PB1/D1
66
35
P17/T1PWMH/BUZ
PB0/D0
67
34
P16/T1PWML
VSS3
68
33
P15/SCK1
VDD3
69
32
P14/SI1/SB1
PC7/A7
70
31
P13/SO1
PC6/A6
71
30
P12/SCK0
PC5/A5
72
29
P11/SI0/SB0
PC4/A4
73
28
P10/SO0
PC3/A3
74
27
P34
PC2/A2
75
26
P33
PC1/A1
76
25
P32
PC0/A0
77
24
P31
PA0/CS2#
78
23
P30
PA1/CS1#
79
22
P87/AN7
PA2/CS0#
80
21
P86/AN6
P70/INT0/T0LCP
P71/INT1/T0HCP
P72/INT2/T0IN
P73/INT3/T0IN
RES#
XT1
P85/AN5
PA5/RS
P84/AN4
PA4/RD#
P83/AN3
9 10 11 12 13 14 15 16 17 18 19 20
P82/AN2
8
P81/AN1
7
P80/AN0
6
VDD1
5
CF2
4
CF1
3
VSS1
2
XT2
1
PA3/WR#
LC875164A/48A/32A
SQFP80
Package Dimension
(unit : mm)
3220
SANYO : SQFP-80
No.6715-6/25
LC875164A/48A/32A
QIP
1
2
PA1/ CS1
SQFP
79
QIP
41
NAME
SI2P3/SCK20
SQFP
39
PA2/ CS0
80
42
PWM1
40
3
PA3/ WR
1
43
PWM0
41
4
PA4/ RD
PA5/RS
P70/INT0/T0LCP
P71/INT1/T0HCP
P72/INT2/T0IN
P73/INT3/T0IN
2
44
VDD2
42
3
4
5
6
7
8
45
46
47
48
49
50
VSS2
P00
P01
P02
P03
P04
43
44
45
46
47
48
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P05
P06
P07
P20/INT4/T1IN
P21/INT4/T1IN
P22/INT4/T1IN
P23/INT4/T1IN
P24/INT5/T1IN
P25/INT5/T1IN
P26/INT5/T1IN
P27/INT5/T1IN
PB7/D7
PB6/D6
PB5/D5
PB4/D4
PB3/D3
PB2/D2
PB1/D1
PB0/D0
VSS3
VDD3
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NAME
RES
XT1
XT2
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7
P30
P31
P32
P33
P34
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
SI2P0/SO2
SI2P1/SI2/SB2
SI2P2/SCK2
PA0/ CS2
No.6715-7/25
LC875164A/48A/32A
System Block Diagram
IR
Interrupt control
PLA
ROM
CF
RC
Xtal
Clock
Generator
Standby control
PC
SIO0
Bus Interface
ACC
SIO1
Port 0
B Register
SIO2
Port 1
C Register
Timer 0
Port 3
ALU
Timer 1
Port 7
Timer 4
Port 8
PSW
Timer 5
ADC
RAR
PWM0
PWM1
INT0-3
Noise Rejection Filter
Port 2
RAM
INT4,,5
Stack Pointer
Base Timer
Parallel interface
Port A
Port B
Port C
Watch Dog Timer
No.6715-8/25
LC875164A/48A/32A
Pin Assignment
Pin Name
VSS1
VSS2
VSS3
VDD1
VDD2
VDD3
Port 0
P00 - P07
I/O
-
Negative power supply
Option
No
-
Positive power supply
No
•8-bit Input/output port
•Data direction can be specified in nibble units
•Use of pull-up resistor can be specified in nibble units
•HOLD-release input
•Input for port 0 interrupt
•8-bit Input/output port
•Data direction can be specified for each bit
•Use of pull-up resistor can be specified for each bit
•Other functions
P10: SIO0 data output
P11: SIO0 data input/bus input/output
P12: SIO0 clock input/output
P13: SIO1 data output
P14: SIO1 data input/bus input/output
P15: SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/Buzzer output
•8-bit Input/output port
•Data direction can be specified for each bit
•Use of pull-up resistor can be specified for each bit
•Other functions
P20-P23: INT4 input/HOLD release input/timer 1 event input
/Timer 0L capture input/Timer 0H capture input
P24-P27: INT5 input/HOLD release input/timer 1 event input
/Timer 0L capture input /Timer 0H capture input
Interrupt receiver format
Rising
Falling
Rising/
H level
falling
INT4
Yes
Yes
Yes
No
INT5
Yes
Yes
Yes
No
Yes
I/O
Port 1
P10 - P17
I/O
Port 2
P20 - P27
I/O
Port 3
P30 - P34
I/O
Port 7
I/O
P70 - P73
Pin Function
•5-bit Input/output port
•Data direction can be specified for each bit
•Use of pull-up resistor can be specified for each bit
•4-bit Input/output port
•Data direction can be specified for each bit
•Use of pull-up resistor can be specified for each bit
•Other functions
P70: INT0 input/HOLD release input/Timer0L capture input
/Output for watchdog timer
P71: INT1 input/HOLD release input/Timer0H capture input
P72: INT2 input/HOLD release input/timer 0 event input
/Timer0L capture input
P73: INT3 input(noise rejection filter attached input)
/timer 0 event input/Timer0H capture input
Interrupt receiver format
Rising
Falling
Rising/
H level
falling
Yes
No
Yes
Yes
INT0
Yes
No
Yes
Yes
INT1
No
Yes
Yes
Yes
INT2
No
Yes
Yes
Yes
INT3
Yes
Yes
L level
No
No
Yes
No
L level
Yes
Yes
No
No
(Continued)
No.6715-9/25
LC875164A/48A/32A
Name
I/O
Port 8
P80 - P87
I/O
Port A
PA0 - PA5
I/O
Function description
•8-bit Input/output port
•Data direction can be specified for each bit
•Other functions
P80-P87: AD input port
•6-bit Input/output port
•Data direction can be specified for each bit
•Use of pull-up resistor can be specified for each bit
•Other functions
PA0: Parallel interface output CS2
Option
No
Yes
PA1: Parallel interface output CS1
PA2: Parallel interface output CS0
PA3: Parallel interface output WR
Port B
PB0 - PB7
I/O
Port C
PC0 - PC7
I/O
SIO2 Port
SI2P0
- SI2P3
I/O
PWM0
PWM1
RES
O
O
I
XT1
I
XT2
I/O
CF1
CF2
I
O
PA4: Parallel interface output RD
PA5: Parallel interface output RS
•8-bit Input/output port
•Data direction can be specified for each bit
•Use of pull-up resistor can be specified for each bit
•Other functions
PB0-PB7: Parallel interface data input/output; address output
•8-bit Input/output port
•Data direction can be specified for each bit
•Use of pull-up resistor can be specified for each bit
•Other functions
PC0-PC7: Parallel interface address output
•4-bit Input/output port
•Data direction can be specified for each bit
•Other functions
SI2P0: SIO2 data output
SI2P1: SIO2 data output/bus input/output
SI2P2: SIO2 clock input/output
SI2P3: SIO2 clock output
PWM0 output port
PWM1 output port
Reset terminal
•Input for 32.768kHz crystal oscillation
•Other function
Input port
When not in use, connect to VDD1.
•Output for 32.768kHz crystal oscillation
•Other function
General purpose input port
When not in use, set to oscillation mode and leave open circuit
Input terminal for ceramic oscillator
Output terminal for ceramic oscillator
Yes
Yes
No
No
No
No
No
No
No
No
No.6715-10/25
LC875164A/48A/32A
Port Output Configuration
Output configuration and pull-up resistor options are shown in the following table.
Input is possible even when port is set to output mode.
Terminal
P00-P07
P10-P17
P20-P27
P30-P34
PA0-PA5
PB0-PB7(*)
PC0-PC7
P70
P71-P73
P80-P87
SI2P0, SI2P2
SI2P3
PWM0,
PWM1
SI2P1
XT1
XT2
Option
applies to:
1 bit units
Option
Output Format
Pull-up resistor
1
2
1
2
CMOS
Nch-open drain
CMOS
Nch-open drain
Programmable (Note 1)
None
Programmable
Programmable
each bit
1
2
CMOS
Nch-open drain
Programmable
Programmable
-
None
None
None
None
Nch-open drain
CMOS
Nch-open drain
CMOS
Programmable
Programmable
None
None
-
None
None
-
None
None
CMOS (When used as standard port)
Nch-open drain (When used for SIO2 data)
Input only
Output for 32.768kHz crystal oscillation
each bit
None
None
Note 1 Programmable pull-up resisters of Port 0 can be attatched in nibble units (P00-03, P04-07).
(*) When in parallel interface mode, PB0-PB7 output format is CMOS, regardless of any selected option.
Note: Connect as follows to reduce noise on VDD and increase the back-up time.
VSS1, VSS2 and VSS3 must be connected together and grounded.
The voltage of Port 7 should be fixed.
Example 1 : In hold mode, during backup, port output ‘H’ level is supplied from the back-up capacitor.
LSI
VDD1
Power
Supply
Back-up capacitor
VDD2
VDD3
VSS1
VSS2
VSS3
Example 2 : During backup in hold mode output is not held high and its value in unsettled.
LSI
VDD1
Power
Supply
Back-up capacitor
VDD2
VDD3
VSS1
VSS2
VSS3
No.6715-11/25
LC875164A/48A/32A
1. Absolute Maximum Ratings at Ta=25°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Supply voltage
VDDMAX
Input voltage
Output voltage
Input/output
voltage
VI(1)
VO(1)
VIO(1)
High
level
output
current
Peak
output
current
Total
output
current
Low
level
output
current
Peak
output
current
Total
output
current
Maximun power
dissipation
Operating
temperature
range
Storage
temperature
range
IOPH(1)
IOPH(2)
ΣIOAH(1)
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
ΣIOAH(5)
IOPL(1)
IOPL(2)
IOPL(3)
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
ΣIOAL(6)
Pdmax
Pins
VDD1, VDD2,
VDD3
XT1, XT2, CF1
PWM0, PWM1
Ports 0, 1, 2
Ports 3, 7, 8
Ports A, B, C
SI2P00-SI2P03
PWM0, PWM1
Ports 0, 1, 2, 3
Ports A, B, C
SI2P00-SI2P03
PWM0, PWM1
P71-P73
P71-P73
Port 1
PWM0, PWM1
Port 3
SI2P00-SI2P03
Ports 0, 2
Port B
Ports A, C
P02-P07
Ports 1, 2, 3
Ports A, B, C
SI2P00-SI2P03
PWM0, PWM1
P00, P01
Ports 7, 8
Port 7
Port 8
Port 1
PWM0, PWM1
Port 3
SI2P00-SI2P03
Ports 0, 2
Port B
Ports A, C
QIP80E
SQFP80
Conditions
VDD1=VDD2
=VDD3
VDD[V]
min.
-0.3
-0.3
-0.3
-0.3
•CMOS output
•For each pin.
Ratings
typ.
max.
+7.0
-5
-5
-30
The total of all pins.
The total of all pins.
The total of all pins.
For each pin.
-20
-20
-20
V
VDD+0.3
VDD+0.3
VDD+0.3
mA
-10
For each pin.
The total of all pins.
The total of all pins.
unit
20
For each pin.
For each pin.
The total of all pins.
The total of all pins.
The total of all pins.
30
5
15
15
50
The total of all pins.
The total of all pins.
The total of all pins.
Ta=-30 to +70°C
70
40
40
350
mW
°C
Topg
-30
70
Tstg
-55
125
No.6715-12/25
LC875164A/48A/32A
2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pins
Operating
supply voltage
range
VDD(1)
HOLD voltage
VHD
VDD1=VDD2
=VDD3
Input high
voltage
VIH(1)
•Ports 1, 2
•P71-P73
•P70 port input
/interrupt
•Ports 0, 8
•Ports A, B, C
Port 70 Watchdog
timer input
XT1, XT2, CF1,
RES
•Ports 1, 2
•P71-P73
•P70 port input
/interrupt
•Ports 0, 8
•Ports A, B, C
Port 70 Watchdog
timer input
XT1, XT2, CF1,
RES
VIH(2)
VIH(3)
VIH(4)
Input low
voltage
VIL(1)
VIL(2)
VIL(5)
VIL(6)
Operation
cycle time
tCYC
External
system clock
frequency
FEXCF(1)
VDD1=VDD2
=VDD3
CF1
Conditions
0.294µs ≤ tCYC ≤
200µs
0.588µs ≤ tCYC ≤
200µs
RAM and the
register data are
kept in HOLD mode.
•CF2 open circuit
•system clock
divider set to 1/1
•external clock
DUTY=50±5%
•CF2 open circuit
•system clock
divider set to 1/2
(Note 1)
VDD[V]
min.
4.5
Ratings
typ.
max.
6.0
2.5
6.0
2.0
6.0
2.5 - 6.0
0.3VDD
+0.7
VDD
2.5 - 6.0
0.3VDD
+0.7
VDD
2.5 - 6.0 0.9VDD
VDD
2.5 - 6.0 0.75VDD
VDD
2.5 - 6.0
VSS
0.1VDD
+0.4
2.5 - 6.0
VSS
0.15VDD
+0.4
2.5 - 6.0
VSS
0.8VDD
-1.0
2.5 - 6.0
VSS
0.25VDD
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
0.294
0.588
0.1
200
200
10
0.2
20.4
unit
V
µs
MHz
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
The oscillation constant is shown in Tables 1 and 2.
No.6715-13/25
LC875164A/48A/32A
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Input high
current
Input low
current
Output high
current
Symbol
IIH(1)
IIH(2)
•Ports 0, 1, 2
•Ports 3, 7, 8
•Ports A, B, C
•SI2P00-SI2P03
• RES
•PWM0, PWM1
XT1, XT2
IIH(3)
CF1
IIL(1)
IIL(2)
•Ports 0, 1, 2
•Ports 3, 7, 8
•Ports A, B, C
•SI2P00-SI2P03
• RES
•PWM0, PWM1
XT1, XT2
IIL(3)
CF1
VOH(1)
•Ports 0, 1, 2, 3
•Ports B, C
•SI2P00-SI2P03
•PWM0, PWM1
Port A
VOH(2)
Output low
current
Pull-up
resistor
Hysteresis
voltage
Pin
capacitance
Pins
VOH(3)
VOH(4)
VOH(5)
VOL(1)
VOL(2)
VOL(3)
VOL(4)
VOL(5)
VOL(6)
VOL(7)
VOL(8)
Rpu
Port 7
•Ports 0, 1, 2, 3
•Ports B, C
•SI2P00-SI2P03
•PWM0, PWM1
P00, P01
Ports 7, 8
Port A
•Ports 0, 1, 2, 3
•Port 7
•Ports A, B, C
VHIS
RES
CP
All pins
Conditions
•Output disable
•Pull-up resistor off
•VIN=VDD
(including off state
leak current of
output Tr.)
When specified as an
input port.
VIN=VDD
VIN=VDD
VDD[V]
2.5 - 6.0
min.
1
2.5 - 6.0
15
-1
2.5 - 6.0
-1
2.5 - 6.0
-15
IOH=-2.0mA
4.5 - 6.0
VDD-1
IOH=-0.1mA
2.5 - 6.0 VDD-0.5
IOH=-5.0mA
IOH=-1.0mA
IOH=-1.0mA
IOL=10mA
4.5 - 6.0 VDD-1
2.5 - 6.0 VDD-0.5
2.5 - 6.0 VDD-1
4.5 - 6.0
IOL=1.6mA
IOL=1.0mA
IOL=30mA
IOL=1mA
IOL=0.5mA
IOL=15mA
IOL=2mA
VOH=0.9VDD
2.5 - 6.0
2.5 - 6.0
4.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 6.0
2.5 - 6.0
4.5 - 5.5
•Every other terminal
connected to VSS.
•f=1MHz
•Ta=25°C
max.
1
2.5 - 6.0
2.5 - 6.0
•Output disable
•Pull-up resistor off
•VIN=VSS
(including off state
leak current of
output Tr.)
When specified as an
input port
VIN=VSS
VIN=VSS
Ratings
typ.
unit
µA
V
1.5
V
0.4
0.4
1.5
0.4
15
40
1.5
0.4
70
kΩ
4.5 - 5.5
0.1VDD
V
4.5 - 5.5
10
pF
No.6715-14/25
LC875164A/48A/32A
4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Serial clock
Input clock
Parameter
Symbol
Pins
SCK0(P12),
SI2P2
Output clock
Serial input
Refer to figure 6
VDD[V]
2.5 - 6.0
min.
2
Cycle
tSCK(1)
Low level
pulse width
tSCKL(1)
1
tSCKLA(1)
1
tSCKH(1)
1
High level
pulse width
tSCKHA(1)
Cycle
tSCK(2)
Low level
pulse width
High level
pulse width
Cycle
tSCKL(2)
1
tSCKH(2)
1
Low level
pulse width
tSCKL(3)
tSCK(3)
High level
pulse width
Ratings
typ.
SCK1(P15)
SCK0(P12),
SI2P2
SI2P3
Refer to figure 6
•Use pull-up resistor
(1kΩ) when output
is open drain.
•Refer to figure 6
SCK0(P12)
SIO0
SI2P2, SI2P3
SIO2
2.5 - 6.0
unit
tCYC
2.5 - 6.0
2
4/3
tSCK
1/2
3/4
1
tSCKH(3)
1/2
tSCKHA(2)
SCK0(P12)
SIO0
SI2P2, SI2P3
SIO2
•CMOS output option
•Refer to figure 6
2
7/4
Cycle
tSCK(4)
Low level
pulse width
High level
pulse width
Data set-up
time
tSCKL(4)
1/2
tSCKH(4)
1/2
Data hold
time
thDI
Output delay
time
tdD0
tsDI
max.
3(SIO0)
tSCKLA(2)
Serial output
Conditions
SCK1(P15)
SB0(P11),
SB1(P14),
SI2P1
SI0
SI1
•Data set-up to
SI0CLK
•Refer to figure 6
2.5 - 6.0
4.5 - 6.0
2
tCYC
tSCK
µs
0.03
2.5 - 6.0
4.5 - 6.0
0.03
2.5 - 6.0
SO0(P10),
SO1(P13),
SB0(O11),
SB1(P14),
SI2P0,
SI2P1
•Data set-up to
SI0CLK
•When port is open
drain: Time delay
from SI0CLK trailing
edge to the SO data
change.
•Refer to figure 6
4.5 - 6.0
1/3tCYC
+0.05
2.5 - 6.0
1/3tCYC
+0.05
No.6715-15/25
LC875164A/48A/32A
5. Parallel Input/Output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format.
Please refer to figures 8 and 9 for parallel output timing waveforms.
Parameter
Symbol
Write cycle, Read tC(1)
cycle
Address set-up
tsA(1)
time
Pins
Conditions
• WR (PA3), PB0-PB7
• RD (PA4), PC0-PC7
VDD[V]
2.5 - 6.0
min.
From address set-up
until control signal
changes
2.5 - 6.0
1/3tCYC
-30ns
2.5 - 6.0
Ratings
typ.
1
max.
unit
tCYC
tCYC
& ns
tsA(2)
RD (PA4), PC0-PC7
Address hold time thA(1)
RD (PA4), PC0-PC7
From change of RD
until address change
2.5 - 6.0
2/3tCYC
-30ns
1/6tCYC
thA(2)
WR (PA3), PC0-PC7
2.5 - 6.0
5
ns
tsRS(1)
WR (PA3), RS(PA5),
From change of WR
until address change
From change of RS,
CS until change in
2.5 - 6.0
1/6tCYC
-15ns
tCYC
& ns
2.5 - 6.0
1/6tCYC
-15ns
1/3tCYC
-15ns
1/3tCYC
-15ns
RS set-up tie
CS (PAX)
CS
set-up time
RS
hold time
WR
from change of RS
until change in RD
tsRS(2)
RD (PA4), RS(PA5)
tsRS(3)
RD (PA4), RS(PA5)
2.5 - 6.0
tsCS(1)
RD (PA4), CS (PAX) From change in CS
2.5 - 6.0
tsCS(2)
WR
until change in RD
(PA3), From change in CS
2.5 - 6.0
2/3tCYC
-15ns
CS (PAX)
until change in WR
thRS(1)
WR (PA3), RS(PA5)
From change in WR
until change in RS
2.5 - 6.0
0
ns
thRS(2)
RD (PA4), RS(PA5),
CS (PAX)
From change in RD
until change in RS,
CS
2.5 - 6.0
1/6tCYC
tCYC
& ns
2.5 - 6.0
0
ns
From change in RD
until change in CS
2.5 - 6.0
1/6tCYC
tCYC
& ns
From change in WR
2.5 - 6.0
0
ns
1/6tCYC
-5ns
2/3tCYC
-5ns
1/6tCYC
-5ns
1/3tCYC
-5ns
thRS(3)
RD (PA4), RS(PA5),
CS (PAX)
CS
hold time
thCS(1)
RD (PA4), RS(PA5)
thCS(2)
WR (PA3), RS(PA5)
until change in CS
WR
’H’ pulse width
WR
’L’ pulse width
tWRH(1)
WR (PA3)
2.5 - 6.0
tWRH(2)
WR (PA3)
2.5 - 6.0
tWRL(1)
WR (PA3)
2.5 - 6.0
tWRL(2)
WR (PA3)
2.5 - 6.0
1/6
tCYC
2/3
tCYC
1/6
tCYC
1/3
tCYC
tCYC
& ns
(Continued)
No.6715-16/25
LC875164A/48A/32A
Parameter
Symbol
Pins
Conditions
tRDH(1)
RD (PA4)
VDD[V]
2.5 - 6.0
tRDH(2)
RD (PA4)
2.5 - 6.0
tRDL(1)
RD (PA4)
2.5 - 6.0
tRDL(2)
RD (PA4)
2.5 - 6.0
tdDT(1)
RD (PA4), PB0-PB7
tdDT(2)
RD (PA4), PB0-PB7
Input data
set-up time
tsDTR(1)
RD (PA4), PB0-PB7
Input data
hold time
thDTR(1)
RD (PA4), PB0-PB7
Output data
set-up time
Output data
set-up time
tsDTW(1)
RD (PA4), PB0-PB7
tsDTW(2)
RD (PA4), PB0-PB7
Output data
hold time
thDTW(1)
RD (PA4), PB0-PB7
RD
’H’ pulse width
RD
’L’ pulse width
Data write
permission delay
thDTW(2)
min.
1/6tCYC
-5ns
1/3tCYC
-5ns
1/3tCYC
-5ns
1/2tCYC
-5ns
Ratings
typ.
1/6
tCYC
1/3
tCYC
1/3
tCYC
1/2
tCYC
max.
unit
tCYC
& ns
Time for permission,
from RD leading
edge until input data
set-up
(Note 1)
From input data setup to RD leading
edge.
(Note 2)
2.5 - 6.0
2.5 - 6.0
40
ns
From RD leading
edge until input data
hold
From output data setup until WR
leading
edge
2.5 - 6.0
0
ns
2.5 - 6.0
1/3tCYC
-30ns
1/3tCYC
-30ns
tCYC
& ns
2.5 - 6.0
0
ns
2.5 - 6.0
0
From WR leading
edge until output data
hold
1/6tCYC
-15ns
1/3tCYC
-15ns
2.5 - 6.0
2.5 - 6.0
Note 1 : Time until incorrect data of Low is disappeared.
Note 2 : Incorrect data of Low is not output in the period between tRDL(1) - tdDT(1).
6. Pulse input Conditions at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pins
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0(P70),
INT1(P71),
INT2(P72)
INT4(P20-P23)
INT5(P24-P27)
INT3(P73)
(The noise
rejection clock
select to 1/1.)
INT3(P73)
(The noise
rejection clock
select to 1/32.)
INT3(P73)
(The noise
rejection clock
select to 1/128.)
•Interrupt acceptable
•Events to timer 0
and 1 can be input.
RES
tPIH(2)
tPIL(2)
tPIH(3)
tPIL(3)
tPIH(4)
tPIL(4)
tPIL(5)
Conditions
VDD[V]
2.5 - 6.0
min.
1
•Interrupt acceptable
•Events to timer 0
can be input.
2.5 - 6.0
2
•Interrupt acceptable
•Events to timer 0
can be input.
2.5 - 6.0
64
•Interrupt acceptable
•Events to timer 0
can be input.
2.5 - 6.0
256
Reset acceptable
2.5 - 6.0
200
Ratings
typ.
max.
unit
tCYC
µs
No.6715-17/25
LC875164A/48A/32A
7. AD Converter Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Resolution
Absolute
precision
Conversion
time
Analog input
voltage range
Analog port
input current
Symbol
N
ET
Pins
AN0(P80)
- AN7(P87)
TCAD
Conditions
(Note 2)
AD conversion time
=32 × tCYC
(ADCR2=0)
(Note 3)
AD conversion time
=64 × tCYC
(ADCR2=1)
(Note 3)
VAIN
IAINH
IAINL
VAIN=VDD
VAIN=VSS
VDD[V]
3.0 - 6.0
3.0 - 6.0
min.
3.0 - 6.0
15.10
(tCYC=
0.588µs)
Ratings
typ.
8
max.
unit
±1.5
bit
LSB
97.92
µs
(tCYC=
3.06µs)
15.10
97.92
(tCYC=
0.294µs)
(tCYC=
1.53µs)
3.0 - 6.0
VSS
VDD
V
3.0 - 6.0
3.0 - 6.0
1
µA
-1
3.0 - 6.0
(Note 2) Absolute precision not including quantizing error (±1/2 LSB).
(Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to register.
8. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Current flow
during basic
operation
(Note 4)
Symbol
IDDOP(1)
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
Pins
VDD
Conditions
•FmCF=10MHz for
Ceramic resonator
oscillation
•FsX’tal=32.768kHz for
crystal oscillation
•System clock: CF
oscillation
•Internal RC oscillation
stopped.
•FmCF=5MHz for
Ceramic resonator
oscillation
•FsX’tal=32.768kHz for
crystal oscillation
•System clock: CF
oscillation
•Internal RC oscillation
stopped.
•FmCF=0Hz
(oscillation stops)
•FsX’tal=32.768kHz for
crystal oscillation
•System clock: Internal
RC oscillation
•FmCF=0Hz
(oscillation stops)
•FsX’tal=32.768kHz for
crystal oscillation
•System clock: X’tal
oscillation
•Internal RC oscillation
stopped.
Ratings
typ.
16
max.
29
4.5 - 6.0
2.5 - 4.5
7
3
12
8
4.5 - 6.0
2.5 - 4.5
1
0.5
3.0
2
4.5 - 6.0
40
80
2.5 - 4.5
15
46
VDD[V]
4.5 - 6.0
min.
unit
mA
µA
(Continued)
No.6715-18/25
LC875164A/48A/32A
Parameter
Symbol
Pins
Current flow:
IDDHALT(1) VDD
HALT mode
(Note 4)
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
Current flow:
IDDHOLD(1) VDD1
HOLD mode
IDDHOLD(2)
(Note 4)
IDDHOLD(2) VDD1
Current flow:
Date/time
clock HOLD
mode
Conditions
•HALT mode
•FmCF=10MHz for
ceramic resonator
oscillation
•FsX’tal=32.768kHz for
crystal oscillation
•System clock: CF
oscillation
•Internal RC oscillation
stopped.
•HALT mode
•FmCF=5MHz for
Ceramic resonator
oscillation
•FsX’tal=32.768kHz for
crystal oscillation
•System clock: CF
oscillation
•Internal RC oscillation
stopped.
•HALT mode
•FmCF=0Hz
(oscillation stops)
•FsX’tal=32.768kHz for
crystal oscillation
•System clock: Internal
RC oscillation
•HALT mode
•FmCF=0Hz
(oscillation stops)
•FsX’tal=32.768kHz for
crystal oscillation
•System clock: X’tal
oscillation
•Internal RC oscillation
stopped.
HOLD mode
Date/time clock HOLD
mode
•CF1=VDD or open
circuit (when using
external clock)
•FmX’tal=32.768kHz for
crystal oscillation
Ratings
typ.
6
max.
13
4.5 - 6.0
2.5 - 4.5
3
1.2
5
3
4.5 - 6.0
2.5 - 4.5
500
300
1500
1000
4.5 - 6.0
2.5 - 4.5
25
8
70
30
4.5 - 6.0
2.5 - 4.5
0.01
0.01
30
30
µA
4.5 - 6.0
2.5 - 4.5
45
6
100
36
µA
VDD[V]
4.5 - 6.0
min.
unit
mA
µA
(Note 4) The currents of output transistors and pull-up MOS transistors are ignored.
No.6715-19/25
LC875164A/48A/32A
Main system clock oscillation circuit characteristics
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board SANYO has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer.
Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Circuit Parameters
Frequency
Manufacturer
Murata
10MHz
Kyocera
Murata
5MHz
Murata
4MHz
Kyocera
Oscillator
C1
C2
CSA10.0MTZ 33pF 33pF
CST10.0MTW (30pF) (30pF)
KBR-10.0M
33pF 33pF
CSA5.00MG
33pF 33pF
CST5.00MGW (30pF) (30pF)
Rd1
0Ω
0Ω
0Ω
0Ω
0Ω
CSA4.00MG
33pF 33pF 0Ω
CST4.00MGW (30pF) (30pF) 0Ω
KBR-4.0MSA 33pF 33pF 0Ω
Operating
supply voltage
range
4.5 - 6.0V
4.5 - 6.0V
4.5 - 6.0V
4.5 - 6.0V
4.5 - 6.0V
Oscillation stabilizing time
4.5 - 6.0V
4.5 - 6.0V
4.5 - 6.0V
Notes
typ
max
0.05ms
0.05ms
0.05ms
0.05ms
0.05ms
0.50ms
0.50ms
0.50ms
0.50ms
0.50ms
0.05ms
0.05ms
0.05ms
0.50ms
0.50ms
0.50ms
Built in C1,C2
Built in C1,C2
Built in C1,C2
*The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum
operating voltage. (Refer to Figure4)
Subsystem clock oscillation circuit characteristics
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board SANYO has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer.
Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator
Frequency
Manufacturer
32.768kHz
Seiko EPSON
Oscillator
C-002Rx
Circuit Parameters
Operating supply
voltage range
C3
C4
Rf
Rd2
12pF 15pF OPEN 300kΩ
4.5 - 6.0V
Oscillation stabilizing time
typ
max
1.0S
3.0S
Notes
*The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the
sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure4)
(Notes)
•Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to the oscillation pins as possible with the shortest possible pattern length.
CF1
CF2
XT1
XT2
Rd1
Rf
Rd2
C1
C2
CF
C4
C3
X’tal
Figure 1
Ceramic oscillation circuit
Figure 2
Crystal oscillation circuit
0.5VDD
Figure 3
AC timing measurement point
No.6715-20/25
LC875164A/48A/32A
VDD
Power Supply
VDD limit
GND
Reset time
RES#
Internal RC
Resonator oscillation
tmsCF
CF1,CF2
tmsXtal
XT1,XT2
Operation mode
Reset
Unfixed
Instruction execution mode
Reset time and oscillation stable time
HOLD release signal
Without HOLD
Release signal
HOLD release signal VALID
Internal RC
Resonator oscillation
tmsCF
CF1,CF2
tmsXtal
XT1,XT2
Operation mode
HOLD
HALT
HOLD release signal and oscillation stable time
Figure 4
Oscillation stabilizing time
No.6715-21/25
LC875164A/48A/32A
VDD
RRES
(Note)
Set CRES, RRES values such that reset time
exceeds 200µs.
RES
CRES
Figure 5
Reset circuit
SI0CLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transmission period
(only SIO0,2)
tSCK
tSCKL
tSCKH
SI0CLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM transmission period
(only SIO0,2)
tSCKLA
tSCKHA
SI0CLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6
Serial input/output test condition
tPIL
Figure 7
tPIH
Pulse input timing condition
No.6715-22/25
LC875164A/48A/32A
• Parallel Input/Output timing waveform : Indirect Setting, Read Mode
tC(1)
read cycle
addr
ADR/DATA:
tsA(1)
CS#:
thRS(1)
tsRS(1)
RS:
tWRH(1)
tWRL(1)
tsRS(2)
tRDL(1)
thRS(2)
WR#:
tsDTR(1)
tRDH(1)
RD#:
tdDT(1)
DATAin:
thDTR(1)
H
data
Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format.
• Parallel Input/Output timing waveform : Indirect Setting, Write Mode
tC(1)
write cycle
ADR/DATA:
addr
data
tsA(1)
thDTW(1)
CS#:
tsRS(1)
thRS(3)
thRS(1)
RS:
tWRH(1)
tWRL(1)
tsRS(3)
tsDTW(1)
WR#:
tWRL(2)
RD#:
DATAin:
Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format.
Figure 8
Indirect mode: Parallel Timing Waveforms
No.6715-23/25
LC875164A/48A/32A
• Parallel Input/Output timing waveform : Direct Setting, Read Mode
tC(1)
read cycle
ADR:
addr
tsA(1)
thA(1)
tsCS(1)
thCS(1)
CS#:
DATA:
tRDL(2)
WR#:
tsDTR(1)
tRDH(2)
RD#:
thDTR(1)
tdDT(2)
DATAin:
H
data
Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format.
• Parallel Input/Output timing waveform : Direct Setting, Write Mode
tC(1)
write cycle
ADR:
addr
tsA(2)
thA(2)
tsCS(2)
thCS(2)
CS#:
data
DATA:
tsDTW(2)
thDTW(2)
WR#:
tWRH(2)
tWRL(2)
RD#:
DATAin:
Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format.
Figure 9
Direct Mode: Parallel Input/Output Timing Diagrams
No.6715-24/25
LC875164A/48A/32A
memo:
PS No.6715-25/25