PHILIPS OQ2536HP

INTEGRATED CIRCUITS
DATA SHEET
OQ2536HP
SDH/SONET STM16/OC48
demultiplexer
Product specification
File under Integrated Circuits, IC19
1998 Mar 10
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
FEATURES
DESCRIPTION
• Normal and loop (test) modes
The OQ2536HP is a 32-channel demultiplexer intended
for use in STM16/OC48 applications. It demultiplexes a
single 2.5 Gbits/s input channel to 32 × 78 Mbits/s output
channels. The data and clock outputs on the low speed
interface are GTL compatible, while the high speed data
and clock inputs are CML compatible.
• 1.2 V GTL (Gunning Transceiver Logic) level compatible
data and clock outputs (low speed interface)
• Differential CML (Current-Mode Logic) data and clock
inputs
• High input sensitivity (100 mV for the high speed inputs)
• Boundary Scan Test (BST) at low speed interface, in
accordance with “IEEE Std 1149.1-1990”
• Low power dissipation (typically 1.45 W).
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
OQ2536HP
NAME
DESCRIPTION
VERSION
HLQFP100
plastic heat-dissipating low profile quad flat package; 100 leads; body
14 × 14 × 1.4 mm
SOT470-1
BLOCK DIAGRAM
handbook, full pagewidth
DINQ
CIN
CINQ
54
2.5 Gbits/s
53
622
Mbits/s
1 : 4 DMUX
56
(1)
4×
1 : 8 DMUX
4
75
OQ2536HP
DLOOP
DLOOPQ
CLOOP
CLOOPQ
DIOA
DIOC
65
66
DIVIDE BY 4
60
D0
to
D31
622 MHz
DIVIDE BY 8
78 MHz
68
69
70
72
71
12
ENL
TRST
TMS
TCK
TDI
TDO
CDIV
2.5 GHz
59
32
BAND GAP
REFERENCE 2
31
(2)
29
13, 14, 36,
26, 27, 28, 37, 63, 85,
86
76, 77
11, 38, 39,
62, 88
5
5
GND VDD
7
VCC2
VEE
74
34
VCC1 BGCAP2
(1) See Chapter “Pinning” for D0 to D31 pin numbers.
(2) Pins 1, 8, 17, 22, 25, 29, 33, 35, 40 to 50, 52, 55, 58, 61, 64, 67, 78, 82, 91 and 96.
Fig.1 Block diagram.
1998 Mar 10
78
Mbits/s
57
BST LOGIC
DIN
2
BAND GAP
REFERENCE 1
51
73
BGCAP1 REFC
MGK346
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
PINNING
SYMBOL
PIN
TYPE(1)
DESCRIPTION
GND
1
S
ground
D29
2
O
78 Mbits/s data output channel for D29
D25
3
O
78 Mbits/s data output channel for D25
D21
4
O
78 Mbits/s data output channel for D21
D17
5
O
78 Mbits/s data output channel for D17
D13
6
O
78 Mbits/s data output channel for D13
D9
7
O
78 Mbits/s data output channel for D9
GND
8
S
ground
D5
9
O
78 Mbits/s data output channel for D5
D1
10
O
78 Mbits/s data output channel for D1
VEE
11
S
supply voltage (−4.5 V)
CDIV
12
O
78 MHz clock output
VCC2
13
S
supply voltage (+1.5 V)
VCC2
14
S
supply voltage (+1.5 V)
D28
15
O
78 Mbits/s data output channel for D28
D24
16
O
78 Mbits/s data output channel for D24
GND
17
S
ground
D20
18
O
78 Mbits/s data output channel for D20
D16
19
O
78 Mbits/s data output channel for D16
D12
20
O
78 Mbits/s data output channel for D12
D8
21
O
78 Mbits/s data output channel for D8
GND
22
S
ground
D4
23
O
78 Mbits/s data output channel for D4
D0
24
O
78 Mbits/s data output channel for D0
GND
25
S
ground
VDD
26
I
supply voltage (+3.3 V)
VDD
27
I
supply voltage (+3.3 V)
VDD
28
I
supply voltage (+3.3 V)
GND
29
S
ground
i.c.
30
−
internally connected, to be left open-circuit
DIOC
31
A
cathode of temperature diode array
DIOA
32
A
anode of temperature diode array
GND
33
S
ground
BGCAP2
34
A
pin for connecting external band gap decoupling capacitor (4 × 1 : 8 DMUX)
GND
35
S
ground
VCC2
36
S
supply voltage (+1.5 V)
VCC2
37
S
supply voltage (+1.5 V)
VEE
38
S
supply voltage (−4.5 V)
VEE
39
S
supply voltage (−4.5 V)
GND
40
S
ground
1998 Mar 10
3
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
SYMBOL
PIN
TYPE(1)
GND
41
S
ground
GND
42
S
ground
GND
43
S
ground
GND
44
S
ground
GND
45
S
ground
GND
46
S
ground
GND
47
S
ground
GND
48
S
ground
GND
49
S
ground
GND
50
S
ground
BGCAP1
51
A
pin for connecting external band gap decoupling capacitor (1 : 4 DMUX)
GND
52
S
ground
DINQ
53
I
inverted data input in normal mode
DIN
54
I
data input in normal mode
GND
55
S
ground
CIN
56
I
clock input in normal mode
CINQ
57
I
inverted clock input in normal mode
GND
58
S
ground
CLOOPQ
59
I
inverted clock input from multiplexer IC OQ2535 (loop mode)
CLOOP
60
I
clock input from multiplexer IC OQ2535 (loop mode)
DESCRIPTION
GND
61
S
ground
VEE
62
S
supply voltage (−4.5 V)
VCC2
63
S
supply voltage (+1.5 V)
GND
64
S
ground
DLOOP
65
I
data input from multiplexer IC OQ2535 (loop mode)
DLOOPQ
66
I
inverted data input from multiplexer IC OQ2535 (loop mode)
GND
67
S
ground
TRST
68
I
test RESET input for BST mode (active LOW)
TMS
69
I
test mode select input for BST
TCK
70
I
test clock input for BST mode
TDO
71
O
serial test data output for BST mode
TDI
72
I
serial test data input for BST mode
REFC
73
A
pin for connecting external reference decoupling capacitor (for standard TTL
reference)
VCC1
74
S
supply voltage (+5.0 V)
ENL
75
I
loop mode enable input (active LOW)
VDD
76
I
supply voltage (+3.3 V)
VDD
77
I
supply voltage (+3.3 V)
GND
78
S
ground
D31
79
O
78 Mbits/s data output channel for D31
D27
80
O
78 Mbits/s data output channel for D27
1998 Mar 10
4
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
SYMBOL
PIN
TYPE(1)
D23
81
O
GND
82
S
ground
D19
83
O
78 Mbits/s data output channel for D19
D15
84
O
78 Mbits/s data output channel for D15
DESCRIPTION
78 Mbits/s data output channel for D23
VCC2
85
S
supply voltage (+1.5 V)
VCC2
86
S
supply voltage (+1.5 V)
D11
87
O
78 Mbits/s data output channel for D11
VEE
88
S
supply voltage (−4.5 V)
D7
89
O
78 Mbits/s data output channel for D7
D3
90
O
78 Mbits/s data output channel for D3
GND
91
S
ground
D30
92
O
78 Mbits/s data output channel for D30
D26
93
O
78 Mbits/s data output channel for D26
D22
94
O
78 Mbits/s data output channel for D22
D18
95
O
78 Mbits/s data output channel for D18
GND
96
S
ground
D14
97
O
78 Mbits/s data output channel for D14
D10
98
O
78 Mbits/s data output channel for D10
D6
99
O
78 Mbits/s data output channel for D6
D2
100
O
78 Mbits/s data output channel for D2
Note
1. Pin type abbreviations: O = Output, I = Input, S = power Supply, A = Analog function.
1998 Mar 10
5
Philips Semiconductors
Product specification
77 VDD
76 VDD
78 GND
79 D31
81 D23
80 D27
82 GND
83 D19
84 D15
OQ2536HP
86 VCC2
85 VCC2
88 VEE
87 D11
89 D7
90 D3
91 GND
92 D30
93 D26
94 D22
95 D18
96 GND
97 D14
98 D10
100 D2
handbook, full pagewidth
99 D6
SDH/SONET STM16/OC48 demultiplexer
GND
1
75 ENL
D29
2
74 VCC1
D25
3
73 REFC
D21
4
72 TDI
D17
5
71 TDO
D13
6
70 TCK
D9
7
69 TMS
GND
8
68 TRST
D5
9
67 GND
D1 10
66 DLOOPQ
VEE 11
65 DLOOP
CDIV 12
64 GND
OQ2536HP
VCC2 13
63 VCC2
62 VEE
VCC2 14
D28 15
61 GND
D24 16
60 CLOOP
GND 17
59 CLOOPQ
D20 18
58 GND
D16 19
57 CINQ
D12 20
56 CIN
D8 21
55 GND
GND 22
54 DIN
D4 23
53 DINQ
D0 24
52 GND
51 BGCAP1
Fig.2 Pin configuration.
1998 Mar 10
6
GND 50
GND 49
GND 48
GND 47
GND 46
GND 45
GND 44
GND 43
GND 42
GND 41
GND 40
VEE 39
VEE 38
VCC2 37
VCC2 36
GND 35
BGCAP2 34
GND 33
DIOA 32
DIOC 31
i.c. 30
GND 29
VDD 28
VDD 27
VDD 26
GND 25
MGK345
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
IC. If multiple decoupling capacitors are used for a single
supply node, large distance between the capacitances
should be avoided in order to avoid resonance.
FUNCTIONAL DESCRIPTION
The OQ2536HP is a 32-channel demultiplexer, intended
for use in STM16/OC48 applications. It demultiplexes a
single 2.5 Gbits/s input channel to 32 × 78 Mbits/s output
channels.
To minimize low frequency switching noise in the vicinity of
the OQ2536HP, all power supply lines should be filtered
once by an LC-circuit with a low cutoff frequency
(as shown in the application diagram, Fig.7).
The demultiplexing is performed in two stages.
The 2.5 Gbits/s data channel is first demultiplexed to four
622 Mbits/s data channels. Each of these channels is then
fed to a 1 : 8 demultiplexer to generate 32 × 78 Mbits/s
output channels.
Ground connection
The ground connection on the PCB needs to be a large
copper area fill connected to a common ground plane with
low inductance.
The ENL control input is used for switching between
normal and loop modes. When loop mode is enabled
(ENL = LOW), inputs DLOOP, DLOOPQ, CLOOP and
CLOOPQ are selected. In normal mode (ENL = HIGH),
inputs DIN, DINQ, CIN and CINQ are selected.
RF connections
A coupled stripline or microstrip with an odd mode
characteristic impedance of 50 Ω (nominal value) should
be used for the RF connections on the PCB.
The connections should be kept as short as possible. This
applies to the CML differential line pairs CIN and CINQ,
DIN and DINQ, CLOOP and CLOOPQ, and DLOOP and
DLOOPQ. In addition, the following lines should not vary in
length by more than 5 mm:
The signal applied to CIN and CINQ is a 2.5 GHz
recovered clock signal, e.g. coming from the OQ2541 data
and clock recovery IC. The clock is divided down to
78 MHz, which is used for receive logic timing and is
available as a GTL compatible output at pin CDIV.
High bit rate stage: 1 : 4 DMUX
• CIN, CINQ, DIN and DINQ
The 2.5 Gbits/s data stream is fed into a 1 : 4
demultiplexer to generate four 622 Mbits/s channels.
• DLOOP, DLOOPQ, CLOOP and CLOOPQ.
The input pins DIN, DINQ, DLOOP, DLOOPQ, CIN, CINQ,
CLOOP and CLOOPQ are terminated internally with 50 Ω
resistors to GND.
Interface to receive logic
The 78 Mbits/s interface lines, CDIV and D0 to D31,
should not exceed 50 mm in length. The parasitic
capacitance of these lines should be as small as possible
(less than 3 pF is desirable).
Low bit rate part: 4 × 1 : 8 DMUX
The four 622 Mbits/s output channels coming from the
high bit rate stage are loaded into four 8-bit shift registers.
The 622 MHz clock for these shift registers comes from the
preceding stage.
ESD protection
The 32 bits contained in the shift registers are loaded into
latches and made available on outputs D0 to D31. These
outputs are 1.2 V GTL compatible and have internal 100 Ω
pull up resistors. The 78 MHz clock output, CDIV, has an
internal 50 Ω pull up resistor.
Cooling
All pads are protected by ESD protection diodes, with the
exception of the high frequency inputs DIN, DINQ,
DLOOP, DLOOPQ, CIN, CINQ, CLOOP and CLOOPQ.
In many cases it is necessary to mount a special cooling
device on the package. The thermal resistance from
junction to case, Rth j-c and from junction to ambient, Rth j-a,
are given in Chapter “Thermal characteristics”. Since the
heat-slug in the package is connected to the die, the
cooling device should be electrically isolated.
The first serial data bit coming in at DIN or DLOOP is given
out at pin D31 (MSB) and so on.
The data outputs may not always represent four STM
bytes. This is because the internal load pulse for the output
latches is not synchronized to the STM16 frame.
To calculate if a heatsink is necessary, the maximum
allowed total thermal resistance R is calculated as:
T j – T amb
R th = ----------------------(1)
P tot
Power supply connections
The power supply pins need to be individually decoupled
using chip capacitors mounted as close as possible to the
1998 Mar 10
OQ2536HP
7
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
where:
OQ2536HP
If for instance Rth c-h = 0.5 K/W and Rth j -a = 33 K/W then:
1
1 –1
[ K ⁄ W]
R thh – a ≤  ----------- – ------  – 3.1 ≤ 17.0
(5)
12.5 33
Rth = total thermal resistance from junction to ambient
in the application
Tj = junction temperature
Built in temperature sensor
Tamb = ambient temperature.
As long as Rth is greater than Rth j-a of the OQ2536HP
including environmental conditions like air flow and board
layout, no heatsink is necessary. For example if
Tj = 120 °C, Tamb = 70 °C and Ptot = 1.45 W, then:
( 120 – 70 )
(2)
R th = ----------------------------- = 34.4
[ K ⁄ W]
1.45
Three series-connected diodes have been integrated for
measuring junction temperature. The diode array,
accessed by means of the DIOA (anode) and DIOC
(cathode) pins, has a temperature dependency of
approximately −6 mV/°C. With a diode current of 1 mA,
the voltage will be somewhere in the range 1.7 to 2.5 V,
depending on temperature.
which is more than the worst case Rth j-a = 33 K/W, so no
heatsink is necessary.
Boundary Scan Test (BST) interface
Boundary scan test logic has been implemented for all
digital inputs and outputs on the low frequency interface, in
accordance with “IEEE Std 1149.1-1990”. All scan tests
other than SAMPLE mode are available. The boundary
scan test logic consists of a TAP controller, a BYPASS
register, a 2-bit instruction register, a 32-bit identification
register and a 36-bit boundary scan register (the last two
are combined). The architecture of the TAP controller and
the BYPASS register is in accordance with IEEE
recommendations.
The four command modes, selected be means of the
instruction register, are: EXTEST (00), PRELOAD (01),
IDCODE (10) and BYPASS (11).
All boundary scan test inputs, TDI, TMS, TCK and TRST,
have internal pull up resistors. The maximum test clock
frequency at TCK is 12 MHz.
Another example; if for safety reasons Tj should stay as
low as 110 °C, while Tamb = 85 °C and Ptot = 2 W, then:
( 110 – 85 )
R th = ----------------------------- = 12.5
(3)
[ K ⁄ W]
2.0
In this case extra cooling is needed. The thermal
resistance of the heatsink is calculated as follows:
–1
1
1
R thh – a ≤  -------- – -----------------  – R thj – c – R thc – h
 R th R thj – a 
(4)
where:
Rth h-a = thermal resistance from heatsink to ambient
Rth c-h = thermal resistance from case to heatsink
Rth j-c = thermal resistance from junction to case,
see Chapter “Thermal characteristics”.
Table 1
BST identifier code
VERSION
OQ
2536 (BINARY)
PHILIPS SEMICONDUCTORS
LSB(1)
0001
01
00 1001 1110 1000
0000 0011 101(2)
1
Notes
1. LSB is shifted out first on the TDO pin.
2. The manufacturer’s code was implemented incorrectly. It should have been 0000 0010 101.
1998 Mar 10
8
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
Table 2
BST bit order
BIT NUMBER
SYMBOL
PIN
33 (MSB)
D31
79
32
D27
80
31
D23
81
30
D19
83
29
D15
84
28
D11
87
27
D7
89
26
D3
90
25
D30
92
24
D26
93
23
D22
94
22
D18
95
21
D14
97
20
D10
98
19
D6
99
18
D2
100
17
D29
2
16
D25
3
15
D21
4
14
D17
5
13
D13
6
12
D9
7
11
D5
9
10
D1
10
9
CDIV
12
8
D28
15
7
D24
16
6
D20
18
5
D16
19
4
D12
20
3
D8
21
2
D4
23
1
D0
24
ENL
75
0
(LSB)(1)
Note
1. LSB is shifted out first on the TDO pin.
1998 Mar 10
9
OQ2536HP
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VCC1
supply voltage
−0.5
+6.0
V
VEE
supply voltage
−6.0
+0.5
V
VDD
supply voltage
−0.5
+5.0
V
VCC2
supply voltage
−0.5
+2.0
V
Vn
DC voltage
2.0
V
V
pins 2 to 7, 9, 10, 15, 16, 18 to 21, 23, 24, 79, 80, 81, 83, 84, 87, 89, 0.0
90, 92 to 95 and 97 to 100
In
pins 53, 54, 56, 57, 59, 60, 65 and 66
−1.0
+0.5
pins 68, 69, 70, 72, 73 and 75
−0.5
VCC1 + 0.5 V
pins 30, 34 and 51
VEE − 0.5
0.5
pins 31and 32
VEE − 0.5
VCC1 + 0.5 V
V
DC current
pins 2 to 7, 9, 10, 15, 16, 18 to 21, 23, 24, 79, 80, 81, 83, 84, 87, 89, −
90, 92 to 95, and 97 to 100
15
mA
pin 12
−
30
mA
pins 31 and 32
−
10
mA
pin 71
−
50
mA
Ptot
total power dissipation
−
2.6
W
Tj
junction temperature
−
120
°C
Tstg
storage temperature
−65
+150
°C
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
Rth j-c
thermal resistance from junction to case
Rth j-a
thermal resistance from junction to
ambient
CONDITIONS
VALUE
UNIT
2.6
K/W
airflow = 0 ft/min
33
K/W
airflow = 100 ft/min
28
K/W
airflow = 200 ft/min
25
K/W
airflow = 400 ft/min
22
K/W
airflow = 600 ft/min
20
K/W
see note 1
Note
1. The thermal resistance from junction to ambient is strongly depending on the board design and airflow. The values
given in the table are typical values and are measured on a single sided test board with dimensions of
76 × 114 × 1.6 mm. Better values can be obtained when mounted on multilayer boards with large ground planes.
1998 Mar 10
10
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
DC CHARACTERISTICS
Typical values at Tamb = 25 °C and at typical supply voltages; minimum and maximum values are valid over the entire
ambient temperature range and supply voltage range.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
General
VCC1
supply voltage
4.75
5.0
5.25
V
VEE
supply voltage
−4.75
−4.5
−4.25
V
VDD
supply voltage
3.14
3.3
3.47
V
VCC2
supply voltage
1.1
1.5
1.6
V
ICC1
supply current
−
14
22
mA
IEE
supply current
−
170
215
mA
IDD
supply current
−
100
185
mA
ICC2
supply current
note 1
−
190
525
mA
Ptot
total power dissipation
note 1
−
1.45
2.6
W
Tj
junction temperature
−
−
+120
°C
Tamb
ambient temperature
−40
−
+85
°C
−
−
0.8
V
TTL input: ENL
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
2.0
−
−
V
IIL
LOW-level input current
−90
−
-
µA
IIH
HIGH-level input current
-
−
210
µA
TTL inputs: TDI, TCK, TMS and TRST; note 2
VIL
LOW-level input voltage
−
−
0.4
V
VIH
HIGH-level input voltage
2.0
−
−
V
CML inputs: CIN, CINQ, DIN, DINQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ; note 3
Vi(p-p)
input voltage (peak-to-peak value)
VIO
permitted input offset voltage
VI,IQ
input voltages
Zi
single ended input impedance
50 Ω measurement
system
100
250
500
mV
−25
−
+25
mV
−600
−
+250
mV
for DC signal
−
50
−
Ω
IOL = 4 mA
−
0.3
0.5
V
TTL output: TDO; note 4
VOL
1998 Mar 10
LOW-level output voltage
11
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
SYMBOL
PARAMETER
OQ2536HP
CONDITIONS
IOH = −400 µA
VOH
HIGH-level output voltage
IOZ
output current in high impedance state
MIN.
TYP.
MAX.
UNIT
2.4
4.0
−
V
−
−
1
µA
-
0.3
0.4
V
1.1
1.5
1.6
V
−
2.1
−
V
Outputs: CDIV and D0 to D31; notes 5 and 6
VOL
LOW-level output voltage
VOH
HIGH-level output voltage; note 7
Open outputs
Temperature diode array
∆VDIOA-DIOC diode voltage range(8)
II(d) = 1 mA
Notes
1. Maximum current ICC2 and maximum power dissipation Ptot are worst case figures i.e. data outputs D0 to D31 remain
in LOW state.
2.
TDI, TCK, TMS and TRST are connected via 90 kΩ to VDD.
3. See Fig.3 for symbol definitions.
4. TDO is switched to high impedance state if BST is inactive.
5. Output CDIV has an internal pull-up resistor of 50 Ω to VCC2. Outputs D0 to D31 have internal pull-up resistors of
100 Ω to VCC2.
6. The first serial data bit coming in at DIN or DLOOP is given out at D31 (MSB) and so on.
7. The HIGH-level output voltage depends on the supply voltage VCC2.
8. The temperature diode array can be used to measure the temperature of the die. The temperature dependency of
this voltage is approximately −6 mV/K.
handbook, full pagewidth
CML INPUT
CML OUTPUT
VI(max)
GND
GND
VO(max)
VIQH
VOQH
VOH
VIH
Vi (p-p)
VIQL
VIL
Vo (p-p)
VOQL
VOL
VIO
VO(min)
VI(min)
Fig.3 Logic level symbol definitions for CML.
1998 Mar 10
12
VOO
MGK144
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
TIMING
Typical values at Tamb = 25 °C and at typical supply voltages; minimum and maximum values are valid over the entire
ambient temperature range and supply voltage range.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
CML input timing; note 1; Fig.5
fclk(CIN)
input clock frequency
2.488
−
−
GHz
tsu
input data set-up time
140
−
−
ps
th
input data hold time
80
−
−
ps
SRCIN
clock slew rate
1
−
−
V/ns
77.76
−
MHz
TTL output timing; note 2; Fig.6
fclk(CDIV)
output clock frequency
δCDIV
output clock duty factor
tr(CDIV)
output clock rise time
tf(CDIV)
output clock fall time
tr(D0 to D31)
data out rise time
tf(D0 to D31)
data out fall time
tCDV
tDI
fclk(CDIV) = 2.488 GHz −
-
50
-
%
−
−
2700
ps
−
−
1000
ps
−
−
5100
ps
−
−
1000
ps
clock edge to data valid time
−
−
2700
ps
data invalid time
−
−
2850
ps
Measured between
10% and 90% levels
of full output swing
Notes
1. The specified timing characteristics are applicable in both normal and loop modes.
2. A capacitive load of 15 pF was connected at all outputs. An input reference level of 1 V was used.
VCC2
handbook, halfpage
VCC2
handbook, halfpage
50 Ω
100 Ω
CDIV
D0 to D31
GND
GND
MBK757
MBK756
Fig.4 GTL output circuits.
1998 Mar 10
13
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
Tcy(CIN)
handbook, full pagewidth
50%
CIN
100 mV
DIN
MGK347
tsu
valid data
th
Fig.5 CML input timing.
handbook, full pagewidth
Tcy(CDIV)
CDIV
1.0 V
1.1 V
D0 to D31
0.9 V
MGK348
tDI
tCDV
Fig.6 Output timing.
1998 Mar 10
14
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
APPLICATION INFORMATION
handbook, full pagewidth
DATA AND CLOCK RECOVERY
OQ2541
DQ
D
DIN
54
DINQ
53
CLQ
CL
CINQ
CIN
56
51
ENL
microcontroller
VEE
57
BGCAP1
10 nF
BGCAP2
10 nF
VEE
75
34
73
REFC
33 nF
TDI
TCK
BOUNDARY SCAN
TEST EQUIPMENT
TMS
72
32
70
31
68
(1)
71
CLOOPQ
DLOOP
DLOOPQ
CLOOP
CLOOPQ
(2)
ferrite
bead
VCC2
OQ2536
74
OQ2535 DLOOPQ
MUX
CLOOP
DIOC
69
TRST
TDO
DLOOP
DIOA
VCC1
100
nF ferrite
bead
1 µF
100
nF
1 µF
ferrite
bead
VDD
100
nF
65
66
60
(3)
ferrite
bead
VEE
100
nF
59
(4)
D0 to D31
1 µF
1 µF
GND
12
CDIV
D0 to D31
C78
RECEIVE LOGIC
MGK349
(1)
(2)
(3)
(4)
VCC2 pins 13, 14, 36, 37, 63, 85 and 86 should be connected together, and to the filter network.
VDD pins 26, 27, 28, 76 and 77 should be connected together, and to the filter network.
VEE pins 11, 38, 39, 62 and 8 should be connected together, and to the filter network.
All GND pins (pins 1, 4, 8, 9, 11, 15, 17, 21, 25, 36, 40, 56, 64, 67, 70, 73, 76, 77, 79, 80, 81, 84, 89, 92 to 98 and 100) must be connected directly
to the PCB ground plane.
Fig.7 Application diagram.
1998 Mar 10
15
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
PACKAGE OUTLINE
HLQFP100: plastic heat-dissipating low profile quad flat package;
100 leads; body 14 x 14 x 1.4 mm
SOT470-1
c
y
X
A
51
75
50 Z E
76
e
J
E HE
A A2
w M
(A 3)
A1
bp
θ
Lp
pin 1 index
L
100
detail X
26
1
25
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.20
0.05
1.5
1.3
0.25
0.28
0.16
0.18
0.12
14.1
13.9
14.1
13.9
0.5
HD
HE
J(2)
16.25 16.25 10.15
15.75 15.75 9.15
L
Lp
v
w
y
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
1.15
0.85
7
0o
1.15
0.85
Notes
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
2. Heatsink intrusion 0.0127 maximum.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
97-01-13
SOT470-1
1998 Mar 10
EUROPEAN
PROJECTION
16
o
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
If wave soldering cannot be avoided, the following
conditions must be observed:
SOLDERING
Introduction
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all LQFP
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
1998 Mar 10
OQ2536HP
17
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
OQ2536HP
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Mar 10
18
Philips Semiconductors
Product specification
SDH/SONET STM16/OC48 demultiplexer
NOTES
1998 Mar 10
19
OQ2536HP
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
425102/200/01/pp20
Date of release: 1998 Mar 10
Document order number:
9397 750 01623