Si8540 H I G H - S ID E C URRENT S ENSE A MPLIFIER Features Complete, unidirectional high-side current sense capability 0.2% full-scale accuracy +5 to +36 V supply operation 85 dB power supply rejection 90 µA max supply current 9 µA shutdown current Operating Temperature Range: –40 to +85 °C 5-pin SOT-23 package RoHS-compliant Applications Battery chargers Smart battery packs DC motor control Backup systems Current control applications 5-Pin SOT-23 Ordering Information: See page 12. Description The Si8540 is a unidirectional, 36 V (max), high-side current sense amplifier for use in applications requiring current monitoring and/or control. This device draws bias current from the high-side line to which it is attached, eliminating the need for an external supply. It measures current from 0.1 to 10 A by sensing the voltage across an external sense resistor (or PCB trace) from dc to 20 kHz and can achieve measurement accuracies of 0.2% (typical) at full load. The device output is a current signal proportional to measured current and is easily converted to a scaled voltage using a single external resistor. The Si8540 is available in compact SOT-23 package. Pin Assignments RG1 1 GND 2 SHDN 3 5 RG2 4 OUT SOT-23 Functional Block Diagram RSENSE ILOAD VSOURCE RG2 LOAD RG1 Patents pending Si8540 VOUT ROUT Rev. 1.2 8/13 Copyright © 2013 by Silicon Laboratories Si8540 Si8540 2 Rev. 1.2 Si8540 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4. Typical Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1. Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. Package Outline: SOT-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8. Land Pattern: SOT-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Rev. 1.2 3 Si8540 1. Electrical Specifications Table 1. Absolute Maximum Ratings Parameter Value Unit Voltage at RG1, RG2, SHDN to GND –0.3 to +40 V Differential Input Voltage, RG1 to RG2 ±0.3 V –0.3 to +8 V Current into SHDN, GND, OUT, RG1, RG2 ±50 mA Continuous Power Dissipation (TA = +70 °C) 5-pin SOT23 derate 7.1 mW/°C above +70 °C* 571 mW Operating Temperature Range –40 to +85 °C Junction Temperature, TJMAX Up to +150 °C Voltage at OUT *Note: The device is mounted on a standard PCB with a 100 mm2 copper foil connected to the GND pin, no airflow. Permanent device damage may occur if the absolute maximum ratings are exceeded, and prolonged use at the absolute maximum ratings may affect reliability. It is recommended that the device operate within the limits indicated in Table 2, “DC and AC Characteristics". 4 Rev. 1.2 Si8540 Table 2. DC and AC Characteristics (Unless otherwise specified: VRG1 = +5 to +36 V, RG1 = RG2 = 200, VSENSE = 0 V, TA = –40 to +85 °C) Parameter Operating Voltage Operating Frequency Symbol Test Condition Min Typ Max Unit VRG1 5 — 36 V F 0 20 — kHz Total Input Current IRG1+IRG2 ILOAD = 0 A — 46 90 µA Input Currents IRG1, IRG2 ILOAD = 0 A — 23 45 µA IOS IRG1 – IRG2 — ±0.4 ±1.5 µA — 100 — mV VSENSE = 100 mV — ±0.2 ±1.5 % VRG1 = 10 V, VSENSE = 0 V — 0.5 15 µA VRG1 = 10 V, VSENSE = 3 mV — ±0.5 +10 µA PSR VSENSE = 100 mV — -85 — dB Shutdown Supply Current IRG1+IRG2 VSHDN = 2.4 V — 3.5 9 µA SHDN Input Low Voltage VIL — — 0.3 V SHDN Input Low Current IIL — — 1.0 µA SHDN Input High Voltage VIH 2.4 — — V SHDN Input High Current IIH VSHDN = 2.4 V — — 1.0 µA VOUT VOUT clamped at 8 V 0 — VRG1 – 3.5 (<8) V IOUT = 1.5 mA 1 3 — M VSENSE = 5 mV to 150 mV, ROUT = 2 = k, COUT = 50 pF, 10% to 90% (Note 2) — — 0.4 0.5 — — µs µs VSENSE = 5 to 150 mV, ROUT = 2 k, COUT = 50 pF (Note 2) — — 1 2 — — µs µs For IOUT > 1.5 mA the internal current limitation starts to limit the output current 1.5 — 10 mA Input Current Matching Sense Voltage1 VSENSE OUT Current Accuracy IRG/IOUT No-Load OUT Error Low-Level OUT Error Power-Supply Rejection OUT Output Voltage Range VSHDN = 0 V OUT Output Resistance (Internal) OUT Rise, Fall Time OUT Settling Time to 1% of Final Value Maximum Output Current IOUT Notes: 1. VSENSE is the voltage across the sense resistor. 2. COUT is the load capacitance seen by the OUT pin. Rev. 1.2 5 Si8540 2. Typical Application Schematic VSUPPLY Micro Controller RG1 Current Sense RSENSE System Bus RG2 VOUT ILOAD Bias Controller RLOAD Bias Filter Control Bus VOUT = ILOAD x RSENSE RG1 = RG2 ROUT (R ) G1 Figure 1. Connecting the Si8540 in a Power Control Application 6 Rev. 1.2 Si8540 3. Functional Description The Si8540 is designed to operate over an input common-mode range of 5 to 36 V. Figure 2 shows an example Si8540 application with external sense resistor, RSENSE, external current gain-setting resistors, RG1 and RG2, and output scaling resistor, ROUT. The supply current flowing into the Si8540 inverting and non-inverting inputs (RG1, RG2) is negligible compared to ILOAD and, as a result, has no appreciable effect on measurement accuracy. The internal current sense amplifier measures the differential input voltage, VSENSE, and generates an output current proportional to ILOAD. Resistor ROUT converts this current to a voltage, and its value determines the output signal gain. The Si8540 is placed in a low-power shutdown mode when SHDN is at VIH. RSENSE SOURCE LOAD ILOAD RG1 RG2 RG1 RG2 Si8540 + _ OUT VOUT ROUT Control SHDN IOUT GND Figure 2. Si8540 Application Circuit 3.1. Application Information The Si8540 can sense a wide range of currents with different sense resistor values. Table 3 lists typical operational values. Table 3. Recommended Current Sense Resistor for a Given Full-Scale Load Current Full-scale Load Current ISENSE (A) CurrentSense Resistor RSENSE (m) Gain-Setting Resistors, RG1 = RG2 () 0.1 1000 1 (k) Full-Scale Output Voltage, VOUT (V) 200 5 100 200 5 20 10 5 Output Resistor, ROUT Typical Error at 1, 10 Scale and 100% of Full Factor Load (%) VOUT/ISENSE (V/A) 1% 10% 100% 2.5 25 10 1 0.2 5 2.5 2.5 10 1 0.2 100 2 2 0.4 5 1 0.2 50 2 2 0.2 5 1 0.4 Rev. 1.2 7 Si8540 3.1.1. Selecting RSENSE Selecting RSENSE involves making the best trade-off between power efficiency and accuracy. Low RSENSE values dissipate less power while higher values maximize accuracy. In general, it is best to choose a relatively high value for RSENSE in applications where the measured current is small. For higher current applications, the sense resistor should be able to dissipate the heat from its power loss; otherwise, its value may drift or it may fail open, possibly causing a large differential voltage across RG1 and RG2 that may damage the device. In most applications, RSENSE should have low inductance to reduce the impact of any high-frequency components in the current being measured (low inductance metal film resistors are recommended). Also, note that the Si8540 requires at least 3.5 V of voltage headroom between the voltage at pin RG1 and pin OUT. This voltage headroom decreases as RSENSE increases. A good guideline for determining the maximum value for RSENSE is shown in the following equation: RSENSEmax = (VSOURCE – VOUTmax – 3.5 V)/ILOAD Where: VSOURCE is the high-side voltage VOUTmax is the full-scale output voltage at the OUT pin ILOAD is the current passing through RSENSE measured by the Si8540 3.1.2. Selecting RG1 and RG2 The values of resistors RG1 and RG2 determine the sense amp current-gain. These two resistors must have the same value, and resulting current gain is equal to RSENSE / RG (where RG = RG1 = RG2). The minimum value of RG is determined by the maximum current at the OUT pin (1.5 mA) and by the resistance between the internal current sense amp input and the sense resistor (approximately 0.2 ). As the value of RG is reduced, the input resistance becomes a larger portion of the total gain-setting resistance. This gain error can be compensated by trimming RG or ROUT. A good guideline for determining the maximum value for RG is shown in the following equation: RGmax = (VSENSEmax / 1.5 mA) Where: RGmax is the largest value for RG1 and RG2 VSENSEmax is the value of VSENSE at maximum ILOAD Note that for a given value of VSENSE, a decrease of the RG resistor values causes a corresponding increase in current at the OUT pin. This causes additional power to be dissipated in ROUT rather than in the load, which can reduce efficiency. Note also that mismatches in the currents passing RG1 and RG2 (IOS) together with RG affect the full scale error. This error can be reduced by lowering the values of RG1, RG2 and/or lowering their tolerances. This error can also be reduced by increasing the value of RSENSE. 3.1.3. Choosing ROUT ROUT must be chosen to generate the required full-scale output voltage at the full scale IOUT, which, in turn, is determined by RG1, RG2, and RSENSE. The upper limit of ROUT is determined by the input impedance of the device that it drives. This input impedance should be much larger than ROUT; otherwise, measurement accuracy will be degraded. A good guideline for choosing the value of ROUT is shown in the following equation: (VOUTfullscale x RG) / (ILOAD x RSENSE) 8 Rev. 1.2 Si8540 4. Typical Performance Data 8 (ROUT = 1 k, COUT = 50 pF, RG1 = RG2 = 10 ) Ioperating (A) +85°C 6 +25°C 4 V SE NS E 5 m V/div -40°C 2 V OUT 500 mV/div 0 10 µs/div 5 15 25 35 Figure 6. Transient Response 2 Supply Voltage (V) Figure 3. Supply Current vs. Supply Voltage (ROUT = 2 k, COUT = 50 pF, RG1 = RG2 = 200 , VSENSE = 100 mV) (ROUT = 2 k, COUT = 50 pF, RG1 = RG2 = 200 ) SHDN 1.0 V/ div V SE NS E 50 m V/div OUT 0.5 V/ div V OUT 500 mV/div 1 µs/div Figure 7. Startup Delay 10 µs/div Figure 4. Transient Response 1 0.5 % 8 0.4 % VRG = 36 V ISHUT DOW N (µA) VRG = 5 V +85 °C 6 0.3 % +25 °C 0.2 % 4 -40 °C 0.1 % 2 0.0 % -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temp (°C) 0 5 10 15 20 25 30 35 Figure 8. Output Error vs. Temperature V SU PPLY (V) Figure 5. Shutdown Supply Current vs Supply Voltage Rev. 1.2 9 Si8540 0.5% 1.0% +8 5 °C 0.4% 0.8% 0.3% 0.6% 0.2% +25 °C 0.1% -4 0 °C 0.4% 0.2% 0.0% 0 0.0% 5 10 15 20 VSUPPLY (V) 25 30 35 80 120 160 V SENSE (mV) Figure 9. Output Error vs. Supply Voltage 10 40 Figure 10. Output Error vs. Sense Voltage Rev. 1.2 Si8540 5. Pin Descriptions RG1 1 GND 2 SHDN 3 5 RG2 4 OUT SOT-23 Figure 11. Pin Configuration Table 4. Pin Descriptions Pin Number Name Description SOT23 1 RG1 Power-side input. 2 GND Ground. 3 SHDN 4 OUT Current output. 5 RG2 Load-side input. Shutdown input. Ground for normal operation. High voltage for shutdown. Rev. 1.2 11 Si8540 6. Ordering Guide Ordering Part #1 Temperature Range Package Si8540-B-FW –40 to +85 °C SOT-232 Notes: 1. Tape and reel options are specified by adding an “R” suffix to the ordering part number. Example: “Si8450-B-FWR” indicates the SOT-23 package option in a tape and reel carrier. 2. Moisture sensitivity level (MSL) is (MSL2A) for SOT-23 package with peak reflow temperature of (260 °C) according to JEDEC industry-standard classifications. 12 Rev. 1.2 Si8540 6.1. Device Marking 6.1.1. SOT-23 Package Top Mark 6.1.2. Top Marking Explanation Line 1 Marking: Manufacturing trace code R = Device revision (B) TTT = Assembly trace code Rev. 1.2 13 Si8540 7. Package Outline: SOT-23 Figure 12 illustrates the package details for the SOT-23. Table 5 lists the values for the dimensions shown in the illustration. Figure 12. SOT-23 Package Table 5. SOT-23 Package Diagram Dimensions Dimension Min Max Dimension A — 1.45 E1 A1 0.00 0.15 L A2 0.90 1.30 L2 Min Max 1.90 BSC 0.30 0.60 0.25 BSC b 0.30 0.50 θ c 0.08 0.20 aaa 0.15 0° 8° D 2.90 BSC bbb 0.20 E 2.80 BSC ccc 0.10 E1 1.60 BSC ddd 0.20 e 0.95 BSC Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-178, Variation AA. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components. 14 Rev. 1.2 Si8540 8. Land Pattern: SOT-23 Figure 13 illustrates the recommended land pattern details for the SOT-23 device. Table 6 lists the values for the dimensions shown in the illustration. Figure 13. SOT-23 Land Pattern Table 6. SOT-23 Land Pattern Dimensions Dimension (mm) C 2.70 E 0.95 X 1.05 Y 0.60 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Card Assembly 5. A No-Clean, Type-3 solder paste is recommended. 6. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components. Rev. 1.2 15 Si8540 DOCUMENT CHANGE LIST Revision 2.5 (July 2007 Integration Associates) to Revision 1.0 (March 2010 Silicon Laboratories) Reformatted document from IA2410 and renamed Si8540. Updated " Functional Block Diagram" on page 1. Updated " Description" on page 1. Updated Table 2 on page 5. OUT current accuracy changed from ±1 to ±1.5%. (max) OUT Error changed from 5 to 15 µA (max) Low-Level OUT Error changed from ±5 to ±10 µA (max) Temperature output error test conditions note updated to include temperature range of –40 to TBD° C. No-Load Updated "3. Functional Description" on page 7. Updated "3.1.1. Selecting RSENSE" on page 8. Updated "3.1.2. Selecting RG1 and RG2" on page 8. Updated "3.1.3. Choosing ROUT" on page 8. Removed temperature sensing function throughout. Added recommended PCB Land Pattern sections. Reformatted document from “IA2410 Rev 2.5” (Integration Associates) and renamed and rereleased as “Si8540 Rev 1.0” (which obsoletes the previous preliminary internal revision 2.6). Revision 1.0 to Revision 1.1 MSL for the SOT-23 package improved to MSL2A (see "6. Ordering Guide" on page 12). Added "6.1. Device Marking" on page 13. Revision 1.1 to Revision 1.2 16 Removed SOIC-8 package throughout document. Rev. 1.2 Si8540 NOTES: Rev. 1.2 17 Si8540 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. 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