Si5355 A N Y - F REQUENCY 1–200 MH Z Q UAD F REQUENCY 8-O UTPUT C LOCK G ENERATOR Features Generates any frequency from 1 to 200 MHz on each of the 4 output banks Eight CMOS clock outputs Guaranteed 0 ppm frequency synthesis error for any combination of frequencies 25 or 27 MHz xtal or 5–200 MHz input clk Five programmable control pins (output enable, frequency select, reset) Separate OEB pins to disable individual banks or all outputs Loss of signal output Low 50 ps (typ) pk-pk period jitter Phase jitter: 2 ps rms 12 kHz–20 MHz Excellent PSRR performance eliminates need for external power supply filtering Low power: 45 mA (core) Core VDD: 1.8, 2.5, or 3.3 V Separate VDDO for each bank of outputs: 1.8, 2.5, or 3.3 V Small size: 4x4 mm 24-QFN Industrial temperature range: –40 to +85 °C Custom versions available using ClockBuilder™ web utility Samples available in 2 weeks Ordering Information: See page 17. Pin Assignments Applications GND CLK0 CLK1 VDDOA P3 23 22 21 20 19 1 18 CLK2 XB 2 17 CLK3 P1 3 16 VDDOB GND GND 4 15 VDDOC P4 5 14 CLK4 P5 6 7 8 9 10 11 12 P2 CLKIN CLK6 The Si5355 is a highly flexible clock generator capable of synthesizing four completely non-integer related frequencies up to 200 MHz. The device has four banks of outputs with each bank supporting two CMOS outputs at the same frequency. Using Silicon Laboratories' patented MultiSynth fractional divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis error regardless of configuration, enabling the replacement of multiple clock ICs and crystal oscillators with a single device. Through a flexible web configuration utility called ClockBuilder™ (www.silabs.com/ClockBuilder), factory-customized pincontrolled Si5355 devices are available in two weeks without minimum order quantity restrictions. The Si5355 supports up to three independent, pin-selectable device configurations, enabling one device to replace three separate clock ICs. 24 XA VDDOD Description Top View CLK7 Storage Switches/routers Computing Servers OC-3/OC-12 line cards VDD LOS Printers Audio/video Networking Communications VDD 13 CLK5 Functional Block Diagram Rev. 1.1 1/13 Copyright © 2013 by Silicon Laboratories Si5355 Si5355 2 Rev. 1.1 Si5355 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1. Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.2. Breakthrough MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3. Input and Output Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4. Multi-Function Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6. Frequency Select/Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.7. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.8. CMOS Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.10. Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.11. ClockBuilder Web-Customization Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1. Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.1. Si5355 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Rev. 1.1 3 Si5355 1. Electrical Specifications Table 1. Recommended Operating Conditions (VDD = 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Units Ambient Temperature TA –40 — 85 oC Core Supply Voltage VDD 2.97 3.3 3.63 V 2.25 2.5 2.75 1.71 1.8 1.98 1.71 — 3.63 Output Buffer Supply Voltage VDDO V Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. Table 2. DC Characteristics (VDD = 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Core Supply Current Output Buffer Supply Current High Level Input Voltage Low Level Input Voltage Symbol Test Condition Min Typ Max Units IDD 100 MHz on all outputs, 25 MHz refclk — 45 60 mA IDDOx CMOS, 50 MHz 15 pF load — 6 9 mA CMOS, 200 MHz 3.3 V VDD0 — 13 18 mA CMOS, 200 MHz 2.5 V — 10 14 mA CMOS, 200 MHz 1.8 V — 7 10 mA CLKIN, P1 0.8 x VDD — 3.63 V P4, P5 0.85 — 1.3 V P2, P3 1.6 — 3.63 V CLKIN, P1, P2, P3 –0.2 — 0.2 x VDD V P4,P5 — — 0.3 V VIH VIL Clock Output High Level Output Voltage VOH Pins: CLK0-7 IOH = –4 mA VDDO – 0.3 — — V Clock Output Low Level Output Voltage VOL Pins: CLK0-7 IOL = +4 mA — — 0.3 V VOLLOS Pin: LOS IOL = +3 mA 0 — 0.4 V — 20 — k LOS Low Level Output Voltage Pn Input Resistance 4 RIN Rev. 1.1 Si5355 Table 3. AC Characteristics (VDD = 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Units 5 — 200 MHz 20–80% VDD — — 2.3 ns 10–90% VDD — — 4 ns Input tr/tf within specified limits shown above 40 — 60 % Input Clock Clock Input Frequency Clock Input Rise/Fall Time FIN TR/TF Clock Input Duty Cycle DC Clock Input Capacitance CIN — 2 — pF FO 1 — 200 MHz 0 0 1 ppb — — 15 pF Output Clocks Clock Output Frequency Clock Output Frequency Synthesis Resolution Output Load Capacitance FRES See "3.3. Input and Output Frequency Configuration" on page 10 CL Clock Output Rise/Fall Time TR/TF 20 to 80% VDD, CL = 15 pF — — 2.0 ns Clock Output Rise/Fall Time TR/TF 20 to 80% VDD, CL = 2 pF — 0.45 0.85 ns 45 50 55 % — — 2 ms Clock Output Duty Cycle DC Powerup Time TPU Output Enable Time TOEB — — 10 µs Reset Minimum Pulse Width TRESET — — 200 ns Output-Output Skew TSKEW Outputs at same frequency, fOUT > 5 MHz –150 — +150 ps Period Jitter JPPKPK 10000 cycles* — 50 75 ps pk-pk Cycle-Cycle Jitter* JCCPK 10000 cycles* — 40 70 ps pk Phase Jitter JPH 12 kHz to 20 MHz — 2 — ps rms PLL Loop Bandwidth FBW — 1.6 — MHz tLOS — 2.6 5 µs CLKIN Loss of Signal Deassert Time tLOS_b 0.01 0.2 1 µs LOS Rise/Fall Time (20–80%) TR/TF — — 10 ns POR to output clock valid Interrupt Status Timing CLKIN Loss of Signal Assert Time CL < 10 pF, pullup < 1 k *Note: Measured in accordance to JEDEC Standard 65. Rev. 1.1 5 Si5355 Table 4. Crystal Specifications Parameter Symbol Test Condition Min Typ Max Units FXTAL Option 1 — 25 — MHz Option 2 — 27 — MHz cL (supported)* 11 12 13 pF cL (recommended) 17 18 19 pF CO — — 5 pF 25 MHz — — 100 27 MHz — — 75 100 — — µW Crystal Frequency Load Capacitance (on-chip differential) Crystal Output Capacitance Equivalent Series Resistance ESR Crystal Drive Level Rating dL *Note: See "AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices" for how to accommodate a 12 pF crystal CL. Table 5. Thermal Conditions Parameter Symbol Test Condition Value Units Thermal Resistance Junction to Ambient JA Still Air 37 oC/W Thermal Resistance Junction to Case JC Still Air 25 o C/W Table 6. Absolute Maximum Ratings1,2,3,4 Parameter Symbol Rating Units VDD –0.5 to 3.8 V Input Voltage Range (all pins except pins 1,2,5,6) VI –0.5 to 3.8 V Input Voltage Range (pins 1,2,5,6) VI2 –0.5 to 1.3 V Output Voltage Range VO –0.5 to (VDD + 0.3) V TJ –55 to +150 oC HBM 2.5 kV CDM 550 V MM 175 V Supply Voltage Range Junction Temperature ESD Tolerance LU Latch-up Tolerance Soldering Temperature (Pb-free profile)5 JESD78 Compliant TPEAK 260 TP 20–40 Soldering Temperature Time at TPEAK (Pb-free profile)5 o C sec Notes: 1. Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. 24-QFN package is RoHS compliant. 3. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx. 4. Moisture sensitivity level is MSL3. 5. The device is compliant with JEDEC J-STD-020. 6 Rev. 1.1 Si5355 2. Typical Application Circuit +3.3 V 0.1 uF Power Supply Decoupling Capacitors (1 per VDD or VDDOx pin) 4-Port Ethernet Switch/Router 1 2 +3.3V 4 VDDOC XA XB CLK0 CLKIN CLK1 1k 3 12 19 Programmable Input Pins Rse 5 Rse 6 Rsh Note: See section 3.1 for information on selecting Rse and Rsh. CLK2 LOS CLK3 Si5355 P1 CLK4 P2 CLK5 P3 CLK6 CLK7 P4 25 25 25 25 22 21 18 17 MHz MHz MHz MHz Ethernet Ethernet PHY Ethernet PHY Ethernet PHY PHY 14 13 10 9 x x 125 MHz 33/66 MHz P5 Rsh GND 8 GND Loss Of Signal 11 VDDOD 15 VDDOB 16 VDDOA 25 MHz XTAL 20 VDD 24 VDD 7 23 23 MCU/ Processor PAD PAD Ethernet Switch Laser Printer +3.3 V 0.1 uF Power Supply Decoupling Capacitors (1 per VDD or VDDOx pin) 1 2 4 XA 125 MHz XB CLK0 CLKIN CLK1 CLK2 +3.3V CLK3 1k Si5355 3 12 Programmable Input Pins Note: See section 3.1 for information on selecting Rse and Rsh. 19 Rse 5 Rse 6 Rsh Rsh Processor DDR Memory CLK4 CLK5 LOS CLK6 P1 CLK7 Print Head 22 21 18 17 14 13 10 9 x 48 MHz Paper Tray x 66/100 MHz x Key Pad x P2 35.788 MHz P3 P4 Touchscreen Controller P5 23 23 GND 8 GND Loss Of Signal USB Controller VDDOD VDDOB 15 11 VDDOC 25 MHz XTAL 20 16 VDD 24 VDD 7 VDDOA Ethernet PHY LCD Screen PAD PAD Rev. 1.1 7 Si5355 3. Functional Description Figure 1. Si5355 Functional Block Diagram 3.1. Input Configuration The Si5355 input can be driven from either an external crystal or a reference clock. Reference selection is made when the device configuration is specified using the ClockBuilder™ web-based utility available at www.silabs.com/ ClockBuilder. If the crystal input option is used, the Si5355 operates as a free-running clock generator. In this mode of operation the device requires a low-cost 25 or 27 MHz fundamental mode crystal connected across XA and XB as shown in Figure 2. Given the Si5355’s frequency flexibility, the same 25 or 27 MHz crystal can be reused to generate any combination of output frequencies. Custom frequency crystals are not required. The Si5355 integrates the crystal load capacitors on-chip to reduce external component count. The crystal should be placed very close to the device to minimize stray capacitance. To ensure stable oscillation, the recommended crystal specifications provided in Table 4 on page 6 must be followed. See AN360 for additional details regarding crystal recommendations. Si5355 XA XTAL XB Figure 2. Connecting an XTAL to the Si5355 For synchronous timing applications, the Si5355 can lock to a 5 to 200 MHz CMOS reference clock. A typical interface circuit is shown in Figure 3. A series termination resistor matching the driver’s output impedance to the impedance of the transmission line is recommended to reduce reflections. Si5355 Rs 50 CLKIN Figure 3. Interfacing CMOS Reference Clocks to the Si5355 8 Rev. 1.1 Si5355 Control input signals to P4 and P5 cannot exceed 1.3 V, yet also must meet the VOH and VOL specifications outlined in Table 2 on page 4. When these inputs are driven from CMOS sources, a resistive attenuator as shown in the Typical Application Circuits must be used. Suggested standard 1% resistor values for Rse and Rsh are shown in Table 7. Table 7. 1% Resistor Values CMOS Level Rse () Rsh () 1.8 V 1000 1580 2.5 V 1960 1580 3.3 V 3090 1580 3.2. Breakthrough MultiSynth Technology Next-generation timing architectures require a wide range of frequencies which are often non-integer related. Traditional clock architectures address this by using a combination of single PLL ICs, 4-PLL ICs and discrete XOs, often at the expense of BOM complexity and power. The Si5355 uses patented MultiSynth technology to dramatically simplify timing architectures by integrating the frequency synthesis capability of 4 phase-locked loops (PLLs) in a single device, greatly minimizing size and power requirements versus traditional solutions. Based on a fractional-N PLL, the heart of the architecture is a low phase noise, high-frequency VCO. The VCO supplies a high frequency output clock to the MultiSynth block on each of the four independent output paths. Each MultiSynth operates as a high-speed fractional divider with Silicon Laboratories' proprietary phase error correction to divide down the VCO clock to the required output frequency with very low jitter. The first stage of the MultiSynth architecture is a fractional-N divider which switches seamlessly between the two closest integer divider values to produce the exact output clock frequency with 0 ppm error. To eliminate phase error generated by this process, MultiSynth calculates the relative phase difference between the clock produced by the fractional-N divider and the desired output clock and dynamically adjusts the phase to match the ideal clock waveform. This novel approach makes it possible to generate any output clock frequency without sacrificing jitter performance. Based on this architecture, the output of each MultiSynth can produce any frequency from 1 to 200 MHz. MultiSynth fVCO Fractional-N Divider Phase Adjust fOUT Phase Error Calculator Divider Select (DIV1, DIV2) Figure 4. Silicon Labs' MultiSynth Technology Rev. 1.1 9 Si5355 3.3. Input and Output Frequency Configuration The Si5355 utilizes a single PLL-based architecture, four independent MultiSynth fractional output dividers, and a MultiSynth fractional feedback divider such that a single device provides the clock generation capability of 4 independent PLLs. Unlike competitive multi-PLL solutions, the Si5355 can generate four unique non-integer related output frequencies with 0 ppm frequency error for any combination of output frequencies. In addition, any combination of output frequencies can be generated from a single reference frequency without having to change the crystal or reference clock frequency between frequency configurations. The Si5355 frequency configuration is set when the device configuration is specified using the ClockBuilder webbased utility available at www.silabs.com/ClockBuilder. Any combination of output frequencies ranging from 1 to 200 MHz can be configured on each of the device outputs. Up to three unique device configurations can be specified in a single device, enabling the Si5355 to replace 3 different clock generators. 3.4. Multi-Function Control Inputs The Si5355 supports 5 user-defined input pins (pins 3, 5, 6, 12, 19) that are customizable to support the functions listed below. The pinout of each device is customized using the ClockBuilder utility. This enables the device to be custom tailored to a specific application. Each of the different functions is described in Table 8. Table 8. Multi-Function Control Inputs Description Pin Function OEB_ALL OEB_A OEB_B OEB_C OEB_D FS0 FS1 RESET 10 Description Output Enable All. All outputs enabled when low. Output Enable Bank A. CLK0/1 enabled when low. Output Enable Bank B. CLK2/3 enabled when low. Output Enable Bank C. CLK4/5 enabled when low. Output Enable Bank D. CLK6/7 enabled when low. Frequency Select. Selects active device frequency plan from factoryconfigured profiles. Frequency Select. Selects active device frequency plan from factoryconfigured profiles. Reset. Device reset required to change FS[1:0] pin setting. Rev. 1.1 Assignable Pin Name P1, P2, P3, P4, or P5 P1, P2, P3, P4, or P5 P1, P2, P3, P4, or P5 P1, P2, P3, P4, or P5 P1, P2, P3, P4, or P5 P2 P3 P1, P3, P4, P5 Si5355 3.5. Output Enable Each of the device’s four banks of CMOS clock outputs can be individually disabled using OEB_A, OEB_B, OEB_C, and OEB_D for CLK0/1, CLK2/3, CLK4/5, and CLK6/7, respectively. Alternatively, all clock outputs can be disabled using the master output enable OEB_ALL. When a Si5355 clock output bank is disabled, both outputs are driven to an active low state. When one or more banks of clock outputs are enabled or disabled, clock start and stop transitions are handled glitchlessly. 3.6. Frequency Select/Device Reset The device frequency plan is customized using the ClockBuilder web utility. The Si5355 optionally supports up to three unique, pin-selectable configurations per device, enabling one device to replace up to three separate clock ICs. To select a particular frequency plan, set the FS pins as outlined below: For custom Si5355 devices configured to support two frequency plans, the FS1 pin should be set as shown in Table 9: Table 9. FS1 Pin Logic for 2 Profile Devices FS1 Profile 0 1 1 2 For custom Si5355 devices configured to support three frequency plans, the FS1 and FS0 pins should be set as shown in Table 10: Table 10. FS1/FS0 Pin Logic for 3 Profile Devices FS1 FS0 Profile 0 0 Reserved 0 1 1 1 0 2 1 1 3 If a change is made to the FS pin settings, the device reset pin (RESET) must be held high for the minimum pulse width specified in Table 3 on page 5 to change the device configuration. The output clocks will be momentarily squelched until the device begins operation with the new frequency plan. If the RESET pin is not selected in ClockBuilder as one of the five programmable pins, a power-on reset must be applied for an FS pin change to take effect. 3.7. Loss-of-Signal Alarm The Si5355 includes an interrupt pin that monitors for both loss of PLL lock (LOL) and loss of input signal (LOS) conditions. The LOS pin is asserted whenever LOL or LOS is true. The LOS condition occurs when there is no input clock to the device. When an input clock is removed, the LOS pin will assert, and the output may drift up to 5%. The LOL condition occurs when there is a reference present but it is off in frequency by a significant amount. In this condition, the LOS pin will assert and the output will be disabled. When the input clock with an appropriate frequency is reapplied, the LOS pin will de-assert. Note that the LOS pin is an open-drain output. Rev. 1.1 11 Si5355 3.8. CMOS Output Drivers The Si5355 has 4 banks of outputs with each bank comprised of 2 clocks for a total of 8 CMOS outputs per device. Each of the output banks can operate from a different VDDO supply (1.8 V, 2.5 V, 3.3 V), simplifying usage in mixed supply applications. All clock outputs between 1 and 200 MHz are in-phase with minimal output-to-output skew (see Table 3 on page 5 for specification). When an output bank is disabled using any of the OEB functions, the clock outputs are stopped low. The CMOS output driver has a controlled impedance in the range of 42 to 50 which includes an internal 22 series resistor. An external series resistor is not needed when driving 50 traces. If higher impedance traces are used then a series resistor may be added. A typical configuration is shown in Figure 5. Si5355 +1.8V, +2.5V, +3.3V VDDOA Bank A MultiSynth CLK0 50 CLK1 50 PLL +1.8V, +2.5V, +3.3V VDDOB Bank B MultiSynth CLK2 50 CLK3 50 +1.8V, +2.5V, +3.3V VDDOC Bank C MultiSynth CLK4 50 CLK5 50 +1.8V, +2.5V, +3.3V VDDOD Bank D MultiSynth CLK6 CLK7 Figure 5. CMOS Output Driver Configuration 12 Rev. 1.1 50 50 Si5355 3.9. Jitter Performance The Si5355 provides consistently low jitter for any combination of output frequencies. The device leverages a low phase noise single PLL architecture and Silicon Laboratories’ patented MultiSynth fractional output divider technology to deliver excellent jitter performance guaranteed across process, temperature, and voltage. The Si5355 provides superior performance to conventional multi-PLL solutions which may suffer from degraded jitter performance depending on frequency plan and the number of active PLLs. 3.10. Power Supply Considerations Additive Jitter (ps pk-pk) The Si5355 has 2 core supply voltage pins (VDD) and 4 clock output bank supply voltage pins (VDDOA–VDDOD), enabling the device to be used in mixed supply applications. The Si5355 does not require ferrite beads for power supply filtering. The device has extensive on-chip power supply regulation to minimize the impact of power supply noise on output jitter. Figure 6 is a curve of additive phase jitter with power supply noise. Note that even when a significant amount of noise is applied to the device power supply, additive phase jitter is still very small. 10 9 8 7 6 5 4 3 2 1 0 0.0001 VDDO VDD 0.001 0.01 0.1 1 Modulation Frequency (MHz) Figure 6. Peak-to-Peak Additive Phase Jitter from 100 mV Sine Wave on Supply 3.11. ClockBuilder Web-Customization Utility ClockBuilder is a web-based utility available at www.silabs.com/ClockBuilder that allows hardware designers to tailor the Si5355’s flexible clock architecture to meet any application-specific requirements and order custom clock samples. Through a simple point-and-click interface, users can specify any combination of input frequency and output frequencies and generate a custom part number for each application-specific configuration. There are no minimum order quantity restrictions. ClockBuilder enables mass customization of clock generators. This allows a broader range of applications to take advantage of using application-specific pin controlled clocks, simplifying design while eliminating the firmware development required by traditional I2C-programmable clock generators. Based on Silicon Labs’ patented MultiSynth technology, the device PLL output frequency is constant and all clock output frequencies are synthesized by the four MultiSynth fractional dividers. All PLL parameters, including divider settings, VCO frequency, loop bandwidth, charge pump current, and phase margin are internally set by the device during the configuration process. This ensures optimized jitter performance and loop stability while simplifying design. Rev. 1.1 13 Si5355 4. Pin Descriptions VDD GND CLK0 CLK1 VDDOA P3 Top View 24 23 22 21 20 19 XA 1 18 CLK2 XB 2 17 CLK3 P1 3 16 VDDOB CLKIN 4 15 VDDOC P4 5 14 CLK4 P5 6 7 8 9 10 11 12 VDD LOS CLK7 CLK6 VDDOD P2 GND GND 13 CLK5 Note: Center pad must be tied to GND for normal operation. Table 11. Si5355 Pin Descriptions Pin # Pin Name 14 I/O Description 1 XA I External Crystal. If a 25 or 27 MHz crystal is used as the device frequency reference, connect it across XA and XB. If an input clock is used on pin 4, this pin should be tied to GND. 2 XB I External Crystal. If a 25 or 27 MHz crystal is used as the device frequency reference, connect it across XA and XB. If an input clock is used on pin 4, this pin should be tied to GND. 3 P1 I Multi-Function Input (3.3 V Tolerant). This pin functions as a multi-function input pin. The pin function (OEB_ALL, OEB_A, OEB_B, OEB_C, OEB_D, or Reset) is user-selectable at time of configuration using the ClockBuilder configuration utility. 4 CLKIN I Single-Ended Input Clock. If a single-ended clock is used as the device frequency reference, connect it to this pin. This pin functions as a high-impedance input for CMOS clock signals. The input should be dc coupled. If a crystal is used as the device frequency reference, this pin should be tied to GND. Rev. 1.1 Si5355 Table 11. Si5355 Pin Descriptions (Continued) 5 P4 I Multi-Function Input. This pin functions as a multi-function input pin. The pin function (OEB_ALL, OEB_A, OEB_B, OEB_C, OEB_D, or Reset) is user-selectable at time of configuration using the ClockBuilder configuration utility. A resistor voltage divider is required when controlled by a signal greater than 1.3 V. See “2. Typical Application Circuit” for details. 6 P5 I Multi-Function Input. This pin functions as a multi-function input pin. The pin function (OEB_ALL, OEB_A, OEB_B, OEB_C, OEB_D, or Reset) is user-selectable at time of configuration using the ClockBuilder configuration utility. A resistor voltage divider is required when controlled by a signal greater than 1.3 V. See “2. Typical Application Circuit” for details. 7 VDD 8 LOS O Loss of Signal. A typical pullup resistor of 1–4 k should be used on this pin. This pin functions as an input clock signal status pin. 0 = no LOS or LOL condition 1 = LOS or LOL condition This pin is open drain and requires an external >1 k pullup resistor. 9 CLK7 O Output Clock 7. CMOS output clock. If unused, this pin must be left floating. 10 CLK6 O Output Clock 6. CMOS output clock. If unused, this pin must be left floating. 11 VDDOD 12 P2 I Multi-Function Input (3.3 V Tolerant). This pin functions as a multi-function input pin. The pin function (OEB_ALL, OEB_A, OEB_B, OEB_C, OEB_D, or Frequency Select) is user-selectable at time of configuration using the ClockBuilder configuration utility 13 CLK5 O Output Clock 5. CMOS output clock. If unused, this pin must be left floating. 14 CLK4 O Output Clock 4. CMOS output clock. If unused, this pin must be left floating. 15 VDDOC VDD Clock Output Bank C Supply Voltage. Power supply for clock outputs 4 and 5. May be operated from a 1.8, 2.5 or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK4/5 are not used, this pin must be tied to VDD or a voltage rail of at least 1.5 V. 16 VDDOB VDD Clock Output Bank B Supply Voltage. Power supply for clock outputs 2 and 3. May be operated from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK2/3 are not used, this pin must be tied to VDD or a voltage rail of at least 1.5 V. VDD Core Supply Voltage. The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. VDD Clock Output Bank D Supply Voltage. Power supply for clock outputs 6 and 7. May be operated from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK6/7 are not used, this pin must be tied to VDD or a voltage rail of at least 1.5 V. Rev. 1.1 15 Si5355 Table 11. Si5355 Pin Descriptions (Continued) 17 CLK3 O Output Clock 3. CMOS output clock. If unused, this pin must be left floating. 18 CLK2 O Output Clock 2. CMOS output clock. If unused, this pin must be left floating. 19 P3 I Multi-Function Input (3.3 V Tolerant). This pin functions as a multi-function input pin. The pin function (OEB_ALL, OEB_A, OEB_B, OEB_C, OEB_D, Frequency Select, or Reset) is user-selectable at time of configuration using the ClockBuilder configuration utility 20 VDDOA 21 CLK1 O Output Clock 1. CMOS output clock. If unused, this pin must be left floating. 22 CLK0 O Output Clock 0. CMOS output clock. If unused, this pin must be left floating. 23 GND GND Ground. Must be connected to system ground. Minimize the ground path impedance for optimal performance of the device. 24 VDD VDD Core Supply Voltage. The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. GND PAD GND GND Ground Pad. This is the large pad in the center of the package. See"7. Recommended PCB Layout" on page 19 for the PCB pad sizes and ground via requirements. The device will not function unless the ground pad is properly connected to a ground plane on the PCB. 16 VDD Clock Output Bank A Supply Voltage. Power supply for clock outputs 0 and 1. May be operated from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK0/1 are not used, this pin must be tied to VDD or a voltage rail of at least 1.5 V. Rev. 1.1 Si5355 5. Ordering Guide Use the ClockBuilder web-based utility available at www.silabs.com/ClockBuilder to specify a unique Si5355 device configuration. ClockBuilder assigns a unique 5-digit code for each unique device configuration and creates an orderable part number. The utility may also be used to order samples, place production orders and look up existing part numbers. In addition, ClockBuilder generates a data sheet addendum for each unique part number that summarizes the device input frequency, output frequencies and other configuration parameters for that specific part number. Si5355A Bxxxxx G M R R = tape & reel Blank = trays (or other) Contact your Silicon Labs sales representative for details regarding shipment media. M = RoHS6, Pb-free QFN Any-Frequency 1–200 MHz Quad Frequency 8-Output Clock Generator G = –40 to +85 oC B = product revision B xxxxx = 5-digit custom code assigned to each unique device configuration by ClockBuilder 5.1. Evaluation Board Si5356 EVB Evaluation Board for Si5356 and Si5355 Rev. 1.1 17 Si5355 6. Package Outline: 24-Lead QFN Figure 7. 24-Lead Quad Flat No-Lead (QFN) Table 12. Package Dimensions Dimension Min Nom Max A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 4.00 BSC. 2.35 2.50 e 0.50 BSC. E 4.00 BSC. 2.65 E2 2.35 2.50 2.65 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 5. J-STD-020 MSL rating: MSL3. 6. Terminal base alloy: Cu. 7. Terminal plating/grid array material: Au/NiPd. 8. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx. 18 Rev. 1.1 Si5355 7. Recommended PCB Layout Table 13. PCB Land Pattern Dimension Min Nom Max P1 2.50 2.55 2.60 P2 2.50 2.55 2.60 X1 0.20 0.25 0.30 Y1 0.75 0.80 0.85 C1 3.90 C2 3.90 E 0.50 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. Connect the center ground pad to a ground plane with no less than five vias. These 5 vias should have a length of no more than 20 mils to the ground plane. Via drill size should be no smaller than 10 mils. A longer distance to the ground plane is allowed if more vias are used to keep the inductance from increasing. Solder Mask Design 5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. The stencil thickness should be 0.125 mm (5 mils). 8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad. Card Assembly 10. A No-Clean, Type-3 solder paste is recommended. 11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.1 19 Si5355 8. Top Marking 8.1. Si5355 Top Marking Si5355 Axxxxx RTTTTT YYWW 8.2. Top Marking Explanation Mark Method: Laser Line 1 Marking: Device Part Number Line 2 Marking: Axxxxx A = Frequency and configuration code. Pin-controlled, any-frequency 1-200 MHz, quad frequency, 8-Output clock generator xxxxx = NVM code for custom factoryprogrammed devices. See Ordering Guide section in data sheet for more information. Line 3 Marking: R = Product revision. TTTTT = Manufacturing trace code. RTTTTT Line 4 Marking: Pin 1 indicator. Circle with 0.5 mm diameter; left-justified YY = Year. WW = Work week. Characters correspond to the year and work week of package assembly. YYWW 20 Rev. 1.1 Si5355 Si5355 DOCUMENT CHANGE LIST Revision 0.1 to Revision 0.2 Documentation updated to reflect CLKIN is on pin 4, not pin 3. Revision 0.2 to Revision 0.3 Revision 1.0 to Revision 1.1 Added cycle-cycle and phase jitter specifications to Table 3 on page 5. Changed period jitter specification from 100 ps to 75 ps pk-pk. Added Theta JC specification to Table 5 on page 6. Updated "2. Typical Application Circuit" on page 7. Added Table 7 on page 9. Clarified device operation during an input clock loss of signal. Updated Recommended PCB Layout. “3.8. CMOS Output Drivers” text to prevent duplicating specs in “Table 3. AC Characteristics.” Added Evaluation Board information to the Ordering Guide. Updated ordering information to refer to revision B silicon. Updated top marking explanation in Section 8.2 Revision 0.3 to Revision 1.0 Added shipment media information for GM (vs GMR) parts. Changed Si5356 references to Si5355. Updated VDDO pin descriptions for unused clock banks. VDDOx associated with an unused clock bank should be tied to > 1.5 V. Changed the name of output enable/disable control function pins in section 3.5 and Tables 3, 8, and 9 to align better with the actual pin functionality. Updated Table 2. DC Characteristics. Added IDDOx specification. Pn Input Resistance specification. Corrected Updated Table 3, “AC Characteristics,” on page 5. Added 10–90% input clock rise/fall time. LOS assert/deassert time. Added note on jitter test. Updated 20–80% rise/fall time with CL = 15 pF for output clocks to the maximum value of 2.0 ns. Changed Frequency Synthesis Resolution spec to the correct value of 1ppb max. Added Updated recommended crystal parameters in Table 4 on page 6 to show support for both crystals rated for either 18 or 12 pF load capacitance. Updated Table 6 on page 6. Added Soldering profile specification Input Voltage Range (VI2) to 1.3 V (max). Corrected Added packaging/RoHS information. Removed jitter spec from section “3.9. Jitter Performance” to prevent duplicating specs in “Table 3. AC Characteristics.” Removed output-to-output skew spec from section Rev. 1.1 21 Si5355 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 22 Rev. 1.1