Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Introduction Technical Note Migrating from Micron's N25Q 512Mb to Micron's MT25Q 512Mb Flash Device Introduction This technical note explains how to migrate to the Micron® MT25Q (512Mb) Flash memory device from the Micron N25Q (512Mb) stacked Flash memory device. Features compared include memory architecture, package options, signal descriptions, command sets, electrical specifications, and device identification. The MT25Q is a monolithic, high-performance multiple input/output serial Flash memory device manufactured on 45nm NOR technology. It features a high-speed SPIcompatible bus interface, execute-in-place (XIP) functionality, advanced write protection mechanisms, and extended address access. Innovative, high-performance, dual and quad input/output commands enable double or quadruple the transfer bandwidth for READ and PROGRAM operations. The MT25Q supports program speeds up to 2 MB/s and erase speeds up to 430 KB/s (for 64KB uniform) or 1700 KB/s (for 256KB uniform). Refer to the MT25Q data sheet for detailed specifications. PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. All information discussed herein is provided on an "as is" basis, without warranties of any kind. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Memory Array Architecture Memory Array Architecture Table 1: Memory Array Architecture N25Q Features MT25Q Features Two 256Mb devices stacked 512Mb monolithic Program 1 to 256 bytes Program 1 to 256 bytes Uniform sector erase (64KB) Uniform sector erase (64KB or 256KB, depending on part number) Uniform subsector erase (4KB) Uniform subsector erase (4KB) Cycling endurance 100,000 Cycling endurance 100,000 Data retention 20 years Data retention 20 years Package Configurations Table 2: Package Configurations Package N25Q MT25Q SOP2-16/300 mils Yes Yes T-PBGA-24b05 (6mm x 8mm, 5 x 5 ball) Yes Yes Signal Descriptions Table 3: Signal Descriptions N25Q Signal MT25Q Signal Type Description C C Input Serial clock DQ0 DQ0 DQ1 DQ1 Input or I/O Serial data input or I/O Output or I/O S# S# W#//DQ0 RESET# or HOLD#/DQ3 RESET# or HOLD#/DQ3 VCC VCC Input Supply voltage VSS VSS Input Ground RESET# RESET# – PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN Input Serial data output or I/O W#/VPP/DQ2 Notes: Notes Chip select Input or I/O Write protect/enhanced program supply voltage or I/O 1 Input or I/O HOLD or I/O Reset 2 1. VPP is not available on the MT25Q device. 2. On the N25Q device, a dedicated RESET# pin is available for part numbers N25Q512A83G1240X and N25Q512A83GSF40X only. On these parts, the RESET# pin must be connected to an external pull-up. On the MT25Q 512Mb device, the dedicated RESET# pin is available with specific part numbers only. On these devices, the external pull-up is not required. 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Commands Commands Table 4: Command Set Command Code N25Q Command Code MT25Q RESET ENABLE 66h 66h RESET MEMORY 99h 99h 9Eh/9Fh 9Eh/9Fh MULTIPLE I/O READ ID AFh AFh/9Eh READ SERIAL FLASH DISCOVERY PARAMETER 5Ah 5Ah READ 03h 03h 2 FAST READ 0Bh 0Bh 2 DUAL OUTPUT FAST READ 3Bh 3Bh 2 DUAL INPUT/OUTPUT FAST READ BBh BBh 2 QUAD OUTPUT FAST READ 6Bh 6Bh 2 Command Notes RESET Operations IDENTIFICATION Operations READ ID 1 READ Operations QUAD INPUT/OUTPUT FAST READ EBh EBh 2 FAST READ (DTR mode) 0Dh 0Dh 2 DUAL OUTPUT FAST READ (DTR mode) 3Dh 3Dh 2 DUAL INPUT/OUTPUT FAST READ (DTR mode) BDh BDh 2 QUAD OUTPUT FAST READ (DTR mode) 6Dh 6Dh 2 QUAD INPUT/OUTPUT FAST READ (DTR mode) EDh EDh 2 QUAD INPUT/OUTPUT WORD READ N/A E7h 4-BYTE READ 13h 13h 2 4-BYTE FAST_READ 0Ch 0Ch 2 4-BYTE DUAL OUTPUT FAST READ 3Ch 3Ch 2 4-BYTE DUAL INPUT/OUTPUT FAST READ BCh BCh 2 4-BYTE QUAD OUTPUT FAST READ 6Ch 6Ch 2 4-BYTE QUAD INPUT/OUTPUT FAST READ ECh ECh 2 4-BYTE FAST READ (DTR mode) N/A 0Eh 4-BYTE DUAL INPUT/OUTPUT FAST READ (DTR mode) N/A BEh 4-BYTE QUAD INPUT/OUTPUT FAST READ (DTR mode) N/A EEh WRITE ENABLE 06h 06h WRITE DISABLE 04h 04h READ STATUS REGISTER 05h 05h WRITE STATUS REGISTER 01h 01h READ FLAG STATUS REGISTER 70h 70h WRITE Operations REGISTER Operations PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 3 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Commands Table 4: Command Set (Continued) Command Code N25Q Command Code MT25Q CLEAR FLAG STATUS REGISTER 50h 50h READ NONVOLATILE CONFIGURATION REGISTER B5h B5h WRITE NONVOLATILE CONFIGURATION REGISTER B1h B1h READ VOLATILE CONFIGURATION REGISTER 85h 85h WRITE VOLATILE CONFIGURATION REGISTER 81h 81h READ ENHANCED VOLATILE CONFIGURATION REGISTER 65h 65h WRITE ENHANCED VOLATILE CONFIGURATION REGISTER 61h 61h READ EXTENDED ADDRESS REGISTER C8h C8h WRITE EXTENDED ADDRESS REGISTER C5h C5h READ LOCK REGISTER E8h E8h WRITE LOCK REGISTER E5h E5h PAGE PROGRAM 02h 02h 4 DUAL INPUT FAST PROGRAM A2h A2h 4 EXTENDED DUAL INPUT FAST PROGRAM D2h D2h 4 QUAD INPUT FAST PROGRAM 32h 32h 4 EXTENDED QUAD INPUT FAST PROGRAM 38h 38h 4 4-BYTE PAGE PROGRAM 12h 12h 4 4-BYTE QUAD INPUT FAST PROGRAM 34h 34h 4 4-BYTE QUAD INPUT EXTENDED FAST PROGRAM N/A 3Eh 4 32KB SUBSECTOR ERASE N/A 52h 4KB SUBSECTOR ERASE 20h 20h 4 64KB SECTOR ERASE D8h D8h 4 BULK ERASE C7h C7h 4 DIE ERASE C4h N/A 4-BYTE SECTOR ERASE DCh DCh 4 Command Notes 3 PROGRAM Operations ERASE Operations 4-BYTE SUBSECTOR ERASE 21h 21h 4 PROGRAM/ERASE RESUME 7Ah 7Ah 4 PROGRAM/ERASE SUSPEND 75h 75h 4 READ OTP ARRAY 4Bh 4Bh PROGRAM OTP ARRAY 42h 42h 4 ENTER 4-BYTE ADDRESS MODE B7h B7h 5 EXIT 4-BYTE ADDRESS MODE E9h E9h 5 35h 35h ONE-TIME PROGRAMMABLE (OTP) Operations QUAD Operations ENTER QUAD INPUT/OUTPUT MODE PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Commands Table 4: Command Set (Continued) Command Code N25Q Command Code MT25Q F5h F5h ENTER DEEP POWER DOWN N/A B9h RELEASE FROM DEEP POWER DOWN N/A ABh READ SECTOR PROTECTION N/A 2Dh PROGRAM SECTOR PROTECTION N/A 2Ch 4-BYTE READ VOLATILE LOCK BITS N/A E0h 4-BYTE WRITE VOLATILE LOCK BITS N/A E1h READ NONVOLATILE LOCK BITS N/A E2h WRITE NONVOLATILE LOCK BITS N/A E3h ERASE NONVOLATILE LOCK BITS N/A E4h READ GLOBAL FREEZE BIT N/A A7h WRITE GLOBAL FREEZE BIT N/A A6h READ PASSWORD N/A 27h WRITE PASSWORD N/A 28h UNLOCK PASSWORD N/A 29h N/A 9Bh/27h Command RESET QUAD INPUT/OUTPUT MODE Notes DEEP POWER-DOWN Operations ADVANCED SECTOR PROTECTION Operations ADVANCED FUNCTION INTERFACE Operations CYCLIC REDUNANCY CHECK Notes: PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 1. The N25Q device enables READ MANUFACTURER ID and DEVICE ID only. 17 bytes of unique ID (UID) are readable by READ ID only. On the MT25Q device, UID can be read by MULTIPLE I/O READ ID. 2. The MT25Q device outputs the entire content of the memory, rolling over the full array. The N25Q device requires the command to be sent twice to download the complete content of the array. Each command rolls over the single 256Mb die to which it has been addressed. 3. In the N25Q device, the end of an operation can be detected by issuing the READ FLAG STATUS REGISTER command twice; S# toggled status register outputs 1 both times between command execution and bit 7 of the flag. This is not required with the MT25Q device. 4. In the N25Q device, this command requires READ FLAG STATUS REGISTER to be issued with at least one byte output. (After code, at least eight clock pulses in extended SPI, four clock pulses in dual I/O SPI, and two clock pulses in quad I/O SPI.) The cycle is not complete until bit 7 of the flag status register outputs 1. This is not required with the MT25Q device. 5. WREN is not necessary for N25Q device part numbers N25Q512A83GSF40x and N25Q512A83G1240x; it is not required for M25Q part number MT25Qx512ABA8x. 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Commands READ Commands After any READ or FAST READ command, the device outputs data from the selected address and rolls over the entire die. For the N25Q 512Mb device, any READ or FAST READ command must be given twice to download the entire contents in the memory—changing the die by the address of the second READ instruction. For the monolithic MT25Q 512Mb device, any READ command rolls over the entire array—a single command is enough to download the entire contents of the device. For both devices, any READ or FAST READ command operates in all supported protocols. All protocols supported by the N25Q device are also supported by the MT25Q device. For both devices, no settings are required to work in quad I/O mode within the extended SPI protocol giving the QOFR or QIOFR command. The N25Q and MT25Q devices have configurable dummy bits in any protocol. Dummy bits can be set by the nonvolatile configuration register (customizing the default at power up) or by the volatile configuration register. Table 5: Supported Protocols Addressing Protocol STR/DTR Protocol STR 3-byte addressing DTR STR 4-byte addressing DTR Note: PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN I/O Protocol Reading Pattern Notes Extended SPI READ, FASTREAD, DOFR, DIOFR, QOFR, QIOFR, 4READ4D 1 DIO-SPI All in x2 1 QIO-SPI All in x4 1 Extended SPI READ, FASTREAD, DOFR, DIOFR, QOFR, QIOFR, 4READ4D DIO-SPI All in x2 QIO-SPI All in x4 Extended SPI READ, FASTREAD, DOFR, DIOFR, QOFR, QIOFR, 4READ4D 1 DIO-SPI All in x2 1 QIO-SPI All in x4 1 Extended SPI READ, FASTREAD, DOFR, DIOFR, QOFR, QIOFR, 4READ4D DIO-SPI All in x2 QIO-SPI All in x4 1. Protocol available in the N25Q device. 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Commands Table 6: STR: Minimum Number of Dummy Cycles Required per Each Frequency DUAL OUTPUT FAST READ DUAL I/O FAST READ QUAD OUTPUT FAST READ QUAD I/O FAST READ MT25Q N25Q MT25Q N25Q MT25Q N25Q MT25Q N25Q MT25Q 90 94 80 88 50 60 43 69 30 41 2 100 112 90 97 70 77 60 78 40 50 3 108 129 100 106 80 88 75 88 50 60 4 108 133 105 115 90 106 90 97 60 69 5 108 133 108 125 100 115 100 106 70 78 6 108 133 108 133 105 125 105 115 80 88 7 108 133 108 133 108 133 108 125 86 97 8 108 133 108 133 108 133 108 133 95 106 9 108 133 108 133 108 133 108 133 105 115 10 108 133 108 133 108 133 108 133 108 125 11 to 14 108 133 108 133 108 133 108 133 108 133 Number of Dummy Clock Cycles N25Q 1 FAST READ Table 7: DTR: Minimum Number of Dummy Cycles Required per Each Frequency DUAL OUTPUT FAST READ DUAL I/O FAST READ QUAD OUTPUT FAST READ QUAD I/O FAST READ MT25Q N25Q MT25Q N25Q MT25Q N25Q MT25Q N25Q MT25Q 47 40 43 25 30 30 34 15 20 50 56 45 48 35 38 38 39 20 25 3 54 64 50 53 40 43 45 43 25 30 4 54 66 53 62 45 48 47 48 30 34 5 54 66 54 66 50 53 50 53 35 39 6 54 66 54 66 53 57 53 57 40 43 7 54 66 54 66 54 62 54 62 43 48 8 54 66 54 66 54 66 54 66 48 53 9 54 66 54 66 54 66 54 66 53 57 10 54 66 54 66 54 66 54 66 54 62 11 to 14 54 66 54 66 54 66 54 66 54 66 Number of Dummy Clock Cycles N25Q 1 45 2 FAST READ PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device XIP and Protocol Exiting Algorithm XIP and Protocol Exiting Algorithm For both N25Q and MT25Q devices, XIP mode and all memory and registers can be reset by the RESET# pin or by issuing one of the sequences shown in the table below. Table 8: Reset Sequences Sequence Steps Effect N25Q MT25Q Disables XIP mode Yes Yes 7 clock cycles within S# LOW (S# becomes HIGH before the 8th clock cycle) +9 clock cycles within S# LOW (S# becomes HIGH before 10th clock cycle) +13 clock cycles within S# LOW (S# becomes HIGH before 14th clock cycle) XIP reset +17 clock cycles within S# LOW (S# becomes HIGH before 18th clock cycle) +25 clock cycles within S# LOW (S# becomes HIGH before 26th clock cycle) +33 clock cycles within S# LOW (S# becomes HIGH before 34th clock cycle Interface rescue DQ0 and DQ3 to 1 for 16 clock cycles with S# LOW (S# must be brought HIGH before 17th clock cycle) Restores to default at power-up No Yes Protocol rescue DQ0 and DQ3 to 1 for 8 clock cycles with S# LOW (S# Sets device to exmust be brought HIGH before 9th clock cycle) tended SPI, STR, no XIP enabled Yes Yes XIP Reset Sequence The XIP reset and protocol rescue sequence places the device in extended SPI, STR, no XIP mode. This sequence is required when power loss occurs because the device may start in an undetermined state (XIP or unnecessary protocol). Note: During execution of the WRITE NONVOLATILE CONFIGURATION REGISTER command, tSHSL2 must be at least 50ns. Below is the RESET sequence for all possible XIP configurations (quad I/O, dual I/O, and fast read). Figure 1: XIP Exiting Sequence 0 6 7 8 16 17 18 30 31 32 48 49 50 74 75 76 108 109 C S# DQ0 DQ3 PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device XIP and Protocol Exiting Algorithm Interface Rescue Sequence The MT25Q device supports the XIP rescue + interface rescue sequence. This sequence places the device in its default state. Note: This sequence resets the interface only; it does not reset the entire device. Any ongoing operations are not interrupted. The interface rescue sequence consists of two steps that must be run in the correct order. During the entire sequence, tSHSL must be ≥50ns. Protocol Rescue Sequence Exit from dual (DIO-SPI) or quad (QIO-SPI) protocol using the following FFh sequence. Figure 2: Protocol Rescue Sequence 0 1 2 3 4 5 6 7 8 C S# DQ0 DQ3 Figure 3: Interface Rescue Sequence 0 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 17 C S# DQ0 DQ3 PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Electrical Characteristics Electrical Characteristics Table 9: DC Characteristics N25Q Parameter Symbol Test Conditions MT25Q Min Max Min Max Units Input leakage current ILI – ±2 – ±2 µA Output leakage current ILO – ±2 – ±2 µA Standby current ICC1 – 150 70 100 µA Deep power-down current ICC3 N/A N/A 5 10 µA Operating current (fast-read extended I/O) ICC3 N25Q: C = 0.1VCC/0.9VCC at 108 MHz, DQ1 = open MT25Q: C = 0.1VCC/ 0.9VCC at 133 MHz, DQ1 = open – 15 – 16 mA C = 0.1VCC/0.9VCC at 54 MHz, DQ1 = open – 6 – 6 mA S = VCC, Vin = VSS or VCC Operating current (fast-read dual I/O) ICC3 N25Q: C = 0.1VCC/0.9VCC at 108 MHz, DQ1 = open MT25Q: C = 0.1VCC/ 0.9VCC at 133 MHz, DQ1 = open – 18 – 20 mA Operating current (fast-read quad I/O) ICC3 N25Q: C = 0.1VCC/0.9VCC at 108 MHz, DQ1 = open MT25Q: C = 0.1VCC/ 0.9VCC at 133 MHz, DQ1 = open – 20 – 22 mA Operating current (page program) ICC4 S# = VCC – 20 – 20 mA Operating current (write status register) ICC5 S# = VCC – 20 – 20 mA Operating current (erase) ICC6 S# = VCC – 20 – 20 mA Notes: PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN Notes 1 1. Deep power-down current is supported by the MT25Q device only. 2. The maximum standby current value (100µA) for the MT25Q device is lower than the maximum value for the N25Q device (150µA). 3. Because of different frequencies in test conditions, the MT25Q device has a maximum operating current (ICC3 ) slightly higher than the N25Q device. 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Electrical Characteristics Table 10: AC Specifications N25Q Parameter MT25Q Symbol Min Max Min Max Units fC DC 108 DC 133 MHz Clock HIGH time tCH 4 – 3.375 – ns Clock LOW time tCL 4 – 3.375 – ns S# active setup time tSLCH 4 – 3.375 – ns S# not active hold time (relative to clock) tCHSL 4 – 3.375 – ns Data in setup time tDVCH 2 – 1.75 – ns Data in hold time tCHDX 3 – 2.5 – ns S# active hold time (relative to clock) tCHSH 4 – 3.375 – ns S# not active setup time (relative to clock) tSHCH 4 – 3.375 – ns Output disable time tSHQZ – 8 – 7 ns Clock low to output valid (under 30pF) tCLQV – 7 – 6 ns HOLD setup time (relative to clock) tHLCH 4 – 3.375 – ns HOLD hold time (relative to clock) tCHHH 4 – 3.375 – ns HOLD setup time (relative to clock) tHHCH 4 – 3.375 – ns HOLD hold time (relative to clock) tCHHL 4 – 3.375 – ns Enhanced VPPH HIGH to S# LOW for extended and dual I/O page program tVPPHS 200 – – – ns tDP – – 3 – µs tRDP – – 30 – µs Clock frequency for all commands other than READ (extended-SPI, DIO-SPI, and QIO-SPI protocols) S# HIGH to deep power-down S# HIGH to standby mode (DPD exit time) Notes: PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 1. All parameters refer to STR mode. 2. AC parameters that have the same value on both the N25Q and MT25Q devices are not included in the table. Refer to the product data sheets for these parameters. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Electrical Characteristics Table 11: WRITE Cycle, PROGRAM, ERASE Times N25Q Parameter MT25Q Symbol Min Max Min Max Units tW 1.3 8 1.3 8 ms tWNVCR 0.2 3 0.2 1 s tCFSR 40 – – – ns WRITE VOLATILE CONFIGURATION REGISTER cycle time tWVCR 40 – – – ns WRITE VOLATILE ENHANCED CONFIGURATION REGISTER cycle time tWRVECR 40 – – – ns tWREAR 40 – – – ns NONVOLATILE SECTOR LOCK tPPBP – – 0.1 2.8 ms PROGRAM PROTECTION MANAGEMENT REGISTER tPPMR – – 0.1 0.5 ms PROGRAM ASP REGISTER tASPP – – 0.1 0.5 ms tPASSP – – 0.2 0.8 ms tPPBE – – 0.2 1 s tPP 0.4 5 0.2 2.8 ms tPOTP 0.2 – 0.12 0.8 ms tSE 0.6 3 0.15 1 s 4KB SECTOR ERASE tSSE 0.25 0.8 0.05 0.4 s 32KB SUBSECTOR ERASE tSSE – – 0.1 1 s BULK ERASE tBE 200 480 153 460 s WRITE STATUS REGISTER cycle time WRITE NONVOLATILE CONFIGURATION REGISTER cycle time CLEAR FLAG STATUS REGISTER cycle time WRITE EXTENDED ADDRESS REGISTER cycle time PROGRAM PASSWORD ERASE NONVOLATILE SECTOR LOCK ARRAY PAGE PROGRAM (256 bytes) PROGRAM OTP (64 bytes) 64KB SECTOR ERASE Notes: PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 1. All parameters refer to STR mode. 2. AC parameters that have the same value on both the N25Q and MT25Q devices are not included in the table. Refer to the product data sheets for these parameters. 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Device Identification Device Identification The N25Q and MT25Q devices can be identified using two JEDEC-compliant methods : • Manufacturer ID/device ID/unique ID, as output by the READ ID or MULTIPLE I/O READ ID command • Serial Flash discovery parameter (SFDP) Table 12: Device Identification Size (Bytes) 1 Name N25Q MT25Q 20h 20h Memory type BAh BAh Memory capacity 20h 20h Manufacturer ID Device ID 2 Manufacturer ID/Device ID/Unique ID The N25Q and MT25Q devices each have a unique ID (UID) composed of 17 read-only bytes: • The first byte is set to 10h • The next two bytes specify device configuration (top, bottom, or uniform architecture and hold/reset functionality) • The next 14 bytes contain optional customized factory data, which are factory programmed Table 13: Device Identification Size (Bytes) Name N25Q MT25Q 10h 10h ID and information ID and information Optional Optional Unique ID 1 byte: length of data to follow 17 2 bytes: extended device ID and device configuration information 14 bytes: customized factory data Note: 1. The UID in the N25Q device can be output in single I/O mode using the READ ID command; the MULTIPLE I/O READ ID command outputs manufacturer ID and device ID only. For the MT25Q device, UID can be output using both the READ ID and MULTIPLE I/O READ ID commands. Table 14: Extended Device ID (UID 2nd Byte) Device bit7 N25Q bit6 bit5 bit4 bit3 bit2 bit1 Reserved Technology Alternate/ standard BP scheme Reserved HOLD/RESET on DQ3 1 = Additional hardware reset pin Architecture – 0 0 0 0 = HOLD 1 = RESET 0 00 PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 13 bit0 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Device Identification Table 14: Extended Device ID (UID 2nd Byte) (Continued) Device bit7 bit6 bit5 bit4 bit3 bit2 bit1 MT25Q – 1 0 0 0 = HOLD 1 = RESET 0 = standard 1 = additional hardware reset pin 00 = uniform 64KB 11 = uniform 256KB bit0 Serial Flash Discovery Parameter (SFDP) Table 15: Parameter Table 0—Defined by JEDEC—Flash Basic Properties DW Description N25Q MT25Q Minimum block/sector erase sizes 1:0 01b 01b Write granularity 2 1 1 3 0 0 WRITE ENABLE opcode select for writing to volatile 4 0 0 Unused 7:5 111b 111b 7:0 20h 20h Supports 1-1-2 FAST READ 0 1 1 Address bytes 2:1 01b 01b Supports double transfer rate clocking 3 0 1 4 1 1 Supports 1-4-4 FAST READ 5 1 1 Supports 1-1-4 FAST READ 6 1 1 Unused 7 1 1 33h 7:0 FFh FFh 34h 7:0 FFh FFh 35h 7:0 FFh FFh 36h 7:0 FFh FFh 37h 7:0 1Fh 1Fh 4:0 01001b 01001b 7:5 001b 001b 7:0 EBh EBh 4:0 00111b 00111b 7:5 001b 001b 7:0 6Bh 6Bh WRITE ENABLE command required for writing to 1 4KB erase opcode Supports 1-2-2 FAST READ Reserved 2 Flash size in bits 1-4-4 FAST READ dummy cycle count 1-4-4 FAST READ number of mode bits 3 1-4-4 FAST READ instruction opcode 1-1-4 FAST READ dummy cycle count 1-1-4 FAST READ number of mode bits 1-1-4 FAST READ instruction opcode PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN Byte Address Bits Notes 30h 31h 32h 38h 39h 3Ah 3Bh 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Device Identification Table 15: Parameter Table 0—Defined by JEDEC—Flash Basic Properties (Continued) DW Description 1-1-2 FAST READ dummy cycle count 1-1-2 FAST READ number of mode bits 4 1-1-2 FAST READ instruction opcode 1-2-2 FAST READ dummy cycle count 1-2-2 FAST READ number of mode bits 1-2-2 instruction opcode Byte Address Bits 3Ch 3Dh 3Eh 3Fh Supports 2-2-2 FAST READ Reserved 5 Supports 4-4-4 FAST READ 40h Reserved 6 7 8 9 MT25Q 00111b 00111b 7:5 001b 001b 7:0 3Bh 3Bh 4:0 00111b 00111b 7:5 001b 001b 7:0 BBh BBh 0 1 1 3:1 111b 111b 4 1 1 7:5 111b 111b Reserved 43:41h 31:8 FFFFFFh FFFFFFh Reserved 45:44h 15:0 FFFFh FFFFh 4:0 00111b 00111b 7:5 001b 001b 2-2-2 FAST READ dummy cycle count 2-2-2 FAST READ number of mode bits 46h 2-2-2 FAST READ instruction opcode 47h 7:0 BBh BBh Reserved 49:48h 15:0 FFFFh FFFFh 4:0 01001b 01001b 7:5 001b 001b 4-4-4 FAST READ dummy cycle count 4-4-4 FAST READ number of mode bits 4Ah 4-4-4 FAST READ instruction opcode 4Bh 7:0 EBh EBh Sector type 1 size 4Ch 7:0 0Ch 0Ch Sector type 1 opcode 4Dh 7:0 20h 20h Sector type 2 size 4Eh 7:0 10h 12h Sector type 2 opcode 4Fh 7:0 D8h D8h Sector type 3 size 50h 7:0 00h 0Fh Sector type 3 opcode 51h 7:0 00h 52h Sector type 4 size 52h 7:0 00h 00h Sector type 4 opcode 53h 7:0 00h 00h Multiplier from typical erase time to maximum erase time Sector type 1 erase, typical time 10 N25Q 4:0 Sector type 2 erase, typical time 57h:54h Sector type 3 erase, typical time Sector type 4 erase, typical time PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 15 3:0 0100b 8:4 00010b 10:9 01b 15:11 01001b 17:16 01b 22:18 00110b 24:23 01b 29:25 00000b 31:30 00b Notes Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Device Identification Table 15: Parameter Table 0—Defined by JEDEC—Flash Basic Properties (Continued) DW Description Byte Address Bits 1011b Page size 7:4 1000b 12:8 1110b 13 0b 17:14 1110b 18 0b 22:19 0000b 23 0b 28:24 00001b 30:29 11b Reserved 31 1b Prohibited operations during PROGRAM SUSPEND 3:0 1100b Prohibited operations during ERASE SUSPEND 7:4 0110b Reserved 8 1b 12:9 0000b 17:13 11000b 19:18 01b 23:20 0010b 28:24 11000b 30:29 01b 31 0b BYTE PROGRAM typical time, first byte 61h:58h BYTE PROGRAM typical time, additional byte CHIP ERASE, typical time 12 PROGRAM RESUME to suspend interval Suspend in-progress program max latency 65h:62h Erase resume to suspend interval Suspend in-progress erase max latency Suspend/resume supported 13 Program resume instruction 66h 7:0 7Ah Program suspend instruction 67h 7:0 75h Resume instruction 68h 7:0 7Ah Suspend instruction 69h 7:0 75h 1:0 11b 2 0b 3 1b 7:4 1111b Reserved Status register polling device busy 14 MT25Q 3:0 PAGE PROGRAM typical time 11 N25Q Multiplier from typical time to maximum time for PAGE PROGRAM or BYTE PROGRAM Exit deep power-down to next operation 73h:70h delay 12:8 11101b 14:13 01b Exit deep power-down instruction 22:15 ABh Enter deep power-down instruction 30:23 B9h Deep power-down supported 31 0b PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 16 Notes 1 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Part Numbers Table 15: Parameter Table 0—Defined by JEDEC—Flash Basic Properties (Continued) DW 15 16 Description Byte Address Bits N25Q MT25Q 4-4-4 mode disable sequences 3:0 1010b 4-4-4 mode enable sequences 8:4 1_0100b 0-4-4 mode supported 9 1b 15:10 00_0011b 19:16 0010b Quad enable requirements (QER) 22:20 000b HOLD and WP disable 23 1b 0-4-4 mode exit method 0-4-4 mode entry method 77h:74h Reserved 31:24 FFh Volatile or nonvolatile register and write enable 6:0 0000001b Reserved 7 1b 13:8 111101b Exit 4-byte addressing 23:14 00_1111_0110 b Enter 4-byte addressing 31:24 0011_0110b Soft reset and rescue sequence support Notes: 81:78h Notes 1. The MT25Q device requires 0.4µs; 1µs is the minimum allowed in the standard SFDP table. 2. The MT25Q device requires 5µs; 64µs is the minimum allowed in the standard SFDP table. Part Numbers Table 16: Cross-Reference Part Numbers N25Q Part Number MT25Q Part Number N25Q512A11G1240x MT25QU512ABA1E12-0SIT N25Q512A11GSF40x MT25QU512ABA1ESF-0SIT N25Q512A13G1240x MT25QL512ABA1E12-0SIT N25Q512A13GSF40x MT25QL512ABA1ESF-0SIT N25Q512A83G1240x MT25QL512ABA8E12-0SIT N25Q512A83G1241x MT25QL512ABA8E12-1SIT N25Q512A83GSF40x MT25QL512ABA8ESF-0SIT Note: PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 1. F = Tape and reel; G = Tube; E = Tray; MT25Q media packing option must be specified during order request 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary TN-25-01: Migrating to Micron's MT25Q 512Mb Flash Device Revision History Revision History Rev. A – 06/13 • Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. PDF: 09005aef853bf83c tn2501_migrating_to_mt25q.pdf - Rev. A 06/13 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved.