EMIF03-SIM02F3 3-line IPAD™, EMI filter including ESD protection Features ■ EMI symmetrical (I/O) low-pass filter ■ High efficiency in EMI filtering ■ Lead-free package ■ Very low PCB space consuming: 1.2 mm2 ■ Very thin package: 0.60 mm ■ High efficiency in ESD suppression ■ High reliability offered by monolithic integration ■ High reduction of parasitic elements through integration and wafer level packaging Flip Chip (8 bumps) Figure 1. Complies with the following standards ■ ■ ■ IEC 61000-4-2 Level 4 on external and Vcc pins: – 15 kV (air discharge) – 8 kV (contact discharge) IEC 61000-4-2 Level 1on internal pins: – 2 kV (air discharge) – 2 kV (contact discharge) Figure 2. MIL STD 883E - Method 3015-6 Class 3 Pin configuration (bump side) 3 2 1 RST in RST ext CLK in Gnd CLK ext B Data in VCC Data ext C A Configuration VCC 100 Ω RST in RST ext R1 47 Ω Applications CLK in CLK ext R2 100 Ω EMI filtering and ESD protection for: Data ext Data in R3 ■ SIM Interface (subscriber identify module) ■ UIM Interface (universal identify module) Cline = 20 pF max. GND Description The EMIF03-SIM02F3 is a highly integrated device designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. This filter includes an ESD protection circuitry which prevents damage to the application when subjected to ESD surges up to 15 kV. TM: IPAD is a trademark of STMicroelectronics. April 2010 Doc ID 11554 Rev 5 1/9 www.st.com 9 Electrical characteristics 1 EMIF03-SIM02F3 Electrical characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol VPP Tj Parameter and test conditions Value Unit Internal pins (A3, B3, C3): ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge External pins (A2, B1, C2, C1): ESD discharge IEC 61000-4-2, air discharge ESD discharge IEC 61000-4-2, contact discharge 15 8 Maximum junction temperature 125 °C 2 2 kV Top Operating temperature range -40 to +85 °C Tstg Storage temperature range -55 to 150 °C Figure 3. Electrical characteristics (definitions) I Symbol VBR IRM VRM VCL IPP IR VF Cline RI/O Table 2. = = = = = = = = = Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Peak pulse current Breakdown current Forward voltage drop Line capacitance Series resistance between Input and Output VF VCL VBR VRM V IRM IR IPP Electrical characteristics (Tamb = 25 °C) Symbol Test conditions Min. Typ. Max. Unit VBR IR = 1 mA 6 - 20 V IRM VRM = 3 V - - 0.2 µA - 1.5 - Ω Rd R1, R3 Tolerance ± 20% - 100 - Ω R2 Tolerance ± 20% - 47 - Ω Vline = 0 V, Vosc = 30 mV, F = 1 MHz - - 20 pF Cline 2/9 IF Doc ID 11554 Rev 5 EMIF03-SIM02F3 Figure 4. 0.00 Electrical characteristics S21 (dB) attenuation measurement Figure 5. (A2-A3 line) db 0.00 -10.00 -10.00 -20.00 -20.00 -30.00 -30.00 S21 (dB) attenuation measurement (B1-B3 line) db F (Hz) -40.00 100.0k 1.0M 10.0M F (Hz) 100.0M -40.00 100.0k 1.0G 1.0M 10.0M 100.0M a2/a3 Figure 6. 0.00 1.0G b1/b3 S21 (dB) attenuation measurement Figure 7. (C1-C3 line) db 0.00 Analog crosstalk measurements db -10.00 -20.00 -10.00 -30.00 -40.00 -20.00 -50.00 -60.00 -70.00 -30.00 -80.00 -90.00 F (Hz) -40.00 100.0k 1.0M 10.0M 100.0M -100.00 100.0k 1.0G F (Hz) 1.0M 10.0M Figure 8. 100.0M 1.0G Xtalka3/b1 c1/c3 Digital crosstalk measurements Figure 9. Line capacitance versus reverse applied voltage (typical) C(pF) 18 Output Line 2 2 mV/div 15 12 9 6 10 ns/div Input Line 1 1 V/div 3 0 0 2 4 6 VR(V) Bumps A3 (RSTin) and B1 (CLKout) Doc ID 11554 Rev 5 3/9 Aplac model 2 EMIF03-SIM02F3 Aplac model Figure 10. Aplac model c2 Lbump Rbump a2 Lbump Rbump 100 b1 Lbump Rbump 47 c1 Lbump Rbump 100 MODEL = Dext1 MODEL = Dext3 Rbump MODEL = Dint1 MODEL = Dext1 MODEL = Dext2 Lbump a3 Rbump Lbump b3 Rbump Lbump c3 MODEL = Dint1 MODEL = Dint2 Bulk Lbump Rbump Lgnd Cgnd Rgnd Figure 11. Aplac parameters aplacvar Ls 950pH aplacvar Rs 150m aplacvar Cext1 12pF aplacvar Cext2 14pF aplacvar Cext3 18pF aplacvar Cint1 4.5pF aplacvar Cint2 4pF aplacvar Rbump 17m aplacvar Lbump 43pH aplacvar Rgnd 500m aplacvar Lgnd 50pH aplacvar Cgnd 0.15pF aplacvar Rsub 100m 4/9 Dint1 BV=15 CJO=Cint1 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.29 VJ=0.6 TT=50n Dext1 BV=15 CJO=Cext1 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.25 VJ=0.6 TT=50n Doc ID 11554 Rev 5 Dint2 BV=15 CJO=Cint2 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.31 VJ=0.6 TT=50n Dext2 BV=15 CJO=Cext2 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.28 VJ=0.6 TT=50n Dext3 BV=15 CJO=Cext3 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.25 VJ=0.6 TT=50n EMIF03-SIM02F3 Aplac model Figure 12. Voltages when IEC 61000-4-2 (+15 kV air discharge) applied to external pin Vin : 10 V/div Vout : 10 V/div 100 ns/div Figure 13. Voltages when IEC 61000-4-2 (- 15 kV air discharge) applied to external pin Vin : 10 V/div Vout : 10 V/div 100 ns/div Doc ID 11554 Rev 5 5/9 Ordering information scheme 3 EMIF03-SIM02F3 Ordering information scheme Figure 14. Ordering information scheme EMIF yy - xxx zz Fx EMI Filter Number of lines Information x = resistance value (ohm) z = capacitance value / 10 (pF) or 3 letters = application 2 digits = version Package F = Flip Chip x = 3: lead-free, pitch = 400 µm, bump = 255 µm 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 15. Package dimensions 605 µm ± 55 255 µm ± 40 170 µm ± 10 1.14 mm ± 30 µm 400 µm ± 40 400 µm ± 40 6/9 170 µm ± 10 1.14 mm ± 30 µm Doc ID 11554 Rev 5 EMIF03-SIM02F3 Ordering information Figure 16. Footprint Figure 17. Marking Dot, ST logo ECOPACK status xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter: 220 µm recommended 260 µm maximum Solder mask opening: 300 µm minimum x x z y ww Solder stencil opening : 220 µm recommended Dot identifying Pin A1 location Ø 1.55 ± 0.1 4.0 ± 0.1 2.0 ± 0.05 3.5 ± 0.1 1.24 xxz yww STE xxz yww STE xxz yww STE 8.0 ± 0.3 0.20 ± 0.02 1.75 ± 0.1 Figure 18. Flip Chip tape and reel specification 4.0 ± 0.1 1.24 0.69 ± 0.05 User direction of unreeling All dimensions in mm 5 Ordering information Table 3. Note: Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF03-SIM02F3 HA Flip Chip 1.74 mg 5000 Tape and reel 7” More information is available in the application notes: AN2348: “STMicroelectronics 400 micro-metre Flip Chip: package description and recommendation for use” AN1751: "EMI filters: recommendations and measurements" Doc ID 11554 Rev 5 7/9 Revision history 6 EMIF03-SIM02F3 Revision history Table 4. 8/9 Document revision history Date Revision Changes 19-Jul-2005 1 Initial release. 26-Feb-2007 2 Changed out to ext in Configuration diagram on page 1. Added Ecopack statement. Reformatted to current layour standard. Updated Application note AN2348 reference and description. 28-Nov-2007 3 Updated ECOPACK statement. Updated Figure 14, Figure 15, Figure 16 and Figure 18. Reformatted to current standards. 09-Feb-2010 4 Updated die dimensions in Figure 15 and pocket dimensions in Figure 18. 07-Apr-2010 5 Updated tolerance dimensions in Figure 15: Package dimensions. Doc ID 11554 Rev 5 EMIF03-SIM02F3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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