RENESAS HD74HC589

HD74HC589
8-bit Serial or Parallel-input/Serial-output Shift Register
(with 3-state outputs)
REJ03D0631-0200
(Previous ADE-205-511)
Rev.2.00
Mar 30, 2006
Description
The HD74HC589 is similar in function to the HD74HC597, which is not a 3-state device.
This device consists of an 8-bit storage latch which feeds parallel data to an 8-bit shift register. Data can also be loaded
serially (see Function Table). The shift register output, OH, is a three-state output, allowing this device to be used in
bus-oriented systems.
Features
• High Speed Operation: tpd (Shift Clock to QH) = 15 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
HD74HC589FPEL
SOP-16 pin (JEITA)
HD74HC589RPEL
SOP-16 pin (JEDEC)
Package Code
(Previous Code)
PRSP0016DH-B
(FP-16DAV)
Package
Abbreviation
PRSP0016DG-A
(FP-16DNV)
Taping Abbreviation
(Quantity)
FP
EL (2,000 pcs/reel)
RP
EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table
Latch Clock
LCK
Shift Clock
SCK
Serial Shift/
Parallel Load
Output Enable
OE
X
X
X
L
X
L
Data are loaded into input latches
Data are loaded from input into shift registers
X
X
L
L
L, H,
L, H,
X
H
Data are transferred from input latches to shift
registers
Outputs are disabled
L
Serial shift Qn = Qn – 1, Q0 = SER
Note:
X
H
1. H; High level, L; Low level, X; Irrelevant
Rev.2.00 Mar 30, 2006 page 1 of 8
Function
HD74HC589
Pin Arrangement
B 1
16 VCC
C 2
15 A
D 3
14 SA
E 4
13
F 5
12 Latch Clock
G 6
11 Shift Clock
H 7
10 Output Enable
GND 8
9 QH
(Top view)
Rev.2.00 Mar 30, 2006 page 2 of 8
Serial Shift/
Parallel Load
HD74HC589
Logic Diagram
SCK
SA
Shift/
Load
SCK
A
LCK Q
D
LCK Q
B
LCK Q
D
LCK Q
SCK
S
SCK
Q
D
SCK
R
S
SCK
Q
D
SCK
R
C
D
E
F
G
H
LCK
LCK
VCC
LCK
QH
OE
Rev.2.00 Mar 30, 2006 page 3 of 8
HD74HC589
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage range
Input / Output voltage
VCC
VIN, VOUT
–0.5 to 7.0
–0.5 to VCC +0.5
V
V
IIK, IOK
IOUT
±20
±35
mA
mA
ICC or IGND
PT
±75
500
mA
mW
Input / Output diode current
Output current
VCC, GND current
Power dissipation
Storage temperature
Tstg
–65 to +150
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item
Supply voltage
Symbol
VCC
Ratings
2 to 6
Unit
V
Input / Output voltage
Operating temperature
VIN, VOUT
Ta
0 to VCC
–40 to 85
V
°C
tr , tf
0 to 1000
0 to 500
Input rise / fall time
Note:
*1
ns
0 to 400
1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Conditions
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Electrical Characteristics
Item
Input voltage
Symbol VCC (V)
VIH
VIL
Output voltage
VOH
Ta = 25°C
Typ Max
Ta = –40 to+85°C
Unit
Min
Max
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
—
—
—
—
—
—
2.0
4.5
6.0
—
—
—
0.5
1.35
1.8
—
—
—
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
—
—
—
0.5
1.35
1.8
—
—
—
4.18
5.68
—
—
—
—
—
—
—
—
0.0
0.0
0.0
—
—
—
—
—
0.1
0.1
0.1
0.26
0.26
±0.5
4.13
5.63
—
—
—
—
—
—
—
—
0.1
0.1
0.1
0.33
0.33
±5.0
—
—
—
—
±0.1
4.0
—
—
±1.0
40
Off-state output
current
IOZ
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
Input current
Quiescent supply
current
Iin
ICC
6.0
6.0
VOL
Min
Rev.2.00 Mar 30, 2006 page 4 of 8
Test Conditions
V
V
V
V
Vin = VIH or VIL IOH = –20 µA
Vin = VIH or VIL
IOH = –6 mA
IOH = –7.8 mA
IOL = 20 µA
IOH = 6 mA
IOH = 7.8 mA
µA Vin = VIH or VIL
Vout = VCC or GND
µA Vin = VCC or GND
µA Vin = VCC or GND, Iout = 0 µA
HD74HC589
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Item
Symbol VCC (V)
Maximum clock
frequency
fmax
Propagation delay
time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Ta = –40 to +85°C
2.0
Min
—
Typ
—
Max
5
Min
—
Max
4
4.5
6.0
—
—
—
—
27
32
—
—
21
25
2.0
4.5
—
—
—
20
200
40
—
—
250
50
6.0
2.0
—
—
—
—
34
175
—
—
43
220
4.5
6.0
—
—
15
—
35
30
—
—
44
37
2.0
4.5
—
—
—
16
175
35
—
—
220
44
6.0
2.0
—
—
—
—
30
150
—
—
37
190
4.5
6.0
—
—
9
—
30
26
—
—
38
33
Output enable
time
tZL
tZH
Output disable
time
tLZ
tHZ
2.0
4.5
—
—
—
14
150
30
—
—
190
38
Pulse width
tw
6.0
2.0
—
80
—
—
26
—
—
100
33
—
4.5
6.0
16
14
8
—
—
—
20
17
—
—
2.0
4.5
100
20
—
1
—
—
125
25
—
—
6.0
2.0
17
100
—
—
—
—
21
125
—
—
4.5
6.0
20
17
—
—
—
—
25
21
—
—
2.0
4.5
100
20
—
—
—
—
125
25
—
—
6.0
2.0
17
5
—
—
—
—
21
5
—
—
4.5
6.0
5
5
0
—
—
—
5
5
—
—
2.0
4.5
5
5
—
—
—
—
5
5
—
—
6.0
2.0
5
5
—
—
—
—
5
5
—
—
4.5
6.0
5
5
—
—
—
—
5
5
—
—
Setup time
tsu
tsu
tsu
Hold time
th
th
th
Output rise/fall
time
tTLH
tTHL
2.0
4.5
—
—
—
5
75
15
—
—
95
19
Input capacitance
Cin
6.0
—
—
—
—
5
13
10
—
—
16
10
Rev.2.00 Mar 30, 2006 page 5 of 8
Unit
Test Conditions
MHz
ns
Latch clock to QH
ns
Shift clock to QH
ns
Serial shift/parallel load to QH
ns
ns
ns
ns
Data to latch clock
ns
SA to shift clock
ns
Serial shift/parallel load to
shift clock
ns
Latch clock to data
ns
Shift clock to SA
ns
Shift clock to serial shift/
parallel load
ns
pF
HD74HC589
Test Circuit
VCC
VCC
Output
OE
See Function Table
Input
Pulse Generator
Zout = 50 Ω
Input
Pulse Generator
Zout = 50 Ω
1 kΩ
SA
S1
QH
OPEN
GND
Shift/Load
CL =
50 pF
SCK
LCK
A to H
VCC
TEST
t PLH / t PHL
S1
OPEN
t ZH/ t HZ
t ZL / t LZ
GND
VCC
Note : 1. CL includes probe and jig capacitance.
Waveforms
1. (SERIAL SHIFT / PARALLEL LOAD = "L")
tr
tf
VCC
Latch
Clock
50% 50%
50%
tW(H)
0V
tW(L)
tPLH
50%
10%
QH
3.
90%
50%
10%
tZL
50%
50%
0V
tPHL
VOH
QH
50%
50%
VOL
VOL
tTHL
4.
tr
10%
VCC
90%
50%
0V
tLZ
tZH
VCC
50%
50%
tPHL
10%
90%
VCC
VOL
VOH
50%
Data
VOL
Notes : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns
2. Waveform - A is for an output with internal conditions such that the
output is low except when disabled by the output control.
3. Waveform - B is for an output with internal conditions such that the
output is high except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
Rev.2.00 Mar 30, 2006 page 6 of 8
50%
0V
tPLH
tHZ
50%
Serial Shift /
Parallel Load
tw
VOH
50%
Waveform - A
Waveform - B
50%
10%
VCC
50%
tw
tPLH
VOH
90%
tf
90%
Shift
Clock
tPHL
tTLH
Input G
2. (SERIAL SHIFT / PARALLEL LOAD = "H")
50%
0V
HD74HC589
5.
6.
Data Valid
Data Valid
VCC
VCC
A to H
50%
SA
VCC
Latch
Clock
50%
0V
50%
0V
0V
th
tsu
50%
tsu
Shift
Clock
th
VCC
50%
7.
Serial Shift /
Parallel Load
VCC
50%
50%
0V
tsu
Shift
Clock
th
VCC
50%
0V
Notes : 1. Input waveform : PRR ≤ 1 MHz, duty cycle 50%, tr ≤ 6 ns, tf ≤ 6 ns
2. The output are measured one at a time with one transition per measurement.
Rev.2.00 Mar 30, 2006 page 7 of 8
0V
HD74HC589
Package Dimensions
JEITA Package Code
P-SOP16-5.5x10.06-1.27
RENESAS Code
PRSP0016DH-B
*1
Previous Code
FP-16DAV
MASS[Typ.]
0.24g
D
F
16
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
9
*2
c
E
HE
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
1
8
e
Z
*3
bp
x
Reference
Symbol
M
A
L1
θ
A1
y
L
Detail F
JEITA Package Code
P-SOP16-3.95x9.9-1.27
RENESAS Code
PRSP0016DG-A
*1
Previous Code
FP-16DNV
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Dimension in Millimeters
Min Nom Max
10.06 10.5
5.50
0.00 0.10 0.20
2.20
0.34 0.40 0.46
0.15 0.20 0.25
0°
8°
7.50 7.80 8.00
1.27
0.12
0.15
0.80
0.50 0.70 0.90
1.15
MASS[Typ.]
0.15g
D
F
16
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
9
c
*2
Index mark
HE
E
bp
Terminal cross section
( Ni/Pd/Au plating )
1
Z
Reference
Symbol
8
e
*3
bp
x
M
A
L1
A1
θ
L
y
Detail F
Rev.2.00 Mar 30, 2006 page 8 of 8
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Dimension in Millimeters
Min Nom Max
9.90 10.30
3.95
0.10 0.14 0.25
1.75
0.34 0.40 0.46
0.15 0.20 0.25
0°
8°
5.80 6.10 6.20
1.27
0.25
0.15
0.635
0.40 0.60 1.27
1.08
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