Standard Products UT54LVDM055LV Dual Driver and Receiver Data Sheet December 2008 www.aeroflex.com/lvds INTRODUCTION FEATURES The UT54LVDM055LV Dual Driver/Dual Receiver is designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400.0 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. Two drivers and two receivers with individual enables >400.0 Mbps (200 MHz) switching rates +340mV differential signaling 3.3 V power supply TTL compatible inputs The UT54LVDM055LV Driver accepts low voltage TTL input levels and translates them to low voltage (350mV) differential output signals. In addition, the driver supports a three-state function that may be used to disable the output stage, disabling the load current, and thus dropping the device to a low idle power state. 10mA LVDS output drivers TTL compatible outputs Cold spare all pins Ultra low power CMOS technology Operational environment; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 300 krad(Si) - Latchup immune (LET > 100 MeV-cm2/mg) Packaging options: - 18-lead flatpack (dual in-line) Standard Microcircuit Drawing 5962-06202 - QML Q and V compliant part The UT54LVDM055LV Receiver accepts low voltage (350mV) differential input signals and translates them to 3V CMOS output levels. The receiver supports a three-state function that may be used to multiplex outputs. The receiver also supports OPEN, shorted and terminated (35 Ω) input fail-safe. Receiver output will be HIGH for all fail-safe conditions. All pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS. RIN1+ + RIN1- R1 ROUT1 R2 ROUT2 - REN1 RIN2+ + RIN2- - REN2 DOUT2+ D2 DOUT2DEN2 DOUT1+ D1 DOUT1DEN1 DIN2 DIN1 Figure 1. UT54LVDM055LV Dual Driver and Receiver Block Diagram 1 PIN DESCRIPTION RIN1- 1 18 REN1 RIN1+ 2 3 17 ROUT1 16 ROUT2 15 14 GND 13 DEN2 RIN2+ UT54LVDM055LV Driver/Receiver REN2 4 5 DOUT2- 6 DOUT2+ 7 12 DIN2 DOUT1+ 8 11 DIN1 DOUT1- 9 10 DEN1 RIN2- VDD Figure 2. UT54LVDM055LV Pinout TRUTH TABLE Enables Input Output DEN DIN DOUT+ DOUT- L X Z Z H L L H H H L Enables Input Output REN RIN+ - RIN- ROUT L X Z H VID > 0.1V H VID < -0.1V L Full Fail-safe OPEN/SHORT or Terminated H 2 Pin No. Name Description 11, 12 DIN Driver input pin, TTL/CMOS compatible 7, 8 DOUT+ Non-inverting driver output pin, LVDS levels 6, 9 DOUT- Inverting driver output pin, LVDS levels 10, 13 DEN Driver active high enable pin 2, 5 RIN+ Non-inverting receiver input pin 1, 4 RIN- Inverting receiver input pin 16, 17 ROUT Receiver output pin 5, 18 REN Receiver active high enable pin 14 VDD Power supply pin, +3.3 + 0.3V 15 VSS Ground pin APPLICATIONS INFORMATION The UT54LVDM055LV provides two drivers and two receivers in the same package. Each driver and each receiver has a dedicated output enable pin. This allows maximum flexibility for the device. ENABLE DATA INPUT The intended application of these devices and signaling technique is for both point-to-point (single termination) and multipoint (double termination) data transmissions over controlled impedance media. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.) LVDS Receiver RT 35Ω + - DATA OUTPUT LVDS Driver Figure 3. Point-to-Point Application Receiver Fail-Safe The UT54LVDM055LV receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to TTL logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The UT54LVMS055LV differential line driver is a balanced current source design. A current mode driver, has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The current mode requires that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 3. AC or unterminated configurations are not allowed. The 10mA loop current will develop a differential voltage of 350mV across the 35Ω termination resistor which the receiver detects with a 250mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350mV - 100mV = 250mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as shown in Figure 4. Note: The steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 700mV. The receiver’s internal fail-safe circuitry is designed to source/ sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. Open Input Pins. The UT54LVDM055LV is a dual receiver device, and if an application requires only 1 receiver, the unused channel inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a three-state or power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 35Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as commonmode and not differential, a balanced interconnect should be used. Twisted pair cable offers better balance than flat ribbon cable. The UT54LVDM055LV receiver’s are capable of detecting signals as low as 100mV, over a +/- 1V commonmode range centered around +1.2V. Both receiver input pins should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground). The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. The termination resistor converts the current sourced by the driver into voltages that are detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a midstream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (VSS to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. 3 OPERATIONAL ENVIRONMENT PARAMETER LIMIT UNITS Total Ionizing Dose (TID) 1.0E6 rad(Si) Single Event Latchup (SEL) >100 MeV-cm2/mg PARAMETER LIMITS ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL VDD DC supply voltage VI/O Voltage on any pin during operation -0.3 to (VDD + 0.3V) Voltage on any pin during cold spare -.3 to 4.0V TSTG -0.3 to 4.0V Storage temperature -65 to +150°C PD Maximum power dissipation 1.25 W TJ Maximum junction temperature2 +150°C Thermal resistance, junction-to-case3 10°C/W DC input current ±10mA ΘJC II Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175°C during burn-in and life test. 3. Test per MIL-STD-883, Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD Positive supply voltage 3.0 to 3.6V TC Case temperature range -55 to +125°C VIN DC input voltage, receiver inputs DC input voltage, logic inputs 4 2.4V 0 to VDD DC ELECTRICAL CHARACTERISTICS DRIVER *1, 2,4 (VDD = 3.3V + 0.3V; -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered SYMBOL PARAMETER CONDITION MIN VIH High-level input voltage (TTL) VIL Low-level input voltage (TTL) VOL Low-level output voltage RL = 35Ω VOH High-level output voltage RL = 35Ω IIN Input leakage current VIN = VDD or GND, VDD = 3.6V ICS Cold Spare Leakage Current VOD1 ΔVOD1 VOS ΔVOS MAX 2.0 UNIT V 0.8 0.855 V V 1.750 V -5 +5 μA VIN=3.6V, VDD=VSS -10 +10 μΑ Differential Output Voltage RL = 35Ω(figure 5) 250 400 mV Change in Magnitude of VOD for Complementary Output States RL = 35Ω(figure 5) 35 mV Offset Voltage + VOL-⎞ RL = 35Ω, VOS = ⎛ VOH -------------------------------- 1.550 V ⎝ 2 ⎠ 1.055 Change in Magnitude of VOS for Complementary Output States RL = 35Ω(figure 5) 35 mV Input clamp voltage ICL = +18mA -1.5 V IOS2, 3 Output Short Circuit Current VIN = VDD, VOUT+ = 0V or VIN = GND, VOUT- = 0V, DEN = VDD 40 mA IOZ Output Three-State Current DEN = 0.8V VOUT = 0V or VDD, VDD = 3.6V +5 μΑ ICCL4 Loaded supply current, drivers and receivers enabled RL = 35Ω all channels REN = DEN = VDD VIN = VDD or VSS(all inputs) ICCZ4 Loaded supply current, drivers and receivers disabled DIN = VDD or VSS REN = DEN = VSS VCL -5 mA 40.0 mA 15.0 Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except differential voltages. 2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. 3. Guaranteed by characterization 4. Receivers are included for parameters ICCL and ICCZ. 5 AC SWITCHING CHARACTERISTICS DRIVER*1, 2, 3 (VDD = +3.3V + 0.3V, TC = -55 °C to +125 °C); Unless otherwise noted, Tc is per the temperature range ordered SYMBOL PARAMETER MIN MAX UNIT tPHLD6 Differential Propagation Delay High to Low (figures 5 and 6) 0.5 1.8 ns tPLHD6 Differential Propagation Delay Low to High (figures 5 and 6) 0.5 1.8 ns tSKD Differential Skew (tPHLD - tPLHD) (figures 5 and 6) 0 0.4 ns tSK11 Channel-to-Channel Skew (figures 5 and 6) 0 0.5 ns tSK25 Chip-to-Chip Skew (figure 5 and 6) 1.3 ns tTLH4 Rise Time (figures 5 and 6) 1.5 ns tTHL4 Fall Time (figures 5 and 6) 1.5 ns tPHZ Disable Time High to Z (figures 7 and 8) 5 ns tPLZ Disable Time Low to Z (figures 7 and 8) 5 ns tPZH Enable Time Z to High (figures 7 and 8) 7.0 ns tPZL Enable Time Z to Low (figures 7 and 8) 7.0 ns Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs. 2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50, tr < 1ns, and tf < 1ns. 3. CL includes probe and jig capacitance. 4. Guaranteed by characterization 5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. 6. May be tested at higher load capacitance and the limit interpolated from characterization data to guarantee this parameter. 6 DC ELECTRICAL CHARACTERISTICS RECEIVER*1,2,4 (VDD = 3.3V + 0.3V; -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered SYMBOL PARAMETER CONDITION MIN MAX VIH High-level input voltage (TTL) VIL Low-level input voltage (TTL) 0.8 V VOL Low-level output voltage IOL = 2mA, VDD = 3.0V 0.25 V VOH High-level output voltage IOH = -0.4mA, VDD = 3.0V 2.7 IIN Logic input leakage current Enables = REN = 0 and 3.6V, VDD = 3.6 -5 +5 μA II LVDS Receiver input Current VIN = 2.4V, VDD = 3.6 -15 +15 μΑ ICS Cold Spare Leakage Current VIN=3.6V, VDD=VSS -10 +10 μΑ VTH3 Differential Input High Threshold VCM = +1.2V +100 mV VTL3 Differential Input Low Threshold VCM = +1.2V IOZ3 Output Three-State Current Disabled, VOUT = 0 V or VDD REN = 0.8V VCL Input clamp voltage Output Short Circuit Current IOS2, 3 2.0 UNIT V V -100 mV +5 μΑ ICL = -18mA -1.5 V Enabled, VOUT = 0 V2 REN = VDD -75 mA -5 Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground. 2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed 1 second. 3. Guaranteed by characterization. 4. Refer to driver DC characteristics for ICCL and ICCZ. 7 AC SWITCHING CHARACTERISTICS RECEIVER*1, 2, 3 (VDD = +3.3V + 0.3V, TA = -55 °C to +125 °C); Unless otherwise noted, Tc is per the temperature range ordered SYMBOL PARAMETER MIN MAX UNIT tPHLD6 Differential Propagation Delay High to Low (figures 9 and 10) 1.0 2.0 ns tPLHD6 Differential Propagation Delay Low to High (figures 9 and 10) 1.0 2.0 ns tSKD Differential Skew (tPHLD - tPLHD) (figures 9 and 10) 0 0.35 ns tSK11 Channel-to-Channel Skew (figures 9 and 10) 0 0.5 ns tSK25 Chip-to-Chip Skew (figures 9 and 10) 1.0 ns tTLH4 Rise Time (figures 9 and 10) 1.2 ns tTHL4 Fall Time (figures 9 and 10) 1.2 ns tPHZ Disable Time High to Z (figures 11 and 12) 4.0 ns tPLZ Disable Time Low to Z (figures 11 and 12) 4.0 ns tPZH Enable Time Z to High (figures 11 and 12) 3.0 ns tPZL7 Enable Time Z to Low (figures 11 and 12) 3.0 ns Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs. 2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z0 = 50Ω, tr and tf (0% - 100%) < 1ns for RIN and tr and tf < 1ns for EN or EN. 3. CL includes probe and jig capacitance. 4. Guaranteed by characterization. 5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. 6. May be tested at higher load capacitance and the limit interpolated from characterization data to guarantee this parameter. 7. During tPZL the output may transition High before going Low. 8 DOUT+ 40pF DIN D Generator RL = 35Ω VOD 50Ω Driver Enabled 40pF DOUT- Figure 4. Driver VOD and VOS Test Circuit or Equivalent Circuit DOUT+ 40pF DIN D Generator RL = 35Ω 50Ω Driver Enabled 40pF DOUT- Figure 5. Driver Propagation Delay and Transition Time Test Circuit or Equivalent Circuit 9 VDD VDD/2 DIN VDD/2 tPLHD DOUT- 0V tPHLD VOH 0V (Differential) VOL DOUT+ 80% 80% VDIFF = DOUT+ - DOUT- 0V 0V VDIFF 20% 20% tTHL tTLH Figure 6. Driver Propagation Delay and Transition Time Waveforms or Equivalent Circuit DOUT+ 40pF VDD 17.5Ω DIN D VSS 17.5Ω EN 40pF Generator 50Ω EN Figure 7. Driver Three-State Delay Test Circuit or Equivalent Circuit or Equivalent Circuit 10 DOUT- EN when EN = VDD VDD VDD/2 VDD/2 0V or VDD VDD/2 VDD/2 EN when EN = VSS DOUT+ when DIN =VDD DOUT- when DIN = VSS 0V tPHZ tPZH VOH 50% 50% VOS VOS 50% 50% DOUT+ when DIN = VSS DOUT- when DIN = VDD VOL tPZL tPLZ Figure 8. Driver Three-State Delay Waveform or Equivlent Circuit 11 RIN+ Generator RIN- R ROUT 40pF 50Ω 50Ω Receiver Enabled Figure 9. Receiver Propagation Delay and Transition Time Test Circuit or Equivalent Circuit RIN- +1.3V VID = 200mV 0V Differential +1.2V +1.1V RIN+ tPHLD tPLHD VOH 80% 80% 50% 50% ROUT 20% 20% VOL tTHL tTLH Figure 10. Receiver Propagation Delay and Transition Time Waveforms or Equivalent Circuits 12 VDD EN 100Ω RIN+ RIN- 40pf 100Ω Figure 11. Receiver Three-State Delay Test Circuit or Equivalent Circuit EN when EN = VDD VDD VDD/2 VDD/2 0V VDD VDD/2 VDD/2 EN when EN = VSS 0V tPZL tPLZ Output when VID = -100mV Output when VID = +100mV 50% 50% VDD/2 VOL tPHZ tPZH 50% VOH 50% VDD/2 Figure 12. Receiver Three-State Delay Waveform or Equivalent Circuit 13 Notes: 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MIL-PRF-38535. 4. Lead position and coplanarity are not measured. 5. ID mark symbol is vendor option and may be different than shown. 6. With solder, increase maximum by 0.003. 7. Package weight 0.8 grams. Figure 13. 18-pin Ceramic Flatpack 14 ORDERING INFORMATION UT54LVDM055LV DUAL DRIVER/RECEIVER: UT 54LVDM055LV- * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = HiRel Temperature Range flow (P) = Prototype flow Package Type: (U) = 18-lead Flatpack (dual-in-line) Access Time: Not applicable Device Type: UT54LVDM055LV LVDS Receiver Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C. Radiation neither tested nor guaranteed. 15 UT54LVDM055LV DUAL DRIVER/RECEIVER: SMD 5962 - 06202 ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (X) = 18 lead Flatpack (dual-in-line) Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 01 - Dual driver receiver 100KRad(Si) 300KRad(Si) Drawing Number: 5962-06202 Total Dose (R) = 1E5 rad(Si) (F) = 3E5 rad(Si) Federal Stock Class Designator: No Options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 16 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com/RadHard [email protected] Aeroflex Colorado Springs, Inc. (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. 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