Standard Products
UT9Q512E 512K x 8 RadTol SRAM
Data Sheet
September, 2008
INTRODUCTION
The UT9Q512E RadTol product is a high-performance CMOS
static RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (E), an
active LOW Output Enable (G), and three-state drivers.
FEATURES
20ns maximum (5 volt supply) address access time
Asynchronous operation for compatibility with industrystandard 512K x 8 SRAMs
TTL compatible inputs and output levels, three-state
bidirectional data bus
Operational environment:
- Total dose: 50 krads(Si)
Writing to the device is accomplished by taking Chip Enable (E)
input LOW and Write Enable (W) inputs LOW. Data on the eight
I/O pins (DQ0 through DQ7) is then written into the location
specified on the address pins (A0 through A18). Reading from
the device is accomplished by taking Chip Enable (E) and
Output Enable (G) LOW while forcing Write Enable (W) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
- SEL Immune 110 MeV-cm2/mg
- SEU LETTH(0.25) = 52 cm2 MeV
- Saturated Cross Section 2.8E-8 cm2/bit
-<1.1E-9 errors/bit-day, Adams 90% worst case
environment geosynchronous orbit
The eight input/output pins (DQ0 through DQ7) are placed in a
high impedance state when the device is deselected (E HIGH),
the outputs are disabled (G HIGH), or during a write operation
(E LOW and W LOW).
Packaging:
- 36-lead ceramic flatpack (3.831 grams)
Standard Microcircuit Drawing 5962-00536
- QML Q and V compliant part
Clk. Gen.
Pre-Charge Circuit
A0
A1
A2
Row Select
I/O Circuit
Column Select
A9
DQ 0 - DQ 7
Data
Control
A10
A11
CLK
Gen.
A12
A13
A14
A15
A16
A17
A18
A3
A4
A5
A6
A7
A8
Memory Array
1024 Rows
512x8 Columns
E
W
G
Figure 1. UT9Q512E SRAM Block Diagram
1
DEVICE OPERATION
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A1
A2
A3
A4
E
DQ0
DQ1
VDD
VSS
DQ2
DQ3
W
A5
A6
A7
A8
A9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
The UT9Q512E has three control inputs called Chip Enable (E),
Write Enable (W), and Output Enable (G); 19 address inputs,
A(18:0); and eight bidirectional data lines, DQ(7:0). E controls
device selection, active, and standby modes. Asserting E enables
the device, causes IDD to rise to its active value, and decodes the
19 address inputs to select one of 524,288 words in the memory.
W controls read and write operations. During a read cycle, G
must be asserted to enable the outputs.
NC
A18
A17
A16
A15
G
DQ7
DQ6
VSS
VDD
DQ5
DQ4
A14
A13
A12
A11
A10
NC
Table 1. Device Operation Truth Table
Figure 2. UT9Q512E 20ns SRAM Pinout (36)
PIN NAMES
A(18:0)
Address
DQ(7:0)
Data Input/Output
E
Chip Enable
W
Write Enable
G
Output Enable
VDD
Power
VSS
Ground
G
W
E
I/O Mode
Mode
X1
X
1
3-state
Standby
X
0
0
Data in
Write
1
1
0
3-state
Read2
0
1
0
Data out
Read
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than VIH (min) and E less than VIL
(max) defines a read cycle. Read access time is measured from
the latter of Chip Enable, Output Enable, or valid address to
valid data output.
SRAM Read Cycle 1, the Address Access in figure 4a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs
remain active throughout the entire cycle. As long as Chip
Enable and Output Enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (tAVAV).
SRAM read Cycle 2, the Chip Enable - Controlled Access in
figure 4b, is initiated by E going active while G remains asserted,
W remains deasserted, and the addresses remain stable for the
entire cycle. After the specified tETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable - Controlled Access in
figure 4c, is initiated by G going active while E is asserted, W
is deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
2
active. For the W initiated write, unless the outputs have been
previously placed in the high-impedance state by G, the user
must wait tWLQZ before applying data to the eight bidirectional
pins DQ(7:0) to avoid bus contention.
WRITE CYCLE
A combination of W less than VIL(max) and E less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than VIH(min), or when W is less
than VIL(max).
OPERATIONAL ENVIRONMENT
Table 2. Operational Environment
Design Specifications1
Write Cycle 1, the Write Enable - Controlled Access in figure
5a, is defined by a write terminated by W going high, with E
still active. The write pulse width is defined by tWLWH when the
write is initiated by W, and by tETWH when the write is initiated
by E. Unless the outputs have been previously placed in the highimpedance state by G, the user must wait tWLQZ before applying
data to the nine bidirectional pins DQ(7:0) to avoid bus
contention.
Total Dose
50
krad(Si)
Heavy Ion
Error Rate2
<1.1E-9
Errors/Bit-Day
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. Adam’s 0% worst case environment, Geosynchronous orbit, 100 mils of
Aluminum.
Write Cycle 2, the Chip Enable - Controlled Access in figure
5b, is defined by a write terminated by E going inactive. The
write pulse width is defined by tWLEF when the write is initiated
by W, and by tETEF when the write is initiated by the E going
3
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL
PARAMETER
LIMITS
VDD
DC supply voltage
-0.5 to 7.0V
VI/O
Voltage on any pin
-0.5 to 7.0V
TSTG
Storage temperature
-65 to +150°C
PD
Maximum power dissipation
TJ
Maximum junction temperature2
+150°C
Thermal resistance, junction-to-case3
10°C/W
DC input current
±10 mA
ΘJC
II
1.0W
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
VDD
Positive supply voltage
4.5 to 5.5V
TC
Case temperature range
(C) screening: -55°C to +125°C
(W) screening: -40°C to +125°C
VIN
DC input voltage
0V to VDD
4
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
-55°C to +125°C for (C) screening and -40oC to +125oC for (W) screening (VDD = 5.0V + 10%)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
VIH
High-level input voltage
(TTL)
VIL
Low-level input voltage
(TTL)
0.8
V
VOL1
Low-level output voltage
IOL = 8mA, VDD =4.5V (TTL)
0.4
V
VOL2
Low-level output voltage
IOL = 200μA,VDD =4.5V (CMOS)
0.05
V
VOH1
High-level output voltage
IOH = -4mA,VDD =4.5V (TTL)
2.4
V
VOH2
High-level output voltage
IOH = -200μA,VDD =4.5V (CMOS)
3.2
V
CIN1
Input capacitance
ƒ = 1MHz @ 0V
10
pF
CIO1
Bidirectional I/O capacitance
ƒ = 1MHz @ 0V
12
pF
IIN
Input leakage current
VIN = VDD and VSS, VDD = VDD (max)
-2
2
μA
IOZ
Three-state output leakage current
VO = VDD and VSS
VDD = VDD (max)
G = VDD (max)
-2
2
μA
VDD = VDD (max), VO = VDD
-90
90
mA
IOS2, 3
Short-circuit output current
2
UNIT
V
VDD = VDD (max), VO = 0V
IDD(OP)4
Supply current operating
@ 1MHz
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
50
mA
IDD(OP)4
Supply current operating
@50MHz
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
76
mA
IDD(SB)
Supply current standby
@0MHz
Inputs: VIL = VSS
IOUT = 0mA
E = VDD - 0.5
VDD = VDD (max)
VIH = VDD - 0.5V
10
mA
45
mA
-55°C, -40°C, 25°C
125°C
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. G = V1H
5
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*
-55°C to +125°C for (C) screening and -40oC to +125oC for (W) screening (VDD = 5.0V + 10%)
SYMBOL
PARAMETER
MIN
MAX
tAVAV1
Read cycle time
tAVQV
Read access time
tAXQX
Output hold time
3
ns
tGLQX
G-controlled Output Enable time
0
ns
tGLQV
G-controlled Output Enable time (Read Cycle 3)
10
ns
tGHQZ2
G-controlled output three-state time
10
ns
tETQX3
E-controlled Output Enable time
tETQV3
E-controlled access time
20
ns
E-controlled output three-state time
10
ns
tEFQZ1,2,4
20
UNIT
ns
20
3
ns
Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 500mV change from steady-state output voltage (see Figure 3).
3. The ET (chip enable true) notation refers to the falling edge of E. SEU immunity does not affect the read parameters.
4. The EF (chip enable false) notation refers to the rising edge of E. SEU immunity does not affect the read parameters.
High Z to Active Levels
Active to High Z Levels
VH - 500mV
VLOAD + 500mV
}
VLOAD
{
{
}
VLOAD - 500mV
VL + 500mV
Figure 3. 5-Volt SRAM Loading
6
ns
tAVAV
A(18:0)
DQ(7:0)
Previous Valid Data
Valid Data
tAVQV
tAXQX
Assumptions:
1. E and G < VIL (max) and W > VIH (min)
Figure 4a. SRAM Read Cycle 1: Address Access
A(18:0)
E
tETQV
tETQX
tEFQZ
DQ(7:0)
DATA VALID
Assumptions:
1. G < VIL (max) and W > VIH (min)
Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access
Fi
4b SRAM R d C l 2 Chi E
bl C
ll d A
tAVQV
A(18:0)
G
tGHQZ
tGLQX
DATA VALID
DQ(7:0)
tGLQV
Assumptions:
1. E< VIL (max) and W > VIH (min)
Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access
7
AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*
-55°C to +125°C for (C) screening and -40oC to +125oC for (E) screening (VDD = 5.0V + 10%)
SYMBOL
PARAMETER
9Q512-25
5.0V
MIN
MAX
UNIT
tAVAV1
Write cycle time
20
ns
tETWH
Chip Enable to end of write
20
ns
tAVET
Address setup time for write (E - controlled)
0
ns
tAVWL
Address setup time for write (W - controlled)
0
ns
tWLWH
Write pulse width
20
ns
tWHAX
Address hold time for write (W - controlled)
2
ns
tEFAX
Address hold time for Chip Enable (E - controlled)
0
ns
tWLQZ2
W - controlled three-state time
10
tWHQX
W - controlled Output Enable time
4
ns
tETEF
Chip Enable pulse width (E - controlled)
20
ns
tDVWH
Data setup time
15
ns
tWHDX
Data hold time
2
ns
tWLEF
Chip Enable controlled write pulse width
20
ns
tDVEF
Data setup time
15
ns
tEFDX
Data hold time
2
ns
tAVWH
Address valid to end of write
20
ns
tWHWL1
Write disable time
5
ns
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test performed with outputs disabled (G high).
2. Three-state is defined as 500mV change from steady-state output voltage (see Figure 3).
8
ns
A(18:0)
tAVAV2
E
tAVWH
tETWH
tWHWL
W
tAVWL
tWLWH
tWHAX
Q(7:0)
tWLQZ
D(7:0)
tWHQX
APPLIED DATA
Assumptions:
1. G < VIL (max). If G > VIH (min) then Q(7:0) will be
in three-state for the entire cycle.
2. G high for tAVAV cycle.
tDVWH
tWHDX
Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access
9
tAVAV3
A(18:0)
tETEF
tAVET
tEFAX
E
or
tAVET
E
W
tETEF
tEFAX
tWLEF
APPLIED DATA
D(7:0)
tWLQZ
tDVEF
Q(7:0)
tEFDX
Assumptions & Notes:
1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle.
2. Either E scenario above can occur.
3. G high for tAVAV cycle.
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
10
CMOS
90%
VDD-0.05V
300 ohms
10%
0.5V
VLOAD = 1.55V
10%
< 5ns
50pF
< 5ns
Input Pulses
Notes:
1. 50pF including scope probe and test socket capacitance.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(i.e., CMOS input = VDD/2).
Figure 6. AC Test Loads and Input Waveforms
11
DATA RETENTION MODE
VDD
VDR > 2.5V
4.5V
4.5V
tR
tEFR
E
Figure 7. Low VDD Data Retention Waveform
DATA RETENTION CHARACTERISTICS (Pre-Radiation)*
(VDD = VDD (min), 1 Sec DR Pulse)
SYMBOL
PARAMETER
TEMP
MINIMUM
MAXIMUM
UNIT
VDR
VDD for data retention
--
2.5
--
V
IDDR 1
Data retention current
-40oC
--
10
mA
-55oC
--
10
mA
25oC
--
10
mA
125oC
--
45
mA
Chip enable to data retention time
--
0
--
ns
Operation recovery time
--
tAVAV
--
ns
tEFR1
tR1
Notes:
* Post-radiation performance guaranteed at 25oC per MIL-STD-883 Method 1019.
1. E1 = VDR all other inputs = VDR or VSS.
12
PACKAGING
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance to MIL-PRF-38535.
4. Dimension are in accordance with MIL-PRF-38535.
5. Lead position and coplanarity are not measured.
6. ID mark symbol is vendor option: no alphanumerics. One or both ID methods ma y be used
for Pin 1 ID.
7. Letter designators are in accordance with MIL-STD-1835.
8. Dimensions shown are in inches.
Figure 8. 36-pin Ceramic FLATPACK
13
ORDERING INFORMATION
512K x 8 SRAM:
UT9Q512E- * *
*
*
Lead Finish: (Notes 1 & 2)
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Screening: (Notes 3, 4, & 5)
(C) = HiRel Temperature Range Flow
(P) = Prototype flow
(W) = Extended Industrial Temperature Range Flow (-40oC to +125oC)
Package Type:
(Y) = 36-lead flatpack package (bottom brazed)
20 = 20ns access time, 5.0V operation
-Aeroflex Core Part Number
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither
tested nor guaranteed.
4. HiRel Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55°C, room temp, and +125°C.
Radiation neither tested nor guaranteed.
5. Extended Industrial Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -40°C room temp
and +125°C. Radiation neither tested nor guaranteed.
14
512K x 8 SRAM: SMD
5962 - 00536
** * * *
Lead Finish: (Notes 1 & 2)
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
Case Outline:
(Y) = 36-lead ceramic flatpack (bottom-brazed)
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Device Type
05 = 20ns access time, 5.0V operation, Mil-Temp
06 = 20ns access time, 5.0V operation, Extended Industrial Temp (-40C to +125C)
Drawing Number: 00536
Total Dose: (Note 3)
(D) = 1E4 (10 krad)(Si))
(P) = 3E4 (30 krad)(Si))
(L) = 5E4 (50krad(Si))
Federal Stock Class Designator: No options
Notes:
1.Lead finish (A,C, or X) must be specified.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering.
15
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
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Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual rights of
Aeroflex or of third parties.
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16
Aeroflex Colorado Springs Application Note
AN-MEM-002
Low Power SRAM Read Operations
Table 1: Cross Reference of Applicable Products
Manufacturer
Part Number
SMD #
Device Type
Internal PIC
Number:*
4M Asynchronous SRAM
UT8R128K32
5962-03236
01 & 02
WC03
4M Asynchronous SRAM
UT8R512K8
5962-03235
01 & 02
WC01
16M Asynchronous SRAM
UT8CR512K32
5962-04227
01 & 02
MQ08
16M Asynchronous SRAM
UT8ER512K32
5962-06261
05 & 06
WC04/05
4M Asynchronous SRAM
UT8Q512E
5962-99607
05 & 06
WJ02
4M Asynchronous SRAM
UT9Q512E
5962-00536
05 & 06
WJ01
16M Asynchronous SRAM
UT8Q512K32E
5962-01533
02 & 03
QS04
16M Asynchronous SRAM
UT9Q512K32E
5962-01511
02 & 03
QS03
32M Asynchronous SRAM
UT8ER1M32
5962-10202
01 - 04
QS16/17
64M Asynchronous SRAM
UT8ER2M32
5962-10203
01 - 04
QS09/10
128M Asynchronous SRAM
UT8ER4M32
5962-10204
01 - 04
QS11/12
40M Asynchronous SRAM
UT8R1M39
5962-10205
01 & 02
QS13
80M Asynchronous SRAM
UT8R2M39
5962-10206
01 & 02
QS14
160M Asynchronous SRAM
UT8R4M39
5962-10207
01 & 02
QS15
Product Name:
* PIC = Aeroflex’s internal Product Identification Code
1.0 Overview
The purpose of this application note is to discuss the Aeroflex SRAMs low power read architecture and to inform users of the
affects associated with the low power read operations.
2.0 Low Power Read Architecture
The aforementioned Aeroflex designed SRAMs all employ an architecture which reduces power consumption during read
accesses. The architecture internally senses data only when new data is requested. A request for new data occurs anytime the
chip enable device pin is asserted, or any of the device address inputs transition states while the chip enable is asserted. A trigger is generated and sent to the sensing circuit anytime a request for new data is observed. Since several triggers could occur
simultaneously, these triggers are wire-ORed to result in a single sense amplifier activity for the read request. This design
method results in less power consumption than designs that continually sense data. Aeroflex’s low power SRAMs listed above
activate the sensing circuit for approximately 5ns whenever and access is requested, thereby, significantly reducing active
power.
Creation Date: 8/19/11
Page 1 of 5
Modification Date: 4/24/13
Aeroflex Colorado Springs Application Note
AN-MEM-002
2.1 The SRAM Read Cycles.
The data sheets for all the devices noted in Table #1 discuss three methods for performing a read operation. The two most common methods for reading data are an Address Access and a Chip Enabled-Controlled Access. The third access discussed is the
Output Enable-Controlled Access. The sequence at which control lines and address inputs are toggled determines which cycle
is considered relevant. As discussed in section 2.0, an assertion of chip enable or any address transition while chip enable is
asserted, initiates a read cycle. If the device chip enable is asserted prior to any address input transitions, then the read access
is considered an Address Access. By keeping the device enabled and repeatedly switching address locations, the user retrieves
all data of interest. A Chip Enable-Controlled Access occurs when the address signals are stable prior to asserting the chip
enable. The Output Enabled-Controlled Access requires that either an Address Access or Chip Enable-Controlled Access has
already been performed and the data is waiting for the Output Enable pin to assert, driving data to the device I/O pins.
The subsequent read cycle verbiage and diagrams are based on the Aeroflex UT8R512K8 data sheet. The number of control,
input, and I/O pins will vary across the products listed in Table 1. The basic design family functionality for read operations is
common among all the devices.
2.1.0 Address Access Read Cycle
The Address Access is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid
data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle.
As long as chip enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle
time (tAVAV).
tAVAV
A(18:0)
DQ(7:0)
Previous Valid Data
Valid Data
tAVQV
Assumptions:
1. E1 and G < VIL (max) and E2 and W > VIH (min)
tAXQX
Note: No time references are relevant with respect to Chip Enable(s). Chip Enable(s) is assumed to be asserted.
SRAM Read Cycle 1: Address Access
Creation Date: 8/19/11
Page 2 of 5
Modification Date: 4/24/13
Aeroflex Colorado Springs Application Note
AN-MEM-002
2.1.1 Chip Enable-Controlled Read Cycle
The Chip Enable-controlled Access is initiated by E1 and E2 going active while G remains asserted, W remains deasserted, and
the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0)
is accessed and appears at the data outputs DQ(7:0).
A(18:0)
E1 low or
E2 high
tETQV
tETQX
DQ(7:0)
tEFQZ
DATA VALID
Assumptions:
1. G < VIL (max) and W > VIH (min)
Note: No specification is given for address set-up time with respect to chip enable assertion. The read cycle description states that
addresses are to remain stable for the entire cycle. Address set-up time relative to chip enable is assumed to be 0ns minimum.
SRAM Read Cycle 2: Chip Enable Access
2.1.1 Output Enabled-Controlled Read Cycle
The Output Enable-controlled Access is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the
addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied.
tAVQV
A(18:0)
G
tGHQZ
tGLQX
DATA VALID
DQ(7:0)
tGLQV
Assumptions:
1. E1 < VIL (max) , E2 > and W > VIH (min)
SRAM Read Cycle 3: Output Enable Access
3.0 Low Power Read Architecture Timing Consideration
The low power read architecture employed by Aeroflex designed SRAMs results in significant power reduction, especially in
applications with longer than minimum read cycle times. However, this type of architecture is responsive to excessive input
signal skew when device addressing and chip enable assertion occur simultaneously. Signal skew of greater than 4-5ns
between all of the read triggering activities is sufficient to start another read cycle.
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3.1 Simultaneous Control and Address Switching
Simultaneous switching of controls and address pins, alone, is not a problem; excessive skew between them is the concern.
Consider the application where several SRAM devices are connected to the same memory bus. The address bus is commonly
connected to all the devices, but the chip enable pin is singularly connected to each individual SRAM. This configuration
results in a loading difference between the address inputs and the chip enable. This lightly loaded chip enable propagates to the
memory more quickly than the heavily loaded address lines. The oscilloscope capture of Figure #1 is the actual timing of an
application which had intermittent data errors due to address transitions lagging chip enable.
Address Signal (Ax)
Chip Enable (/E)
Timing shown from VIL (yellow trace /CS) and VIH (pink for address signal) as delta X =
6ns. Even at actual internal gate switching point (~ VDD/2), the skew is still around 6ns.
Figure #1 SRAM Signal Capture
The signal transitions in the scope plot of Figure #1 appear to be fairly coincidental. A closer look however, reveals the chip
enable signal actually starts and reaches VIL approximately 6ns before the address signal reaches VIH. Even at one half VDD
(closer to actual logical gate switching of the inputs), the delta in signal times is still approximately 6ns.
Simultaneous switching of controls and address inputs is not recommended for a couple of reasons. The first is the previously
described signal skew sensitivity between controls and/or address inputs. The second reason is that activating all the controls
and address inputs simultaneously results in peak instantaneous current consumption. This condition causes maximum strain
to the power decoupling. Chip Enable activates address decoding circuits, address switching introduces input buffer switching
current, and output enable assertion turns on all the device output drivers. Peforming all three simultaneously results in worst
case transient current demand by the memory.
3.1.0 Technical Overview of Skew Sensitivity
Recall from section 2.0 that any activity requesting new data causes a read trigger. The triggers are wire-ORed together. In
order to meet the faster access times demanded by today’s applications, the ORed trigger only exists during the first 4-5ns of
the read cycle. Since the slowest of the address transitions occurs more than 5ns after the initiation of the read activity, a second read activity is initiated. The sensing circuit does not have time to normalize before the second read activity has started.
For this reason a Chip Enable-Controlled read cycle requires that address inputs remain stable for the entire cycle. Infrequent
and random sensing errors can result if the bit columns are continually pulled to one state then quickly requested to sense the
opposite state. Another effect of the low power read architecture that differs from previous generation designs (those that continually sense for data) is that the bit line will not be sensed again until another read triggering event occurs. If another read
trigger event (chip enable assertion and/or address change) does no occur for a particular address, the incorrect data remains at
the outputs.
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4.0 Summary and Conclusion
The Aeroflex SRAMs in Table #1 all employ a low power consumption read architecture. Power is conserved by sensing data
only when new data is requested. A request occurs anytime chip enable is asserted or any address input signal transitions while
chip enable is asserted. The data sheets for the SRAMs listed in Table #1 do not explicitly define the case of simultaneous
switching of address and control signals during read operations. Data sheet read cycle descriptions indicate that control inputs
are established prior to address changes, and address inputs are stable prior to control assertions. Simultaneous switching of
addresses and controls is tolerable, when the skew between all input signals is < 4ns. For designs that must employ the simultaneous activation of address and control signals, two important issues should be considered by the designer. The first is the
input signal skew sensitivity of the low power read architecture discussed by this application note. The second is the instantaneous current consumption that results from simultaneous access methods. Aeroflex recommends the use of only one read
access method at a time. If multiple read accesses (simultaneous chip enable assertion and address switching) cannot be
avoided, then Aeroflex recommends that the chip enable signal be delayed until all addresses have completed transitions.
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