Standard Products UT8R512K8 512K x 8 SRAM Data Sheet March 2009 www.aeroflex.com/memories FEATURES 15ns maximum access time Asynchronous operation for compatibility with industrystandard 512K x 8 SRAMs CMOS compatible inputs and output levels, three-state bidirectional data bus - I/O Voltage 3.3 volts, 1.8 volt core Operational environment: - Intrinsic total-dose: 300K rad(Si) INTRODUCTION The UT8R512K8 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by active LOW and HIGH chip enables (E1, E2), an active LOW output enable (G), and three-state drivers. This device has a power-down feature that reduces power consumption by more than 90% when deselected. - SEL Immune >100 MeV-cm2/mg - LETth (0.25): 53.0 MeV-cm2/mg - Memory Cell Saturated Cross Section 1.67E-7cm2/bit - Neutron Fluence: 3.0E14n/cm2 - Dose Rate - Upset 1.0E9 rad(Si)/sec - Latchup >1.0E11 rad(Si)/sec Packaging options: - 36-lead ceramic flatpack (3.762 grams) Standard Microcircuit Drawing 5962-03235 - QML Q & Vcompliant part INPUT DRIVER TOP/BOTTOM DECODER INPUT DRIVERS BLOCK DECODER A(18:0) INPUT DRIVERS INPUT DRIVERS E1 Writing to the device is accomplished by taking chip enable one (E1) input LOW, chip enable two (E2) HIGH and write enable (W) input LOW. Data on the eight I/O pins (DQ0 through DQ7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip enable one (E1) and output enable (G) LOW while forcing write enable (W) and chip enable two (E2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (DQ0 through DQ7) are placed in a high impedance state when the device is deselected (E1 HIGH or E2 LOW), the outputs are disabled (G HIGH), or during a write operation (E1 LOW, E2 HIGH and W LOW). ROW DECODER COLUMN DECODER MEMORY ARRAY COLUMN I/O CHIP ENABLE E2 G W DATA WRITE CIRCUIT DATA READ CIRCUIT OUTPUT ENABLE WRITE ENABLE Figure 1. UT8R512K8 SRAM Block Diagram 1 INPUT DRIVERS OUTPUT DRIVERS DQ(7:0) DEVICE OPERATION A0 A1 A2 A3 A4 E1 DQ0 DQ1 VDD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VSS DQ2 DQ3 W A5 A6 A7 A8 A9 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 E2 A18 A17 A16 A15 G DQ7 DQ6 VSS The UT8R512K8 has four control inputs called Chip Enable 1 (E1), Chip Enable 2 (E2), Write Enable (W), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). E1 and E2 device enables control device selection, active, and standby modes. Asserting E1 and E2 enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. W controls read and write operations. During a read cycle, G must be asserted to enable the outputs. VDD1 DQ5 DQ4 A14 A13 A12 A11 A10 VDD2 Table 1. Device Operation Truth Table Figure 2. 15ns SRAM Pinout (36) PIN NAMES A(18:0) Address W WriteEnable DQ(7:0) Data Input/Output G Output Enable E1 E2 Chip Enable 1 (active low) VDD1 Power (1.8V) Chip Enable 2 (active high) VDD2 Power (3.3V) VSS G W E2 E1 I/O Mode Mode X X X 1 3-state Standby X X 0 X 3-state Standby X 0 1 0 Data in Write 1 1 1 0 3-state Read2 0 1 1 0 Data out Read Notes: 1. “X” is defined as a “don’t care” condition. 2. Device active; outputs disabled. READ CYCLE A combination of W and E2 greater than VIH (min) and E1 less than VIL (max) defines a read cycle. Read access time is measured from the latter of chip enable, output enable, or valid address to valid data output. Ground SRAM Read Cycle 1, the Address Access in Figure 3a, is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as chip enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). SRAM Read Cycle 2, the Chip Enable-controlled Access in Figure 3b, is initiated by E1 and E2 going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0). SRAM Read Cycle 3, the Output Enable-controlled Access in Figure 3c, is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. 2 WRITE CYCLE OPERATIONAL ENVIRONMENT A combination of W and E1 less than VIL(max) and E2 greater than VIH(min) defines a write cycle. The state of G is a “don’t care” for a write cycle. The outputs are placed in the highimpedance state when either G is greater than VIH(min), or when W is less than VIL(max). Write Cycle 1, the Write Enable-controlled Access in Figure 4a, is defined by a write terminated by W going high, with E1 and E2 still active. The write pulse width is defined by tWLWH when the write is initiated by W, and by tETWH when the write is initiated by E1 or E2. Unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the nine bidirectional pins DQ(7:0) to avoid bus contention. Write Cycle 2, the Chip Enable-controlled Access in Figure 4b, is defined by a write terminated by either of E1 or E2 going inactive. The write pulse width is defined by tWLEF when the write is initiated by W, and by tETEF when the write is initiated by either E1or E2 going active. For the W initiated write, unless the outputs have been previously placed in the high-impedance state by G, the user must wait tWLQZ before applying data to the eight bidirectional pins DQ(7:0) to avoid bus contention. The UT8R512K8 SRAM incorporates special design and layout features which allows operation in a limited environment. Table 2. Operational Environment Design Specifications1 Total Dose 300K rad(Si) Heavy Ion Error Rate2 8.9x10-10 Errors/Bit-Day Notes: 1. The SRAM is immune to latchup to particles >100MeV-cm2/mg. 2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of Aluminum. Supply Sequencing No supply voltage sequencing is required between VDD1 and VDD2. 3 ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL PARAMETER LIMITS VDD1 DC supply voltage -0.3 to 2.1V VDD2 DC supply voltage -0.3 to 3.8V VI/O Voltage on any pin -0.3 to 3.8V TSTG Storage temperature -65 to +150°C PD Maximum power dissipation TJ Maximum junction temperature2 +150°C Thermal resistance, junction-to-case3 5°C/W DC input current ±5 mA ΘJC II 1.2W Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD1 Positive supply voltage 1.7 to 1.9V1 VDD2 Positive supply voltage 3.0 to 3.6V TC Case temperature range (P) Screening: -25°C (C) Screening: -55 to +125°C (W) Screening: -40 to +125°C VIN DC input voltage 0V to VDD2 Notes: 1. For increased noise immunity, supply voltage (VDD1) can be increased to 2.0V. If not tested, all applicable DC and AC charateristics are guaranteed by characterization at VDD1 (max) = 2.0V. 4 DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)* Unless otherwise noted, Tc is per the temperature ordered SYMBOL PARAMETER CONDITION MIN MAX UNIT VIH High-level input voltage VIL Low-level input voltage VOL1 Low-level output voltage IOL = 8mA,VDD2 =VDD2 (min) VOH1 High-level output voltage IOH = -4mA,VDD2 =VDD2 (min) CIN1 Input capacitance ƒ = 1MHz @ 0V 12 pF CIO1 Bidirectional I/O capacitance ƒ = 1MHz @ 0V 12 pF IIN Input leakage current VIN = VDD2 and VSS -2 2 μA IOZ Three-state output leakage current VO = VDD2 and VSS, VDD2 = VDD2 (max) G = VDD2 (max) -2 2 μA IOS2, 3 Short-circuit output current VDD2 = VDD2 (max), VO = VDD2 VDD2 = VDD2 (max), VO = VSS -100 +100 mA Supply current operating @ 1MHz Inputs : VIL = VSS + 0.2V VIH = VDD2 - 0.2V, IOUT = 0 VDD2 = VDD2 (max) VDD1 = 1.9V 12 mA VDD1 = 2.0V 19 mA Supply current operating @66MHz Inputs : VIL = VSS + 0.2V, VIH = VDD2 - 0.2V, IOUT = 0 VDD2 = VDD2 (max) VDD1 = 1.9V 30 mA VDD1 = 2.0V 43 mA IDD2(OP1) Supply current operating @ 1MHz Inputs : VIL = VSS + 0.2V VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max) VDD2 = VDD2 (max) .2 mA IDD2(OP2) Supply current operating @66MHz Inputs : VIL = VSS + 0.2V, VIH = VDD2 - 0.2V, IOUT = 0 VDD1 = VDD1 (max), VDD2 = VDD2 (max) 4 mA IDD1(OP1) IDD1(OP2) .7*VDD2 5 V .3*VDD2 V .2*VDD2 V .8*VDD2 V IDD1(SB)4 Supply current standby @ 0Hz CMOS inputs , IOUT = 0 E1 = VDD2 -0.2, E2 = GND VDD2 = VDD2 (max) IDD2(SB)4 IDD1(SB)4 Supply current standby A(18:0) @ 66MHz CMOS inputs , IOUT = 0 E1 = VDD2 - 0.2, E2 = GND, VDD2 = VDD2 (max) IDD2(SB)4 VDD1 = 1.9V 11 mΑ VDD1 = 2.0V 18 mA VDD1 = VDD1 (max) 100 μA VDD1 = 1.9V 11 mΑ VDD1 = 2.0V 18 mA VDD1 = VDD1 (max) 100 μA Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25×C per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second. 4. VIH = VDD2 (max), VIL = 0V. 6 AC CHARACTERISTICS READ CYCLE (Pre and Post-Radiation)* VDD1 = VDD1 (min), VDD2 = VDD2 (min); Unless otherwise noted, Tc is per the temperature ordered SYMBOL PARAMETER UNIT 8R512-155 MIN MAX tAVAV1 Read cycle time 15 ns tAVQV Read access time tAXQX2 Output hold time 3 ns tGLQX1,2 G-controlled output enable time 0 ns tGLQV G-controlled output enable time 7 ns tGHQZ2 G-controlled output three-state time 7 ns tETQX2,3 E-controlled output enable time 15 5 ns ns tETQV3 E-controlled access time 15 ns tEFQZ4 E-controlled output three-state time2 7 ns Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25×C per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. Guaranteed, but not tested. 2. Three-state is defined as a 200mV change from steady-state output voltage. 3. The ET (chip enable true) notation refers to the latter falling edge of E1 or rising edge of E2. SEU immunity does not affect the read parameters. 4. The EF (chip enable false) notation refers to the latter rising edge of E1 or falling edge of E2. SEU immunity does not affect the read parameters. 7 tAVAV A(18:0) DQ(7:0) Previous Valid Data Valid Data tAVQV Assumptions: 1. E1 and G < VIL (max) and EZ and W > VIH (min) tAXQX Figure 3a. SRAM Read Cycle 1: Address Access A(18:0) E1 low or E2 high tETQV tETQX tEFQZ DQ(7:0) DATA VALID Assumptions: 1. G < VIL (max) and W > VIH (min) Figure 3b. SRAM Read Cycle 2: Chip Enable Access tAVQV A(18:0) G tGHQZ tGLQX DATA VALID DQ(7:0) tGLQV Assumptions: 1. E1 < VIL (max) , E2 > and W > VIH (min) Figure 3c. SRAM Read Cycle 3: Output Enable Access 8 AC CHARACTERISTICS WRITE CYCLE (Pre and Post-Radiation)* VDD1 = VDD1 (min), VDD2 = VDD2 (min); Unless otherwise noted, Tc is per the temperature ordered SYMBOL 8R512-15 PARAMETER MIN UNIT MAX tAVAV1 Write cycle time 15 ns tETWH Chip enable to end of write 12 ns tAVET Address setup time for write (E1/E2- controlled) 0 ns tAVWL Address setup time for write (W - controlled) 1 ns tWLWH Write pulse width 12 ns tWHAX Address hold time for write (W - controlled) 2 ns tEFAX Address hold time for chip enable (E1/E2- controlled) 0 ns tWLQZ2 W - controlled three-state time tWHQX2 W - controlled output enable time 4 ns tETEF Chip enable pulse width (E1/E2 - controlled) 12 ns tDVWH Data setup time 7 ns tWHDX Data hold time 2 ns tWLEF Chip enable controlled write pulse width 12 ns tDVEF Data setup time 7 ns tEFDX Data hold time 0 ns tAVWH Address valid to end of write 12 ns Write disable time 3 ns tWHWL1 5 ns Notes: *For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25×C per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. Test with G high. 2. Three-state is defined as 200mV change from steady-state output voltage. 9 A(18:0) tAVAV E1 tAVWH E2 tETWH tWHWL W tAVWL tWLWH tWHAX Q(7:0) tWLQZ tWHQX D(7:0) APPLIED DATA Assumptions: 1. G < VIL (max). If (G > VIH (min) then Q(8:0) will be in three-state for the entire cycle). tDVWH tWHDX Figure 4a. SRAM Write Cycle 1: W - Controlled Access 10 tAVAV A(18:0) tETEF tAVET tEFAX E1 E2 tETEF or tAVET tEFAX E1 E2 W tWLEF APPLIED DATA D(7:0) tWLQZ tDVEF Q(7:0) tEFDX Assumptions & Notes: 1. G < VIL (max). (If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle). 2. Either E1 scenario above can occur. Figure 4b. SRAM Write Cycle 2: Chip Enable - Controlled Access 11 DATA RETENTION CHARACTERISTICS (Pre-Radiation)* (VDD2 = VDD2 (min), 1 Sec DR Pulse) SYMBOL PARAMETER VDR TEMP MINIMUM MAXIMUM UNIT -- 1.0 -- V -55°C -- 600 μA 25°C -- 600 μA 125°C -- 12 mA -40°C -- 600 μA 25°C -- 600 μA 125°C -- 12 mA Chip deselect to data retention time -- 0 -- ns Operation recovery time -- tAVAV -- ns VDD1 for data retention Data retention current IDDR 1 Device Type 1 Data retention current IDDR 1 Device Type 2 tEFR1,2 tR1,2 Notes: * For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25×C per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. E1 = VDD2 or E2 = VSS all other inputs = VDD2 or VSS 2. VDD2 = 0 volts to VDD2 (max) DATA RETENTION MODE 1.7V 1.7V VDR > 1.0V VDD1 VIN >0.7VDD2 CMOS tR tEFR E2 VSS E1 VDD2 VIN <0.3VDD2 CMOS Figure 5. Low VDD Data Retention Waveform VDD2 VDD2 CMOS DUT Test Point Zo = 50-ohms CL = 50pF 90% VDD2-0.05V RTERM 100-ohms 10% 0.0V RTERM 100-ohms < 2ns < 2ns Input Pulses Notes: 1. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = VDD2/2). Figure 6. AC Test Loads and Input Waveforms 12 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MIL-PRF-38535. 4. Dimension sybology is in accordance with MIL-PRF-38535. 5. Lead position and coplanarity are not measured. 6. ID mark symbol is vendor option: no alphanumerics. One or both ID methods ma y be used for Pin 1 ID. 7. Equivalent to MIL-STD-1853A F-19 configuration A (glass field) using a configuration B (multi-layer) ceramiic body style. Figure 7. 36-pin Ceramic FLATPACK 13 PACKAGING 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MIL-PRF-38535. 4. Dimension sybology is in accordance with MIL-PRF-38535. 5. Lead position and coplanarity are not measured. 6. ID mark symbol is vendor option: no alphanumerics. One or both ID methods ma y be used for Pin 1 ID. 7. Equivalent to MIL-STD-1853A F-19 configuration A (glass field) using a configuration B (multi-layer) ceramiic body style. Figure 7. 36-pin Ceramic FLATPACK 14 ORDERING INFORMATION 512K x 8 SRAM: UT **** * - * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = HiRel Temperature Range flow (-55°C to +125°C) (P) = Prototype flow (W) = Extended industrial temperature range flow (-40°C to +125°C) Package Type: (U) = 36-lead FP Access Time: (15) = 15ns access time Device Type: (8R512K8) = 512K x 8 SRAM Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C. Radiation neither tested nor guaranteed. 5. Extended Industrial Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -40°C, room temp, and 125°C. Radiation neither tested nor guaranteed. 15 512K x 8 SRAM: SMD 5962 - ******* ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (U) = 36-lead ceramic flatpack Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type (01) = 15ns access time, CMOS I/O, 36-lead flatpack package, dual chip enable (-55°C to +125°C) (02) = 15ns access time, CMOS I/O, 36-lead flatpack package, dual chip enable (-40°C to +125°C) (02TBD)=15ns access time, CMOS I/O, 40-lead flatpack package, dual chip enable (not available) Drawing Number: 03235 Total Dose: (R) = 100K rad(Si) (F) = 300K rad(Si) Federal Stock Class Designator: No options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 16 NOTES 17 Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Colorado Springs (Aeroflex) reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 18 Aeroflex Colorado Springs Application Note AN-MEM-002 Low Power SRAM Read Operations Table 1: Cross Reference of Applicable Products Manufacturer Part Number SMD # Device Type Internal PIC Number:* 4M Asynchronous SRAM UT8R128K32 5962-03236 01 & 02 WC03 4M Asynchronous SRAM UT8R512K8 5962-03235 01 & 02 WC01 16M Asynchronous SRAM UT8CR512K32 5962-04227 01 & 02 MQ08 16M Asynchronous SRAM UT8ER512K32 5962-06261 05 & 06 WC04/05 4M Asynchronous SRAM UT8Q512E 5962-99607 05 & 06 WJ02 4M Asynchronous SRAM UT9Q512E 5962-00536 05 & 06 WJ01 16M Asynchronous SRAM UT8Q512K32E 5962-01533 02 & 03 QS04 16M Asynchronous SRAM UT9Q512K32E 5962-01511 02 & 03 QS03 32M Asynchronous SRAM UT8ER1M32 5962-10202 01 - 04 QS16/17 64M Asynchronous SRAM UT8ER2M32 5962-10203 01 - 04 QS09/10 128M Asynchronous SRAM UT8ER4M32 5962-10204 01 - 04 QS11/12 40M Asynchronous SRAM UT8R1M39 5962-10205 01 & 02 QS13 80M Asynchronous SRAM UT8R2M39 5962-10206 01 & 02 QS14 160M Asynchronous SRAM UT8R4M39 5962-10207 01 & 02 QS15 Product Name: * PIC = Aeroflex’s internal Product Identification Code 1.0 Overview The purpose of this application note is to discuss the Aeroflex SRAMs low power read architecture and to inform users of the affects associated with the low power read operations. 2.0 Low Power Read Architecture The aforementioned Aeroflex designed SRAMs all employ an architecture which reduces power consumption during read accesses. The architecture internally senses data only when new data is requested. A request for new data occurs anytime the chip enable device pin is asserted, or any of the device address inputs transition states while the chip enable is asserted. A trigger is generated and sent to the sensing circuit anytime a request for new data is observed. Since several triggers could occur simultaneously, these triggers are wire-ORed to result in a single sense amplifier activity for the read request. This design method results in less power consumption than designs that continually sense data. Aeroflex’s low power SRAMs listed above activate the sensing circuit for approximately 5ns whenever and access is requested, thereby, significantly reducing active power. Creation Date: 8/19/11 Page 1 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 2.1 The SRAM Read Cycles. The data sheets for all the devices noted in Table #1 discuss three methods for performing a read operation. The two most common methods for reading data are an Address Access and a Chip Enabled-Controlled Access. The third access discussed is the Output Enable-Controlled Access. The sequence at which control lines and address inputs are toggled determines which cycle is considered relevant. As discussed in section 2.0, an assertion of chip enable or any address transition while chip enable is asserted, initiates a read cycle. If the device chip enable is asserted prior to any address input transitions, then the read access is considered an Address Access. By keeping the device enabled and repeatedly switching address locations, the user retrieves all data of interest. A Chip Enable-Controlled Access occurs when the address signals are stable prior to asserting the chip enable. The Output Enabled-Controlled Access requires that either an Address Access or Chip Enable-Controlled Access has already been performed and the data is waiting for the Output Enable pin to assert, driving data to the device I/O pins. The subsequent read cycle verbiage and diagrams are based on the Aeroflex UT8R512K8 data sheet. The number of control, input, and I/O pins will vary across the products listed in Table 1. The basic design family functionality for read operations is common among all the devices. 2.1.0 Address Access Read Cycle The Address Access is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as chip enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (tAVAV). tAVAV A(18:0) DQ(7:0) Previous Valid Data Valid Data tAVQV Assumptions: 1. E1 and G < VIL (max) and E2 and W > VIH (min) tAXQX Note: No time references are relevant with respect to Chip Enable(s). Chip Enable(s) is assumed to be asserted. SRAM Read Cycle 1: Address Access Creation Date: 8/19/11 Page 2 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 2.1.1 Chip Enable-Controlled Read Cycle The Chip Enable-controlled Access is initiated by E1 and E2 going active while G remains asserted, W remains deasserted, and the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0) is accessed and appears at the data outputs DQ(7:0). A(18:0) E1 low or E2 high tETQV tETQX DQ(7:0) tEFQZ DATA VALID Assumptions: 1. G < VIL (max) and W > VIH (min) Note: No specification is given for address set-up time with respect to chip enable assertion. The read cycle description states that addresses are to remain stable for the entire cycle. Address set-up time relative to chip enable is assumed to be 0ns minimum. SRAM Read Cycle 2: Chip Enable Access 2.1.1 Output Enabled-Controlled Read Cycle The Output Enable-controlled Access is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. tAVQV A(18:0) G tGHQZ tGLQX DATA VALID DQ(7:0) tGLQV Assumptions: 1. E1 < VIL (max) , E2 > and W > VIH (min) SRAM Read Cycle 3: Output Enable Access 3.0 Low Power Read Architecture Timing Consideration The low power read architecture employed by Aeroflex designed SRAMs results in significant power reduction, especially in applications with longer than minimum read cycle times. However, this type of architecture is responsive to excessive input signal skew when device addressing and chip enable assertion occur simultaneously. Signal skew of greater than 4-5ns between all of the read triggering activities is sufficient to start another read cycle. Creation Date: 8/19/11 Page 3 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 3.1 Simultaneous Control and Address Switching Simultaneous switching of controls and address pins, alone, is not a problem; excessive skew between them is the concern. Consider the application where several SRAM devices are connected to the same memory bus. The address bus is commonly connected to all the devices, but the chip enable pin is singularly connected to each individual SRAM. This configuration results in a loading difference between the address inputs and the chip enable. This lightly loaded chip enable propagates to the memory more quickly than the heavily loaded address lines. The oscilloscope capture of Figure #1 is the actual timing of an application which had intermittent data errors due to address transitions lagging chip enable. Address Signal (Ax) Chip Enable (/E) Timing shown from VIL (yellow trace /CS) and VIH (pink for address signal) as delta X = 6ns. Even at actual internal gate switching point (~ VDD/2), the skew is still around 6ns. Figure #1 SRAM Signal Capture The signal transitions in the scope plot of Figure #1 appear to be fairly coincidental. A closer look however, reveals the chip enable signal actually starts and reaches VIL approximately 6ns before the address signal reaches VIH. Even at one half VDD (closer to actual logical gate switching of the inputs), the delta in signal times is still approximately 6ns. Simultaneous switching of controls and address inputs is not recommended for a couple of reasons. The first is the previously described signal skew sensitivity between controls and/or address inputs. The second reason is that activating all the controls and address inputs simultaneously results in peak instantaneous current consumption. This condition causes maximum strain to the power decoupling. Chip Enable activates address decoding circuits, address switching introduces input buffer switching current, and output enable assertion turns on all the device output drivers. Peforming all three simultaneously results in worst case transient current demand by the memory. 3.1.0 Technical Overview of Skew Sensitivity Recall from section 2.0 that any activity requesting new data causes a read trigger. The triggers are wire-ORed together. In order to meet the faster access times demanded by today’s applications, the ORed trigger only exists during the first 4-5ns of the read cycle. Since the slowest of the address transitions occurs more than 5ns after the initiation of the read activity, a second read activity is initiated. The sensing circuit does not have time to normalize before the second read activity has started. For this reason a Chip Enable-Controlled read cycle requires that address inputs remain stable for the entire cycle. Infrequent and random sensing errors can result if the bit columns are continually pulled to one state then quickly requested to sense the opposite state. Another effect of the low power read architecture that differs from previous generation designs (those that continually sense for data) is that the bit line will not be sensed again until another read triggering event occurs. If another read trigger event (chip enable assertion and/or address change) does no occur for a particular address, the incorrect data remains at the outputs. Creation Date: 8/19/11 Page 4 of 5 Modification Date: 4/24/13 Aeroflex Colorado Springs Application Note AN-MEM-002 4.0 Summary and Conclusion The Aeroflex SRAMs in Table #1 all employ a low power consumption read architecture. Power is conserved by sensing data only when new data is requested. A request occurs anytime chip enable is asserted or any address input signal transitions while chip enable is asserted. The data sheets for the SRAMs listed in Table #1 do not explicitly define the case of simultaneous switching of address and control signals during read operations. Data sheet read cycle descriptions indicate that control inputs are established prior to address changes, and address inputs are stable prior to control assertions. Simultaneous switching of addresses and controls is tolerable, when the skew between all input signals is < 4ns. For designs that must employ the simultaneous activation of address and control signals, two important issues should be considered by the designer. The first is the input signal skew sensitivity of the low power read architecture discussed by this application note. The second is the instantaneous current consumption that results from simultaneous access methods. Aeroflex recommends the use of only one read access method at a time. If multiple read accesses (simultaneous chip enable assertion and address switching) cannot be avoided, then Aeroflex recommends that the chip enable signal be delayed until all addresses have completed transitions. Creation Date: 8/19/11 Page 5 of 5 Modification Date: 4/24/13