UT8ER512K32 - Aeroflex Microelectronic Solutions

Standard Products
UT8ER512K32 Monolithic 16M SRAM
Data Sheet
July 24, 2012
www.aeroflex.com/memories
INTRODUCTION
FEATURES
 20ns Read, 10ns Write maximum access times
 Functionally compatible with traditional 512K x 32 SRAM
devices
 CMOS compatible input and output levels, three-state
bidirectional data bus
- I/O Voltage 3.3 volt, 1.8 volt core
 Operational environment:
- Total-dose: 100 krad(Si)
The UT8ER512K32 is a high-performance CMOS static RAM
organized as 524,288 words by 32 bits. Easy memory expansion
is provided by active LOW and HIGH chip enables (E1, E2), an
active LOW output enable (G), and three-state drivers. This
device has a power-down feature that reduces power
consumption by more than 90% when deselected.
Writing to the device is accomplished by driving chip enable one
(E1) input LOW, chip enable two (E2) HIGH and write enable
(W) input LOW. Data on the 32 I/O pins (DQ0 through DQ31)
is then written into the location specified on the address pins (A0
through A18). Reading from the device is accomplished by
taking chip enable one (E1) and output enable (G) LOW while
forcing write enable (W) and chip enable two (E2) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins will appear on the I/O pins.
- SEL Immune: <111MeV-cm2/mg
- SEU error rate = 8.1x10-16 errors/bit-day assuming
geosynchronous orbit, Adam’s 90% worst environment,
and 6600ns default Scrub Rate Period (=97% SRAM
availability)
 Packaging options:
- 68-lead ceramic quad flatpack (6.898 grams)
 Standard Microcircuit Drawing 5962-06261
- QML Q & V
The 32 input/output pins (DQ0 through DQ31) are placed in a
high impedance state when the device is deselected (E1 HIGH
or E2 LOW), the outputs are disabled (G HIGH), or during a
write operation (E1 LOW, E2 HIGH and W LOW).
A0
A1
W
A2
E1
Pre-Charge Circuit
A3
E2
A4
Memory Array
512K x 32
A5
Row Select
A6
A7
A8
I/O Circuit
A9
A17
G
DQ(31) to DQ(0)
A18
Read/Write
Circuit
Column Select
Data Control
A10 A11 A12 A13 A14 A15 A16
EDAC
BUSY, SCRUB
MBE
Figure 1. UT8ER512K32 SRAM Block Diagram
1
UT8ER512K32 Master or Slave Options
PIN DESCRIPTIONS
To reduce the bit error rates, the UT8ER512K32 employs an
embedded EDAC (error detection and correction) with user
programmable auto scrubbing options. The UT8ER512K32
device automatically corrects single bit word errors in event of
an upset. During a read operation, if a multiple bit error occurs
in a word, the UT8ER512K32 asserts the MBE (multiple bit
error) output to notify the host.
Pins
Type
Description
A(18:0)
I
Address
DQ(31:0)
BI
Data Input/Output
E1
I
Enable (Active Low)
E2
I
Enable (Active High)
W
I
Write Enable
G
I
Output Enable
VDD1
P
Power (1.8)
VDD2
P
Power (3.3V)
VSS
P
Ground
MBE
BI
Multiple Bit Error
SCRUB
I
Slave SCRUB Input
SCRUB
O
Master SCRUB Output
BUSY
NC
Slave No Connect
BUSY
O
Master Wait State Control
The UT8ER512K32 is offered in two options: Master
(UT8ER512K32M) or Slave (UT8ER512K32S). The master is
a full function device which features user defined autonomous
EDAC scrubbing options. The slave device employs a scrub on
demand feature.
The UT8ER512K32M (master) and UT8ER512K32S (slave)
device pins SCRUB and BUSY are physically different. The
SCRUB pin is an output on master devices, but an input on slave
devices. The master SCRUB pin asserts low when a scrub cycle
initiates, and can be used to demand scrub cycles from multiple
slave units when connected to the SCRUB input of slave(s). The
BUSY pin is an output for the master device and can be used to
generate wait states by the memory controller. The BUSY pin
is a no connect (NC) for slave units.
The UT8ER512K32 has four control inputs called Enable 1
(E1), Enable 2 (E2), Write Enable (W), and Output Enable (G);
19 address inputs, A(18:0); and 32 bidirectional data lines,
DQ(31:0). E1 and E2 device enables control device selection,
active, and standby modes. Asserting E1 and E2 enables the
device, causes IDD to rise to its active value, and decodes the 19
address inputs to select one of 524,288 words in the memory. W
controls read and write operations. During a read cycle, G must
be asserted to enable the outputs.
W
A6
A7
A8
A9
A10
VDD1
A18
A17
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Table 1. SRAM Device Control Operation Truth Table
Busy
MBE
VDD2
VSS
SCRUB
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
1
2
3
4
5
Top View
6
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
VDD1
A11
A12
A13
A14
A15
A16
E1
G
E2
VDD2
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VSS
VSS
A0
A1
A2
A3
A4
A5
DEVICE OPERATION
G
W
E2
E1
I/O Mode
Mode
X
X
X
H
DQ(31:0)
3-State
Standby
X
X
L
X
DQ(31:0)
3-State
Standby
L
H
H
L
DQ(31:0)
Data Out
Word Read
H
H
H
L
DQ(31:0)
All 3-State
Word Read2
X
L
H
L
DQ(31:0)
Data In
Word Write
Figure 2. 20ns SRAM Pinout (68)
Note: Pin 31 on the UT8ER512K32S (Slave) is a no connect (NC).
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
2
WRITE CYCLE
Table 2. EDAC Control Pin Operation Truth Table
MBE
SCRUB
BUSY
I/O Mode
Mode
H
H
H
Read
Uncorrectable
Multiple Bit Error
L
H
H
Read
Valid Data Out
X
H
H
X
Device Ready
X
H
L
X
Device Ready /
Scrub Request
Pending
X
L
X
Not
Accessible
Device Busy
A combination of W and E1 less than VIL(max), and E2 greater
than VIH(min) defines a write cycle. The state of G is a “don’t
care” for a write cycle. The outputs are placed in the highimpedance state when either G is greater than VIH(min), or when
W is less than VIL(max).
Write Cycle 1, the Write Enable-controlled Access in Figure 4a,
is defined by a write terminated by W going high, with E1 and
E2 still active. The write pulse width is defined by tWLWH when
the write is initiated by W, and by tETWH when the write is
initiated by E1 and E2. To avoid bus contention tWLQZ must be
satisfied before data is applied to the 32 bidirectional pins
DQ(31:0) unless the outputs have been previously placed in high
impedance state by deasserting G.
Notes:
1. “X” is defined as a “don’t care” condition
2. Busy signal is a "NC" for UT8ER512K32S slave device and is an "X" don’t
care.
READ CYCLE
Write Cycle 2, the Chip Enable-controlled Access in Figure 4b,
is defined by a write terminated by the latter of E1 or E2 going
inactive. The write pulse width is defined by tWLEF when the
write is initiated by W, and by tETEF when the write is initiated
by either E1or E2 going active. For the W initiated write, unless
the outputs have been previously placed in the high-impedance
state by G, the user must wait tWLQZ before applying data to the
thirty-two bidirectional pins DQ(31:0) to avoid bus contention.
A combination of W and E2 greater than VIH (min) and E1 and
G less than VIL (max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while E1 and E2 are
asserted, G is asserted, and W is deasserted. Valid data appears
on data outputs DQ(31:0) after the specified tAVQV is satisfied.
Outputs remain active throughout the entire cycle. As long as
device enable and output enable are active, the minimum time
between valid address changes is specified by the read cycle
time (tAVAV).
CONTROL REGISTER WRITE/READ CYCLES
Configuration options can be selected by writing to the control
register. The configuration table (Table 4) details the
programming options. The control register is accessed by
applying a series of values to the address bus as shown in Figure
6a. The contents of the control register are written following the
fifth address. The contents of the address bus are written to the
control register if bit 9 is zero. The contents of the control register
are output to the data bus if bit 9 is one. NOTE: MBE must be
driven high by the user for both a write or a read of the control
register.
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by the latter of either E1and E2 going
active while G remains asserted, W remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
tETQV is satisfied, the 32-bit word addressed by A(18:0) is
accessed and appears at the data outputs DQ(31:0).
MEMORY SCRUBBING/CYCLE STEALING
SRAM Read Cycle 3, the Output Enable-controlled Access in
Figure 3c, is initiated by G going active while E1 and E2 are
asserted, W is deasserted, and the addresses are stable. Read
access time is tGLQV unless tAVQV or tETQV (reference Figure
3b) have not been satisfied.
The UT8ER512K32 SRAM uses architectural improvements
and embedded error detection and correction to maintain
unsurpassed levels of error protection. This is accomplished by
what Aeroflex refers to as Cycle Stealing. To minimize the
system design impact on the speed of operation, the edge
relationship between BUSY and SCRUB is programmable via
the sequence described in figure 6a.
SRAM EDAC Status Indications during a Read Cycle, if MBE
is Low, the data is good. If MBE is High the data is corrupted
(reference Table 2).
The effective error rate is a function of the intrinsic rate and the
environment. As a result, some users may desire an increased
scrub rate to lower the error rate at the sacrifice of reduced total
throughput, while others may desire a lower scrub rate to
3
increase the total throughput and accept a higher error rate. This
rate at which the SRAM controller will correct errors from the
memory is user programmable. The required sequence is
described in figure 6a.
Table 3. Operational Environment Design Specifications1
A master mode scrub cycle will occur at the user defined Scrub
Rate Period. A scrub cycle is defined as the verification and
correction (if necessary) of data for a single word address
location. Address locations are scrubbed sequentially every
Scrub Rate Period (tSCRT). Scrub cycles will occur at every
Scrub Rate Period regardless of the status of control pins.
Control pin function will be returned upon deassertion of BUSY
pin. The Slave mode scrub cycle occurs anytime the SCRUB
pin is asserted. The scrub cycle is defined the same as the master
mode, and will occur regardless of control pin status. Control
pin function will be returned upon SCRUB deassertion.
Total Dose
100K
rad(Si)
Heavy Ion
Error Rate2
8.1x10-16
Errors/Bit-Day
Notes:
1. The SRAM is immune to latchup to particles <111MeV-cm2/mg.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum and default EDAC scrub rate.
SUPPLY SEQUENCING
No supply voltage sequencing is required between VDD1 and
VDD2.
POWER-UP REQUIREMENTS
During power-up of the UT8ER512K32 device, the power
supply voltages will transverse through voltage ranges where
the device is not guaranteed to operate before reaching final
levels. Since some circuits on the device will start to operate at
lower voltage levels than others, the device may power-up in an
unknown state. To eliminate this with most power-up situations,
the device employs an on-chip power-on-reset (POR) circuit.
The POR, however, requires time to complete the operation.
Therefore, it is recommended that all device activity be delayed
by a minimum of 100ms, after both VDD1 and VDD2 supplies
have reached their respective minimum operating voltage.
Data is not only corrected during the internal scrub, but again
during a user requested read cycle. If the data presented contains two or more errors after tAVAV is satisfied, the MBE signal
will be asserted. (Note: Reading un-initialized memory
locations may result in un-intended MBE assertions.)
Operational Environment
The UT8ER512K32 SRAM incorporates special design, layout,
and process features which allows operation in a limited
environment.
4
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL
PARAMETER
LIMITS
VDD1
DC supply voltage (Core)
-0.3 to 2.1V
VDD2
DC supply voltage (I/O)
-0.3 to 3.8V
VI/O
Voltage on any pin
-0.3 to 3.8V
TSTG
Storage temperature
-65 to +150C
PD2
Maximum package power dissipation
permitted @ Tc = +125oC
TJ
JC
II
5W
Maximum junction temperature
+150C
Thermal resistance, junction-to-case2
5C/W
±10 mA
DC input current
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Per MIL-STD-883, Method 1012, Section 3.4.1, PD = (TJC(max) - Tc (max))
JC
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
VDD1
DC supply voltage (Core)
1.7 to 1.9V1
VDD2
DC supply voltage (I/O)
3.0 to 3.6V
TC
Case temperature range
(C) Screening: -55 to +125C
(W) Screening: -40 to +125C
VIN
DC input voltage
0V to VDD2
Notes:
1. For increased noise immunity, supply voltage VDD1 can be increased to 2.0V. All characteristics contained herein are guaranteed by characterization at VDD1
= 2.0Vdc unless otherwise specified.
5
DC ELECTRICAL CHARACTERISTICS (Pre and Post-Radiation)*
(Tc = -55C to +125C for (C) screening and -40C to +125C for (W) screening) (VDD1 = 1.7V to 1.9V; VDD2 = 3.0V to 3.6V)
SYMBOL
PARAMETER
VIH
High-level input voltage
VIL
Low-level input voltage
0.3*VDD2
V
VOL1
Low-level output voltage IOL = 8mA,VDD2 =VDD2 (min)
0.2*VDD2
V
VOH
High-level output
voltage
IOH = -4mA,VDD2 =VDD2 (min)
CIN2
Input capacitance
 = 1MHz @ 0V
12
pF
CIO2
Bidirectional I/O
capacitance
 = 1MHz @ 0V
12
pF
Input leakage current
VIN = VDD2 and VSS
-2
2
A
IOZ3
Three-state output
leakage current
VO = VDD2 and VSS
VDD2 = VDD2 (max), G = VDD2 (max)
-2
2
A
IOS4, 5
Short-circuit output
current
VDD2 = VDD2 (max), VO = VDD2
VDD2 = VDD2 (max), VO = VSS
-100
+100
mA
25
mA
70
mA
65
mA
250
mA
300
mA
270
mA
IIN
CONDITION
MIN
MAX
0.7*VDD2
IDD1(OP16,7,8) VDD1 Supply current
operating
@ 1MHz, EDAC enabled
@ default Scrub Rate
Period (see table 4).
Inputs : VIL = VSS + 0.2V,
-55oC and 25oC
VIH = VDD2 -0.2V, IOUT = 0
VDD1= 2.0V
VDD1 = VDD1 (max),
125oC
VDD1 = 1.9V
VDD2 = VDD2 (max)
IDD1(OP26,7,8) VDD1 Supply current
operating
@ 50MHz, EDAC
enabled @ default Scrub
Rate Period (see table 4).
Inputs: VIL = VSS + 0.2V,
-55oC and 25oC
VIH = VDD2 -0.2V, IOUT = 0
VDD1 = 2.0V
VDD1 = VDD1 (max),
125oC
VDD1 = 1.9V
VDD2 = VDD2 (max)
UNIT
V
0.8*VDD2
V
IDD2(OP16,8)
VDD2 Supply current
operating
@ 1MHz, EDAC enabled
@ default Scrub Rate
Period (see table 4).
Inputs : VIL = VSS + 0.2V,
VIH = VDD2 -0.2V, IOUT = 0
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
2
mA
IDD2(OP26,8)
VDD2 Supply current
Inputs : VIL = VSS + 0.2V,
operating
VIH = VDD2 -0.2V, IOUT = 0
@ 50MHz, EDAC
VDD1 = VDD1 (max), VDD2 = VDD2 (max)
enabled @ default Scrub
Rate Period (see table 4).
5
mA
6
SYMBOL
IDD1(SB)7,9
PARAMETER
CONDITION
Supply current standby
CMOS inputs, IOUT = 0
@ 0Hz, EDAC bypassed E1 = V
DD2 -0.2, E2 = GND
VDD1 = VDD1 (max), VDD2
= VDD2 (max)
IDD2(SB)9
IDD1(SB)7,9
IDD2(SB)9
MIN
MAX
UNIT
-55oC and 25oC
25
mA
125oC
70
mA
2
mA
-55oC and 25oC
25
mA
125oC
70
mA
2
mA
Supply current standby
CMOS inputs, IOUT = 0
@ 0Hz, EDAC bypassed E1 = V
DD2 -0.2, E2 = GND
VDD1 = VDD1 (max), VDD2
= VDD2 (max)
Supply current standby
A(18:0) @ 50MHz,
EDAC bypassed
Supply current standby
A(18:0) @ 50MHz,
EDAC bypassed
CMOS inputs, IOUT = 0
E1 = VDD2 - 0.2, E2 = GND,
VDD1 = VDD1 (max), VDD2
= VDD2 (max)
CMOS inputs, IOUT = 0
E1 = VDD2 - 0.2, E2 = GND,
VDD1 = VDD1 (max), VDD2
= VDD2 (max)
Notes:
* For devices procured with a total ionizing dose tolerance, the post-irradiation performance is guaranteed.
1. The SCRUB and BUSY pins for UT8ER512K32M (master) are tested functionally for VOL specification.
2. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
3. The SCRUB and BUSY pins for UT8ER512K32M (master) are guaranteed by design, but neither tested nor characterized.
4. Supplied as a design limit but not guaranteed or tested.
5. Not more than one output may be shorted at a time for maximum duration of one second.
6. EDAC enabled. Default Scrub Rate Period applicable to master device only.
7. Post radiation limits are the 125oC temperature limit when specified.
8. Operating current limit includes standby current.
9. VIH = VDD2 (max), VIL = 0V.
7
AC CHARACTERISTICS READ CYCLE (Pre and Post-Radiation)*
(Tc = -55C to +125C for (C) screening and -40C to +125C for (W) screening, VDD1 = 1.7V to 1.9V, VDD2 = 3.0V to 3.6V)
SYMBOL
PARAMETER
MIN
UNIT
FIGURE
ns
3a
ns
3c
MAX
tAVAV11
Read cycle time
tAVQV1
Address to data valid from address change
tAXQX2
Output hold time
3
ns
3a
tGLQX1,2
G-controlled output enable time
2
ns
3c
8
ns
3c
6
ns
3c
ns
3b
20
ns
3b
7
ns
3b
20
ns
3a
tGLQV
20
20
G-controlled output data valid
tGHQZ12
G-controlled output three-state time
2
tETQX2,3
E-controlled output enable time
5
tETQV3
E-controlled access time
tEFQZ2,4
E-controlled output three-state time2
2
tAVMV
Address to error flag valid
tAXMX2
Address to error flag hold time from address change
3
ns
3a
tGLMX2
G-controlled error flag enable time
2
ns
3c
tGLMV
G-controlled error flag valid
ns
3c
tETMX2
E-controlled error flag enable time
ns
3b
tETMV3
E-controlled error flag time
20
ns
3b
tGHMZ2
G-controlled error flag three-state time
6
ns
3b
7
5
2
Notes:
* For devices procured with a total ionizing dose tolerance, the post-irradiation performance is guaranteed.
1. Guaranteed by characterization, but not tested.
2. Three-state is defined as a 300mV change from steady-state output voltage.
3. The ET (enable true) notation refers to the latter falling edge of E1 or rising edge of E2.
4. The EF (enable false) notation refers to the latter rising edge of E1 or falling edge of E2.
8
tAVAV1
A(18:0)
DQ(31:0)
Previous Valid Data
Valid Data
MBE
Assumptions:
1. E1 and G < VIL (max) and E2 and W > VIH
(min)
2. SCRUB > VOH (min)
3. Reading uninitialized addresses will cause MBE
to be asserted.
Figure
Valid Data
tAVQV1, tAVMV
tAXQX, tAXMX
3a. SRAM Read Cycle 1: Address Access
A(18:0)
Latter of E1 low,
and E2 high
tETQV, tETMV
tETQX, tETMX
tEFQZ
DQ(31:0)
DATA VALID
MBE
DATA VALID
Assumptions:
1. G < VIL (max) and W > VIH (min)
2. SCRUB > VOH (min)
3. Reading uninitialized addresses will cause MBE
to be asserted.
Figure
3b. SRAM Read Cycle 2: Chip Enable Access
tAVQV1
tAVMV
A(18:0)
tGLQV
G
tGHQZ1
tGLQX1
DQ(31:0)
DATA VALID
tGLMX
MBE
DATA VALID
Assumptions:
1. E1 < VIL (max), E2 and W > VIH (min)
tGLMV
tGHMZ
2. SCRUB > VOH (min)
3. Reading uninitialized addresses will cause
Figure
MBE to be asserted.
3c. SRAM Read Cycle 3: Output Enable Access
9
AC CHARACTERISTICS WRITE CYCLE (Pre and Post-Radiation)*
(Tc = -55C to +125C for (C) screening and -40C to +125C for (W) screening, VDD1 = 1.7V to 1.9V, VDD2 = 3.0V to 3.6V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
FIGURE
tAVAV21
Write cycle time
10
ns
4a/4b
tETWH
Device enable to end of write
10
ns
4a
tAVET
Address setup time for write (E1/E2- controlled)
0
ns
4b
tAVWL
Address setup time for write (W - controlled)
0
ns
4a
tWLWH1
Write pulse width
8
ns
4a
tWHAX
Address hold time for write (W - controlled)
0
ns
4a
tEFAX
Address hold time for device enable (E1/E2- controlled)
0
ns
4b
ns
4a/4b
tWLQZ2
W - controlled three-state time
7
tWHQX2
W - controlled output enable time
3
ns
4a
tETEF
Device enable pulse width (E1/E2 - controlled)
10
ns
4b
tDVWH
Data setup time
5
ns
4a
tWHDX
Data hold time
2
ns
4a
tWLEF1
Device enable controlled write pulse width
8
ns
4b
tDVEF
Data setup time
5
ns
4a/4b
tEFDX
Data hold time
2
ns
4b
tAVWH
Address valid to end of write
10
ns
4a
tWHWL1
Write disable time
2
ns
4a
Notes:
* For devices procured with a total ionizing dose tolerance, the post-irradiation performance is guaranteed.
1. Tested with G high.
2. Three-state is defined as 300mV change from steady-state output voltage.
10
A(18:0)
tAVAV2
E1
tAVWH
E2
tETWH, tWLEF
tWHWL
W
tAVWL
tWLWH
tWHAX
Q(31:0)
tWHQX
tWLQZ
D(31:0)
APPLIED DATA
tDVWH, tDVEF
Assumptions:
1. G < VIL (max). (If G > VIH (min) then Q(31:0) and MBE will be in threestate for the entire cycle.)
tWHDX
2. SCRUB > VOH (min)
Figure 4a. SRAM Write Cycle 1: W - Controlled Access
11
tAVAV2
A(18:0)
tETEF
tAVET
tEFAX
E1
E2
or
tEFAX
tAVET
E1
E2
tWLEF
W
APPLIED DATA
D(31:0)
tDVEF
Q(31:0)
tEFDX
Assumptions & Notes:
1. G < VIL (max). (If G > VIH (min) then Q(31:0) and MBE will be in three-state for the entire cycle.)
2. Either E1 / E2 scenario can occur.
3. SCRUB > VOH (min)
Figure 4b. SRAM Write Cycle 2: Enable - Controlled Access
12
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
S c r u b R a te P e r io d (D e fa u lt = 7 h )
B U S Y to S C R U B (D e fa u lt = A h )
E D A C B y p a s s (D e fa u lt = 0 h )
R e a d / W r ite C o n tr o l R e g is te r
N o te :
1 . S e e T a b le 4 f o r C o n t r o l R e g is t e r D e f in it io n s
Figure 5. EDAC Control Register
Table 4: EDAC Programming Configuration Table
ADDR BIT
A (0 - 3)
PARAMETER
Scrub Rate Period
1,2,3
VALUE
FUNCTION
3-15
As Scrub Rate Period changes from 0 - 15, then the interval
between Scrub cycles will change as follows:
3 = 600 ns
8 = 13.0 us
12 = 205 us
Note:
0-2
4 = 1000 ns
reserved 5 = 1800 ns
6 = 3400 ns
7 = 6600 ns
9 = 25.8 us
13 = 409.8 us4
10 = 51.4 us
14 = 819.4 us4
11 = 102.6 us
15 = 1.64 ms4
BUSY to SCRUB1,3,5
0-15
If BUSY changes from 0 - 15, then the interval tBLSL
between SCRUB and BUSY will change as follows:
0 = 0 ns
6 = 300 ns
11 = 550 ns
1 = 50 ns
7 = 350 ns
12 = 600 ns
2 = 100 ns
8 = 400 ns
13 = 650 ns
3 = 150 ns
9 = 450 ns
14 = 700 ns
4 = 200 ns
10 = 500 ns
15 = 750 ns
5 = 250ns
A (8)
Bypass EDAC Bit 6
0, 1
If 0, then normal EDAC operation will occur.
If 1, then EDAC will be bypassed.
A (9)
Read / Write Control Register
0, 1
0 = A0 to A8 will be written to the control register
1 = Control register will be asserted to the data bus
A (4 - 7)
Notes:
1. Values based on minimum specifications. For guaranteed ranges of Scrub Rate Period (tSCRT) and BUSY to SCRUB (tBLSL), reference the Master Mode
AC Characteristic table.
2. Default Scrub Rate Period is 6600 ns.
3. Scrub Rate Period and BUSY to SCRUB applicable to the UT8ER512K32M device only.
4. Period below test capability.
5. The default for tBLSL is 500 ns.
6. The default state for A8 is 0.
13
EDAC CONTROL REGISTER AC CHARACTERISTICS (Pre and Post-Radiation)*
(-55C to +125C for (C) screening and -40C to +125C for (W) screening, VDD1 = 1.7V to 1.9V, VDD2 = 3.0V to 3.6V
SYMBOL
PARAMETER
MIN
UNIT
FIGURE
MAX
tAVAV3
Address valid to address valid for control register cycle
200
ns
6a
tAVCL
Address valid to control low
400
ns
6a
tAVEX
Address valid to enable valid
200
ns
6a
tAVQV3
Address to data valid control register read
ns
6a
tCHAV
MBE high to address valid
0
ns
6a
tCLAX
MBE low to address hold time
0
ns
6a
tMLQX1
MBE control EDAC disable time
3
ns
6a
tGHQZ31
Output tri-state time
2
ns
6a
tMLGL2
MBE low to output enable
85
ns
6a
400
9
Notes:
* For devices procured with a total ionizing dose tolerance, the post-irradiation performance is guaranteed.
1. Three-state is defined as 300mV change from steady-state output.
2. Guaranteed by design neither tested or characterized.
E2
Valid E1 and E2, Device Enabled
E1
tGHQZ3
tCLAX
G
tCHAV
tMLGL
MBE1,2
tAVEX
ADDR (18:0)
70000h
7FF00h
3A500h
55A00h
00XYZh
10500h
tMLQX
tAVCL
tAVAV3
Control Reg.
Read
DQ (8:0)
t
AVQV3
Note:
1. MBE is driven high by the user.
2. Device must see a transistion to address 70000h coincident with or subsequent to MBE assertion.
3. Lower 10 bits of the last address are used to read or configure the control register (ref Control Register Write/Read Cycles page 3 and Table 4).
Assumptions:
1. SCRUB > VOH before the start of the configuration cycle. Ignore SCRUB during configuration cycle.
Figure 6a. EDAC Control Register Cycle
14
MASTER MODE AC CHARACTERISTICS (Pre and Post-Radiation)*
(-55C to +125C for (C) screening and -40C to +125C for (W) screening, VDD1 = 1.7V to 1.9V, VDD2 = 3.0V to 3.6V
SYMBOL
PARAMETER
MIN
tBLSL1
User Programmable - BUSY low to SCRUB
tSLSH1
UNIT
FIGURE
MAX
(50)(n)
(90)(n)+1
ns
6b
SCRUB low to SCRUB high
200
350
ns
6b
tSHBH
SCRUB high to BUSY high
50
85
ns
6b
tSCRT2
Scrub Rate Period
(2n)(50)+200 (2n)(90)+350
ns
Notes:
* For devices procured with a total ionizing dose tolerance, the post-irradiation performance is guaranteed.
1. See Table 4 for User Programmable information. The value "n" is decimal equivalent of hexidecimal value 0x0 through 0xF programmed into control register
address bits A4-A7 by user. Default value "n" = 10.
2. See Table 4 for User Programmable information. The value "n" is decimal equivalent of hexidecimal value 0x3 through 0xF programmed into control register
address bits A0-A3. Default value is "n" = 7.
tSLSH1
SCRUB
BUSY
tBLSL
tSHBH
Assumptions:
1. The conditions pertain to both a Read or Write.
Figure 6b. Master Mode Scrub Cycle
SLAVE MODE AC CHARACTERISTICS (Pre and Post-Radiation)*
(-55C to +125C for (C) screening and -40C to +125C for (W) screening, VDD1 = VDD1 (min), VDD2 = VDD2 (min))
SYMBOL
PARAMETER
MIN
MAX
UNIT
FIGURE
tSLSH2
SCRUB low to SCRUB high (slave)
200
ns
6c
tSHSL1
SCRUB high to SCRUB low (slave)
400
ns
6c
Notes:
* For devices procured with a total ionizing dose tolerance, the post-irradiation performance is guaranteed.
1. Guaranteed by design, neither tested nor characterized.
tSLSH2
SCRUB
tSHSL
Assumptions:
1. The conditions pertain to both a Read or Write.
Figure 6c. Slave Mode Scrub Cycle
15
V DD2
V DD2
R TE R M
100-ohm s
C L = 40pF
DUT
Test
Point
Zo = 50-ohm s
R TE R M
100-ohm s
VDD2
VSS
90%
90%
10%
< 2ns
10%
CMOS Input Pulses
< 2ns
Notes:
1. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = VDD2/2
Figure 7. AC Test Loads and Input Waveforms
16
PACKAGING
Notes:
1. All exposed metallized areas are gold plated over nickel
per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance with MIL-PRF-38535.
Figure 8. 68-Lead Ceramic Quad Flatpack
17
ORDERING INFORMATION
512K x 32 SRAM
UT **** - * *
* * *
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Screening:
(C) = HiRel Temperature Range flow (-55C to +125C)
(P) = Prototype flow
Package Type:
(W) = 68-lead ceramic quad flatpack
Access Time:
(21) = 20ns read / 10ns write access times
Device Type:
(8ER512K32M) =512K x 32 SRAM Master Device
(8ER512K32S) = 512K x 32 SRAM Slave Device
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. Radiation neither tested nor
guaranteed.
4. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation
neither tested nor guaranteed.
18
512K x 32 SRAM: SMD
5962
*****
* * *
Lead Finish: (Notes 1 & 2)
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
Case Outline:
(X) = 68-lead ceramic quad flatpack
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Device Type
(05) = 20ns read / 10ns write Master Device (-55C to +125C)
(06) = 20ns read / 10ns write Slave Device (-55C to +125C)
Drawing Number: 06261
Total Dose: (Note 3)
(R ) = 100 krad(Si)
Federal Stock Class Designator: No options
Notes:
1.Lead finish (A,C, or X) must be specified.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.TID tolerance guarantee is tested in accordance with MIL-STD-883 Test Method 1019 Condition A and section 3.11.2 resulting in an effective dose rate of
1 rad(Si)/sec.
19
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced HiRel
COLORADO
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www.aeroflex.com
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Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights,
trademark rights, or any other of the intellectual rights of
Aeroflex or of third parties.
Our passion for performance is defined by three
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20
Aeroflex Colorado Springs Application Note
AN-MEM-002
Low Power SRAM Read Operations
Table 1: Cross Reference of Applicable Products
Manufacturer
Part Number
SMD #
Device Type
Internal PIC
Number:*
4M Asynchronous SRAM
UT8R128K32
5962-03236
01 & 02
WC03
4M Asynchronous SRAM
UT8R512K8
5962-03235
01 & 02
WC01
16M Asynchronous SRAM
UT8CR512K32
5962-04227
01 & 02
MQ08
16M Asynchronous SRAM
UT8ER512K32
5962-06261
05 & 06
WC04/05
4M Asynchronous SRAM
UT8Q512E
5962-99607
05 & 06
WJ02
4M Asynchronous SRAM
UT9Q512E
5962-00536
05 & 06
WJ01
16M Asynchronous SRAM
UT8Q512K32E
5962-01533
02 & 03
QS04
16M Asynchronous SRAM
UT9Q512K32E
5962-01511
02 & 03
QS03
32M Asynchronous SRAM
UT8ER1M32
5962-10202
01 - 04
QS16/17
64M Asynchronous SRAM
UT8ER2M32
5962-10203
01 - 04
QS09/10
128M Asynchronous SRAM
UT8ER4M32
5962-10204
01 - 04
QS11/12
40M Asynchronous SRAM
UT8R1M39
5962-10205
01 & 02
QS13
80M Asynchronous SRAM
UT8R2M39
5962-10206
01 & 02
QS14
160M Asynchronous SRAM
UT8R4M39
5962-10207
01 & 02
QS15
Product Name:
* PIC = Aeroflex’s internal Product Identification Code
1.0 Overview
The purpose of this application note is to discuss the Aeroflex SRAMs low power read architecture and to inform users of the
affects associated with the low power read operations.
2.0 Low Power Read Architecture
The aforementioned Aeroflex designed SRAMs all employ an architecture which reduces power consumption during read
accesses. The architecture internally senses data only when new data is requested. A request for new data occurs anytime the
chip enable device pin is asserted, or any of the device address inputs transition states while the chip enable is asserted. A trigger is generated and sent to the sensing circuit anytime a request for new data is observed. Since several triggers could occur
simultaneously, these triggers are wire-ORed to result in a single sense amplifier activity for the read request. This design
method results in less power consumption than designs that continually sense data. Aeroflex’s low power SRAMs listed above
activate the sensing circuit for approximately 5ns whenever and access is requested, thereby, significantly reducing active
power.
Creation Date: 8/19/11
Page 1 of 5
Modification Date: 4/24/13
Aeroflex Colorado Springs Application Note
AN-MEM-002
2.1 The SRAM Read Cycles.
The data sheets for all the devices noted in Table #1 discuss three methods for performing a read operation. The two most common methods for reading data are an Address Access and a Chip Enabled-Controlled Access. The third access discussed is the
Output Enable-Controlled Access. The sequence at which control lines and address inputs are toggled determines which cycle
is considered relevant. As discussed in section 2.0, an assertion of chip enable or any address transition while chip enable is
asserted, initiates a read cycle. If the device chip enable is asserted prior to any address input transitions, then the read access
is considered an Address Access. By keeping the device enabled and repeatedly switching address locations, the user retrieves
all data of interest. A Chip Enable-Controlled Access occurs when the address signals are stable prior to asserting the chip
enable. The Output Enabled-Controlled Access requires that either an Address Access or Chip Enable-Controlled Access has
already been performed and the data is waiting for the Output Enable pin to assert, driving data to the device I/O pins.
The subsequent read cycle verbiage and diagrams are based on the Aeroflex UT8R512K8 data sheet. The number of control,
input, and I/O pins will vary across the products listed in Table 1. The basic design family functionality for read operations is
common among all the devices.
2.1.0 Address Access Read Cycle
The Address Access is initiated by a change in address inputs while the chip is enabled with G asserted and W deasserted. Valid
data appears on data outputs DQ(7:0) after the specified tAVQV is satisfied. Outputs remain active throughout the entire cycle.
As long as chip enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle
time (tAVAV).
tAVAV
A(18:0)
DQ(7:0)
Previous Valid Data
Valid Data
tAVQV
Assumptions:
1. E1 and G < VIL (max) and E2 and W > VIH (min)
tAXQX
Note: No time references are relevant with respect to Chip Enable(s). Chip Enable(s) is assumed to be asserted.
SRAM Read Cycle 1: Address Access
Creation Date: 8/19/11
Page 2 of 5
Modification Date: 4/24/13
Aeroflex Colorado Springs Application Note
AN-MEM-002
2.1.1 Chip Enable-Controlled Read Cycle
The Chip Enable-controlled Access is initiated by E1 and E2 going active while G remains asserted, W remains deasserted, and
the addresses remain stable for the entire cycle. After the specified tETQV is satisfied, the eight-bit word addressed by A(18:0)
is accessed and appears at the data outputs DQ(7:0).
A(18:0)
E1 low or
E2 high
tETQV
tETQX
DQ(7:0)
tEFQZ
DATA VALID
Assumptions:
1. G < VIL (max) and W > VIH (min)
Note: No specification is given for address set-up time with respect to chip enable assertion. The read cycle description states that
addresses are to remain stable for the entire cycle. Address set-up time relative to chip enable is assumed to be 0ns minimum.
SRAM Read Cycle 2: Chip Enable Access
2.1.1 Output Enabled-Controlled Read Cycle
The Output Enable-controlled Access is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the
addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied.
tAVQV
A(18:0)
G
tGHQZ
tGLQX
DATA VALID
DQ(7:0)
tGLQV
Assumptions:
1. E1 < VIL (max) , E2 > and W > VIH (min)
SRAM Read Cycle 3: Output Enable Access
3.0 Low Power Read Architecture Timing Consideration
The low power read architecture employed by Aeroflex designed SRAMs results in significant power reduction, especially in
applications with longer than minimum read cycle times. However, this type of architecture is responsive to excessive input
signal skew when device addressing and chip enable assertion occur simultaneously. Signal skew of greater than 4-5ns
between all of the read triggering activities is sufficient to start another read cycle.
Creation Date: 8/19/11
Page 3 of 5
Modification Date: 4/24/13
Aeroflex Colorado Springs Application Note
AN-MEM-002
3.1 Simultaneous Control and Address Switching
Simultaneous switching of controls and address pins, alone, is not a problem; excessive skew between them is the concern.
Consider the application where several SRAM devices are connected to the same memory bus. The address bus is commonly
connected to all the devices, but the chip enable pin is singularly connected to each individual SRAM. This configuration
results in a loading difference between the address inputs and the chip enable. This lightly loaded chip enable propagates to the
memory more quickly than the heavily loaded address lines. The oscilloscope capture of Figure #1 is the actual timing of an
application which had intermittent data errors due to address transitions lagging chip enable.
Address Signal (Ax)
Chip Enable (/E)

Timing shown from VIL (yellow trace /CS) and VIH (pink for address signal) as delta X =
6ns. Even at actual internal gate switching point (~ VDD/2), the skew is still around 6ns.
Figure #1 SRAM Signal Capture
The signal transitions in the scope plot of Figure #1 appear to be fairly coincidental. A closer look however, reveals the chip
enable signal actually starts and reaches VIL approximately 6ns before the address signal reaches VIH. Even at one half VDD
(closer to actual logical gate switching of the inputs), the delta in signal times is still approximately 6ns.
Simultaneous switching of controls and address inputs is not recommended for a couple of reasons. The first is the previously
described signal skew sensitivity between controls and/or address inputs. The second reason is that activating all the controls
and address inputs simultaneously results in peak instantaneous current consumption. This condition causes maximum strain
to the power decoupling. Chip Enable activates address decoding circuits, address switching introduces input buffer switching
current, and output enable assertion turns on all the device output drivers. Peforming all three simultaneously results in worst
case transient current demand by the memory.
3.1.0 Technical Overview of Skew Sensitivity
Recall from section 2.0 that any activity requesting new data causes a read trigger. The triggers are wire-ORed together. In
order to meet the faster access times demanded by today’s applications, the ORed trigger only exists during the first 4-5ns of
the read cycle. Since the slowest of the address transitions occurs more than 5ns after the initiation of the read activity, a second read activity is initiated. The sensing circuit does not have time to normalize before the second read activity has started.
For this reason a Chip Enable-Controlled read cycle requires that address inputs remain stable for the entire cycle. Infrequent
and random sensing errors can result if the bit columns are continually pulled to one state then quickly requested to sense the
opposite state. Another effect of the low power read architecture that differs from previous generation designs (those that continually sense for data) is that the bit line will not be sensed again until another read triggering event occurs. If another read
trigger event (chip enable assertion and/or address change) does no occur for a particular address, the incorrect data remains at
the outputs.
Creation Date: 8/19/11
Page 4 of 5
Modification Date: 4/24/13
Aeroflex Colorado Springs Application Note
AN-MEM-002
4.0 Summary and Conclusion
The Aeroflex SRAMs in Table #1 all employ a low power consumption read architecture. Power is conserved by sensing data
only when new data is requested. A request occurs anytime chip enable is asserted or any address input signal transitions while
chip enable is asserted. The data sheets for the SRAMs listed in Table #1 do not explicitly define the case of simultaneous
switching of address and control signals during read operations. Data sheet read cycle descriptions indicate that control inputs
are established prior to address changes, and address inputs are stable prior to control assertions. Simultaneous switching of
addresses and controls is tolerable, when the skew between all input signals is < 4ns. For designs that must employ the simultaneous activation of address and control signals, two important issues should be considered by the designer. The first is the
input signal skew sensitivity of the low power read architecture discussed by this application note. The second is the instantaneous current consumption that results from simultaneous access methods. Aeroflex recommends the use of only one read
access method at a time. If multiple read accesses (simultaneous chip enable assertion and address switching) cannot be
avoided, then Aeroflex recommends that the chip enable signal be delayed until all addresses have completed transitions.
Creation Date: 8/19/11
Page 5 of 5
Modification Date: 4/24/13