HD74LS248 BCD-to-Seven-Segment Decoder / Driver (internal pull-up outputs) REJ03D0466–0300 Rev.3.00 Jul.15.2005 The HD74LS248 is electrically and functionally identical to the HD74LS48, respectively, and has the same pin assignments as its equivalents. It can be used interchangeably in present or future designs to offer designers a choice between two indicator fonts. The HD74LS48 composes the 6 and the 9 without tails and the HD74LS248 composes the 6 and the 9 with tails. Composition of all other characters, including display patterns for BCD inputs above nine, is identical. The HD74LS248 features active-low outputs designed for driving indicators directly. All of the circuits have full ripple-blanking input / output controls and a lamp test input. Segment identification and resultant displays are shown below. Display patterns for BCD input count above 9 are unique symbols to authenticate input conditions. This circuit incorporates automatic leading and / or trailing-edge zero-blanking control (RBI and RBO). Lamp test (LT) of this type may be performed at any time when the BI / RBO node is at a high level. This type contains an overriding blanking input (BI) which can be used to control the lamp intensity be pulsing or to inhibit the outputs. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS248FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) Pin Arrangement B 1 C 2 Lamp Test RB Output RB Input D 6 A 7 GND 8 16 VCC 15 f Inputs B f 3 C g 14 g 4 LT a 13 a BI/BRO b RBI c 12 b D d 11 c A e 10 d 9 e 5 Inputs (Top view) Rev.3.00, Jul.15.2005, page 1 of 6 Outputs HD74LS248 Function Table Decimal or Function 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT Inputs LT RBI D C B A BI/ RBO H H H H H H H H H H H H H H H H X H L H X X X X X X X X X X X X X X X X L X L L L L L L L L H H H H H H H H X L X L L L L H H H H L L L L H H H H X L X L L H H L L H H L L H H L L H H X L X L H L H L H L H L H L H L H L H X L X H H H H H H H H H H H H H H H H L L H Outputs a b c d e f g H L H H L H H H H H L L L H L L L L H H H H H H L L H H H L L H L L L L L H H H L H H H H H H H L H L L L L L L H H L H H L H H L H H H H L H H L L L H H L H L L L H L H L H L L L H L L L H H L L L H H H L H H L L H H H L L L H L L H H H H H L H H H H H H H L L L H Note 1 2 3 4 H; high level, L; low level, X; irrelevant Notes: 1. The blanking input (BI) must be open or held at a high logic level when output functions 0 through 15 are desired. The ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired. 2. When a low logic level is applied directly to the blanking input (BI), all segment outputs are off regardless of the level of any other input. 3. When ripple-blanking input (RBI) and inputs A, B, C, and D are a low level with the lamp test input high, all segment outputs go off and the ripple-blanking output (RBO) goes to a low level (response condition). 4. When a blanking input ripple blanking input (BI/RBO) is open or held high and a low is applied to the lamptest input, all segment outputs are on. Rev.3.00, Jul.15.2005, page 2 of 6 HD74LS248 Block Diagram a A B b C c Inputs D d BI/BRO Blanking Input or Ripple Blanking Output Outputs e f Lamp Test Input RBI Ripple Blanking Input g Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC 7 V Input voltage VIN 7 V PT 400 mW Tstg –65 to +150 °C Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Rev.3.00, Jul.15.2005, page 3 of 6 HD74LS248 Recommended Operating Conditions Item Symbol Min Typ Max Supply voltage VCC 4.75 5.00 5.25 V Operating temperature Topr –20 25 75 °C — — –100 µA — — –50 µA a to g IOH BI/RBO Output current a to g IOL BI/RBO Unit — — 6 mA — — 3.2 mA a f g e b c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 d Electrical Characteristics (Ta = –20 to +75 °C) Item Symbol min. typ.* max. Unit VIH VIL 2.0 — — — — 0.8 V V VOH 2.4 — — V IO –1.3 — — mA VOL — — — — — — — — 0.4 0.5 0.4 0.5 V IOL = 2 mA IOL = 6 mA IOL = 1.6 mA IOL = 3.2 mA Except BI/RBO IIH — — 20 µA VCC = 5.25 V, VI = 2.7 V Except BI/RBO BI/RBI IIL — — –0.4 mA VCC = 5.25 V, VI = 0.4 V — — –1.2 Except BI/RBO II — — 0.1 mA VCC = 5.25 V, VI = 7 V Input voltage Output voltage a to g BI/RBO Output current** a to g a to g Output voltage BI/RBO Input current Short-circuit BI/RBO IOS –0.3 — –2 mA output current Supply current*** ICC — 25 38 mA Input clamp voltage VIK — — –1.5 V Notes: * VCC = 5 V, Ta = 25°C ** Input condition as for VOH. *** ICC is measured with all outputs open and all inputs at 4.5 V. Condition IOH = –100 µA IOH = –50 µA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V VCC = 4.75 V, VO = 0.85 V VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Propagation delay time Symbol tPLH tPHL tPLH tPHL Rev.3.00, Jul.15.2005, page 4 of 6 Input A RBI min. — — — — typ. — — — — max. 100 100 100 100 Unit Condition ns CL = 15 pF, RL = 4 kΩ ns CL = 15 pF, RL = 6 kΩ HD74LS248 Testing Method Test Circuit VCC 4.5V RL See Testing Table a Input P.G. Zout = 50Ω Note: A B C D b Output c d CL e LT RBI f BI/RBO g CL includes probe and jig capacitance. Testing Table Item ton toff RBI 4.5V 4.5V 4.5V IN D GND GND GND GND Inputs C GND GND 4.5V GND B GND 4.5V 4.5V GND A IN IN IN GND a OUT — — OUT b — — OUT OUT c — OUT — OUT Outputs d OUT — OUT OUT e OUT OUT OUT OUT f OUT — OUT OUT Waveform tTHL tTLH 90% 1.3 V Input 3V 90% 1.3 V 10% 10% 0V tPHL tPLH VOH In phase output 1.3 V 1.3 V VOL tPHL tPLH VOH Out of phase output 1.3 V 1.3 V VOL Note: Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% Rev.3.00, Jul.15.2005, page 5 of 6 g — — OUT — HD74LS248 Package Dimensions JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 2.20 A L1 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 1.27 e x 0.12 y 0.15 0.80 Z 0.50 L L Rev.3.00, Jul.15.2005, page 6 of 6 8° 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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