Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1C PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1CN0 Pin Name/Function TDI TMS TRST TCK TDO IO IO IO IO IO IO IO IO IO IO NC NC IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) RDN1A RUP1A Configuration Function TDI TMS TRST TCK TDO Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_TX_L1n DIFFIO_TX_L1p DIFFIO_RX_L1n DIFFIO_RX_L1p DIFFIO_TX_L2n DIFFIO_TX_L2p DIFFIO_RX_L2n DIFFIO_RX_L2p DIFFIO_TX_L3n DIFFIO_TX_L3p DIFFOUT_L1n DIFFOUT_L1p DIFFOUT_L2n DIFFOUT_L2p DIFFOUT_L3n DIFFOUT_L3p DIFFOUT_L4n DIFFOUT_L4p DIFFOUT_L5n DIFFOUT_L5p DIFFIO_TX_L4n DIFFIO_TX_L4p DIFFIO_RX_L4n DIFFIO_RX_L4p DIFFIO_TX_L5n DIFFIO_TX_L5p DIFFIO_RX_L5n DIFFIO_RX_L5p DIFFIO_TX_L6n DIFFIO_TX_L6p DIFFIO_RX_L6n DIFFIO_RX_L6p DIFFIO_TX_L7n DIFFIO_TX_L7p DIFFIO_RX_L7n DIFFIO_RX_L7p DIFFIO_TX_L8n DIFFIO_TX_L8p DIFFIO_RX_L8n DIFFIO_RX_L8p DIFFIO_TX_L9n DIFFIO_TX_L9p DIFFIO_RX_L9n DIFFIO_RX_L9p DIFFIO_TX_L10n DIFFIO_TX_L10p DIFFIO_TX_L11n DIFFIO_TX_L11p DIFFIO_RX_L11n DIFFIO_RX_L11p DIFFIO_TX_L12n DIFFIO_TX_L12p DIFFIO_RX_L12p DIFFIO_TX_L13n DIFFOUT_L7n DIFFOUT_L7p DIFFOUT_L8n DIFFOUT_L8p DIFFOUT_L9n DIFFOUT_L9p DIFFOUT_L10n DIFFOUT_L10p DIFFOUT_L11n DIFFOUT_L11p DIFFOUT_L12n DIFFOUT_L12p DIFFOUT_L13n DIFFOUT_L13p DIFFOUT_L14n DIFFOUT_L14p DIFFOUT_L15n DIFFOUT_L15p DIFFOUT_L16n DIFFOUT_L16p DIFFOUT_L17n DIFFOUT_L17p DIFFOUT_L18n DIFFOUT_L18p DIFFOUT_L19n DIFFOUT_L19p DIFFOUT_L21n DIFFOUT_L21p DIFFOUT_L22n DIFFOUT_L22p DIFFOUT_L23n DIFFOUT_L23p DIFFOUT_L24p DIFFOUT_L25n Pin List F1517 J29 N27 A32 G30 F30 K29 L29 C34 D34 J30 K30 C31 D31 M28 N28 C35 D35 H32 J32 B32 C32 M31 N31 C33 D33 M30 N30 G31 H31 M29 N29 E31 F31 K31 L31 E32 F32 R28 T28 E34 F34 R27 T27 J33 K32 F33 G33 P29 R29 H34 L32 Dynamic OCT Support No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 DQ1L DQ1L DQSn1L DQS1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQSn3L DQS3L DQ3L DQ3L DQSn4L DQS4L DQ4L DQ4L DQ4L DQ4L DQ5L DQ5L DQSn5L DQS5L DQ5L DQ5L DQSn6L DQS6L DQ6L DQ6L DQ7L DQ7L DQSn7L DQS7L DQ7L DQ7L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ2L DQ2L/CQn2L DQ2L DQ2L DQSn2L/DQ2L DQS2L/CQ2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQ3L DQ3L/CQn3L DQ3L DQ3L DQSn3L/DQ3L DQS3L/CQ3L DQ3L DQ3L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ8L DQ8L DQ8L Page 1 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C VREF VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 1C 1C 1C VREFB1CN0 VREFB1CN0 VREFB1CN0 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 1C 1C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C VREFB1CN0 VREFB1CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO NC IO IO IO NC NC IO IO IO IO IO IO IO IO IO IO IO IO NC NC NC NC CLK1n CLK1p CLK3p CLK3n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_TX_L13p DIFFIO_TX_L14n DIFFIO_TX_L14p DIFFIO_TX_L15p DIFFIO_RX_L15n DIFFIO_RX_L15p DIFFIO_RX_L16n DIFFIO_RX_L16p DIFFIO_TX_L17n DIFFIO_TX_L17p Emulated LVDS Output Channel DIFFOUT_L25p DIFFOUT_L27n DIFFOUT_L27p DIFFOUT_L29p DIFFOUT_L30n DIFFOUT_L30p DIFFOUT_L32n DIFFOUT_L32p DIFFOUT_L33n DIFFOUT_L33p DIFFIO_RX_L17p DIFFOUT_L34p DIFFIO_TX_L18p DIFFOUT_L35p DIFFIO_TX_L19n DIFFIO_TX_L19p DIFFOUT_L37n DIFFOUT_L37p DIFFIO_RX_L19p DIFFIO_TX_L20n DIFFIO_TX_L20p DIFFOUT_L38p DIFFOUT_L39n DIFFOUT_L39p DIFFIO_TX_L21n DIFFIO_TX_L21p DIFFOUT_L41n DIFFOUT_L41p DIFFIO_TX_L24p DIFFIO_TX_L25p DIFFIO_TX_L25n DIFFIO_TX_L26p DIFFIO_TX_L26n DIFFIO_RX_L27p DIFFIO_RX_L28p DIFFIO_TX_L28p DIFFIO_TX_L28n DIFFIO_RX_L29p DIFFIO_RX_L29n DIFFIO_TX_L29p DIFFIO_TX_L29n DIFFIO_RX_L30p DIFFIO_TX_L30p DIFFOUT_L48p DIFFOUT_L50p DIFFOUT_L50n DIFFOUT_L52p DIFFOUT_L52n DIFFOUT_L53p DIFFOUT_L55p DIFFOUT_L56p DIFFOUT_L56n DIFFOUT_L57p DIFFOUT_L57n DIFFOUT_L58p DIFFOUT_L58n DIFFOUT_L59p DIFFOUT_L60p CLKUSR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 INIT_DONE CRC_ERROR DEV_OE DEV_CLRn CLK1n CLK1p CLK3p CLK3n Pin List F1517 M32 P32 P31 T30 N34 N33 M34 M33 V28 W28 L35 L34 R31 R30 V31 U31 W30 W29 N35 P34 V27 W26 R35 R34 V30 V29 U35 V34 W33 W32 W35 W34 J34 K34 AJ34 AH34 AB30 AB27 AB28 AC28 AC29 AK34 AL34 AD28 AD29 AH32 AH33 AE28 AE29 AN34 AD30 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1517 DQ8L DQ8L DQ8L DQ9L DQ9L DQ9L DQSn10L DQS10L DQ10L DQ10L DQS for X8/X9 for F1517 DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQ9L DQ9L/CQn9L DQ9L DQ9L DQS for X16/ X18 for F1517 DQ8L DQ8L DQ8L DQ8L DQ8L DQ8L DQSn8L/DQ8L DQS8L/CQ8L DQ8L DQ8L DQS11L DQS9L/CQ9L DQ8L DQ11L DQ9L DQ8L DQ12L DQ12L DQ10L DQ10L DQS12L DQ12L DQ12L DQ10L/CQn10L DQ10L DQ10L DQ13L DQ13L DQ10L DQ10L DQ14L DQ15L DQ15L DQ15L DQ15L DQ16L DQS16L DQ17L DQ17L DQS17L DQSn17L DQ17L DQ17L DQ18L DQ18L DQ17L DQ17L DQ17L DQ17L DQ17L DQ18L DQS18L/CQ18L DQ18L DQ18L DQ18L/CQn18L DQ18L DQ18L DQ18L DQ19L DQ19L DQ19L DQ19L DQ19L DQ19L DQS19L/CQ19L DQSn19L/DQ19L DQ19L DQ19L DQ19L DQ19L Page 2 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 2C 2C 2C 2C 2C 2C 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) RUP2A RDN2A Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_L31p DIFFIO_TX_L31p DIFFIO_TX_L31n DIFFIO_RX_L32p DIFFIO_RX_L32n DIFFIO_TX_L32p DIFFIO_RX_L33p DIFFIO_RX_L33n DIFFIO_TX_L33p DIFFIO_TX_L33n DIFFIO_RX_L34p DIFFIO_RX_L34n DIFFIO_TX_L34p DIFFIO_TX_L34n DIFFIO_RX_L35p DIFFIO_RX_L35n DIFFIO_TX_L35p DIFFIO_TX_L35n DIFFIO_RX_L36p DIFFIO_RX_L36n DIFFIO_TX_L36p DIFFIO_TX_L36n DIFFIO_TX_L37p DIFFIO_TX_L37n DIFFIO_RX_L38p DIFFIO_RX_L38n DIFFIO_TX_L38p DIFFIO_TX_L38n DIFFIO_RX_L39p DIFFIO_RX_L39n DIFFIO_TX_L39p DIFFIO_TX_L39n DIFFIO_RX_L40p DIFFIO_RX_L40n DIFFIO_TX_L40p DIFFIO_TX_L40n DIFFIO_RX_L41p DIFFIO_RX_L41n DIFFIO_TX_L41p DIFFIO_TX_L41n DIFFIO_RX_L42p DIFFIO_RX_L42n DIFFIO_TX_L42p DIFFIO_TX_L42n DIFFIO_RX_L43p DIFFIO_RX_L43n DIFFIO_TX_L43p DIFFIO_TX_L43n DIFFIO_RX_L44p DIFFIO_RX_L44n DIFFIO_TX_L44p Pin List Emulated LVDS Output Channel DIFFOUT_L61p DIFFOUT_L62p DIFFOUT_L62n DIFFOUT_L63p DIFFOUT_L63n DIFFOUT_L64p DIFFOUT_L65p DIFFOUT_L65n DIFFOUT_L66p DIFFOUT_L66n DIFFOUT_L67p DIFFOUT_L67n DIFFOUT_L68p DIFFOUT_L68n DIFFOUT_L69p DIFFOUT_L69n DIFFOUT_L70p DIFFOUT_L70n DIFFOUT_L71p DIFFOUT_L71n DIFFOUT_L72p DIFFOUT_L72n DIFFOUT_L74p DIFFOUT_L74n DIFFOUT_L75p DIFFOUT_L75n DIFFOUT_L76p DIFFOUT_L76n DIFFOUT_L77p DIFFOUT_L77n DIFFOUT_L78p DIFFOUT_L78n DIFFOUT_L79p DIFFOUT_L79n DIFFOUT_L80p DIFFOUT_L80n DIFFOUT_L81p DIFFOUT_L81n DIFFOUT_L82p DIFFOUT_L82n DIFFOUT_L83p DIFFOUT_L83n DIFFOUT_L84p DIFFOUT_L84n DIFFOUT_L85p DIFFOUT_L85n DIFFOUT_L86p DIFFOUT_L86n DIFFOUT_L87p DIFFOUT_L87n DIFFOUT_L88p F1517 AM34 AF29 AG30 AJ32 AK33 AE30 AN32 AP33 AC26 AD26 AN33 AP34 AD27 AE27 AT34 AR34 AJ31 AH30 AT33 AU33 AK32 AL32 AG29 AH29 AP32 AR32 AK31 AL31 AN30 AP30 AE26 AF26 AM31 AN31 AK30 AL30 AT31 AU31 AG28 AH28 AR31 AT30 AG27 AH27 AT32 AU32 AL29 AM29 AU34 AV34 AJ29 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1517 DQS18L DQ19L DQ19L DQS19L DQSn19L DQ19L DQS for X8/X9 for F1517 DQS19L/CQ19L DQ19L DQ19L DQ19L/CQn19L DQ19L DQ19L DQS for X16/ X18 for F1517 DQ19L/CQn19L DQ19L DQ19L DQ19L DQ19L DQ19L DQ20L DQ20L DQS20L DQSn20L DQ20L DQ20L DQ21L DQ21L DQ21L DQ21L DQS21L DQSn21L DQ22L DQ22L DQ22L DQ22L DQ23L DQ23L DQ23L DQ23L DQS23L DQSn23L DQ24L DQ24L DQS24L DQSn24L DQ24L DQ24L DQ25L DQ25L DQ25L DQ25L DQS25L DQSn25L DQ26L DQ26L DQS26L DQSn26L DQ26L DQ26L DQ24L DQ24L DQ24L DQ24L DQS24L/CQ24L DQSn24L/DQ24L DQ24L DQ24L DQ24L DQ24L DQ25L DQ25L DQ25L DQ25L DQS25L/CQ25L DQSn25L/DQ25L DQ25L DQ25L DQ25L/CQn25L DQ25L DQ25L DQ25L DQ26L DQ26L DQ26L DQ26L DQS26L/CQ26L DQSn26L/DQ26L DQ26L DQ26L DQ26L/CQn26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQS26L/CQ26L DQSn26L/DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L/CQn26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L DQ26L Page 3 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 2A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB2AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 Pin Name/Function IO nCONFIG nSTATUS CONF_DONE PORSEL nCE IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_TX_L44n Emulated LVDS Output Channel DIFFOUT_L88n nCONFIG nSTATUS CONF_DONE nCE RDN3A RUP3A DIFFIO_RX_B1n DIFFIO_RX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_RX_B3n DIFFIO_RX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_RX_B5n DIFFIO_RX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_RX_B8n DIFFIO_RX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_RX_B10n DIFFIO_RX_B10p DIFFIO_RX_B11n DIFFIO_RX_B11p Pin List DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B21p DIFFOUT_B22n DIFFOUT_B22p DIFFOUT_B23n F1517 AK29 AW36 AW35 AV35 AP29 AN29 AD25 AE25 AG25 AF25 AE24 AK27 AK26 AJ26 AH26 AL27 AK25 AJ25 AW34 AW33 AW32 AV32 AV31 AW31 AW30 AV29 AW28 AW27 AW29 AV28 AN27 AP27 AN26 AM26 AP26 AL25 AR28 AP28 AT29 AU29 AU28 AT28 AG24 AH24 AU27 AT27 AM25 AN25 AP24 AN24 AP25 Dynamic OCT Support Yes No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 DQ1B DQ1B DQSn1B DQS1B DQ1B DQ1B DQSn2B DQS2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQSn3B DQS3B DQ3B DQ3B DQSn4B DQS4B DQ4B DQ4B DQ4B DQ4B DQ5B DQ5B DQSn5B DQS5B DQ5B DQ5B DQSn6B DQS6B DQ6B DQ6B DQ6B DQ6B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQ3B DQ3B/CQn3B DQ3B DQ3B DQSn3B/DQ3B DQS3B/CQ3B DQ3B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ7B DQ7B DQSn7B DQS7B DQ7B DQ7B DQ7B DQ7B DQ7B/CQn7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B Page 4 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3BN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B12n DIFFIO_RX_B12p DIFFIO_RX_B13n DIFFIO_RX_B13p DIFFIO_RX_B14n DIFFIO_RX_B14p DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_RX_B16n DIFFIO_RX_B16p DIFFIO_RX_B17n DIFFIO_RX_B17p DIFFIO_RX_B18n DIFFIO_RX_B18p DIFFIO_RX_B19n DIFFIO_RX_B19p DIFFIO_RX_B20n DIFFIO_RX_B20p DIFFIO_RX_B21n DIFFIO_RX_B21p PLL_B1_CLKOUT4 PLL_B1_CLKOUT3 DIFFIO_RX_B22n DIFFIO_RX_B22p PLL_B1_CLKOUT0n PLL_B1_CLKOUT0p PLL_B1_FBn/CLKOUT2 PLL_B1_FBp/CLKOUT1 CLK5n CLK5p CLK4n CLK4p DIFFIO_RX_B23n DIFFIO_RX_B23p DIFFIO_RX_B24n DIFFIO_RX_B24p Pin List Emulated LVDS Output Channel DIFFOUT_B23p DIFFOUT_B24n DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B25p DIFFOUT_B26n DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B27p DIFFOUT_B28n DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B29p DIFFOUT_B30n DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B31p DIFFOUT_B32n DIFFOUT_B32p DIFFOUT_B33n DIFFOUT_B33p DIFFOUT_B34n DIFFOUT_B34p DIFFOUT_B35n DIFFOUT_B35p DIFFOUT_B36n DIFFOUT_B36p DIFFOUT_B37n DIFFOUT_B37p DIFFOUT_B38n DIFFOUT_B38p DIFFOUT_B39n DIFFOUT_B39p DIFFOUT_B40n DIFFOUT_B40p DIFFOUT_B41n DIFFOUT_B41p DIFFOUT_B42n DIFFOUT_B42p DIFFOUT_B43n DIFFOUT_B43p DIFFOUT_B44n DIFFOUT_B44p DIFFOUT_B45n DIFFOUT_B45p DIFFOUT_B46n DIFFOUT_B46p DIFFOUT_B47n DIFFOUT_B47p DIFFOUT_B48n DIFFOUT_B48p F1517 AR25 AU26 AT26 AT25 AU25 AW26 AV26 AH22 AE23 AG22 AF22 AE22 AF23 AL23 AK23 AK24 AJ22 AJ23 AH23 AN23 AM23 AN22 AM22 AL21 AL22 AU24 AT24 AR23 AP23 AU23 AT23 AG20 AD21 AF20 AE20 AE21 AG21 AW25 AV25 AJ20 AH20 AW23 AV23 AP21 AN21 AU22 AT22 AW22 AV22 AT21 AR22 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No DQS for X4 for F1517 DQ7B DQSn8B DQS8B DQ8B DQ8B DQ8B DQ8B DQ9B DQ9B DQSn9B DQS9B DQ9B DQ9B DQSn10B DQS10B DQ10B DQ10B DQ10B DQ10B DQ11B DQ11B DQSn11B DQS11B DQ11B DQ11B DQSn12B DQS12B DQ12B DQ12B DQ12B DQ12B DQ13B DQ13B DQSn13B DQS13B DQ13B DQ13B DQS for X8/X9 for F1517 DQ7B DQSn7B/DQ7B DQS7B/CQ7B DQ7B DQ7B DQ7B DQ7B DQ8B DQ8B DQ8B DQ8B/CQn8B DQ8B DQ8B DQSn8B/DQ8B DQS8B/CQ8B DQ8B DQ8B DQ8B DQ8B DQ11B DQ11B DQ11B DQ11B/CQn11B DQ11B DQ11B DQSn11B/DQ11B DQS11B/CQ11B DQ11B DQ11B DQ11B DQ11B DQS for X16/ X18 for F1517 DQ7B DQ7B DQ7B/CQn7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQSn7B/DQ7B DQS7B/CQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B DQ7B Page 5 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B 4B PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) CLK6p CLK6n CLK7p CLK7n PLL_B2_FBp/CLKOUT1 PLL_B2_FBn/CLKOUT2 PLL_B2_CLKOUT0p PLL_B2_CLKOUT0n Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B25p DIFFIO_RX_B25n DIFFIO_RX_B26p DIFFIO_RX_B26n DIFFIO_RX_B27p DIFFIO_RX_B27n PLL_B2_CLKOUT3 PLL_B2_CLKOUT4 DIFFIO_RX_B28p DIFFIO_RX_B28n DIFFIO_RX_B29p DIFFIO_RX_B29n DIFFIO_RX_B30p DIFFIO_RX_B30n DIFFIO_RX_B31p DIFFIO_RX_B31n DIFFIO_RX_B32p DIFFIO_RX_B32n DIFFIO_RX_B33p DIFFIO_RX_B33n DIFFIO_RX_B34p DIFFIO_RX_B34n DIFFIO_RX_B35p DIFFIO_RX_B35n DIFFIO_RX_B36p DIFFIO_RX_B36n DIFFIO_RX_B37p DIFFIO_RX_B37n Pin List Emulated LVDS Output Channel DIFFOUT_B49p DIFFOUT_B49n DIFFOUT_B50p DIFFOUT_B50n DIFFOUT_B51p DIFFOUT_B51n DIFFOUT_B52p DIFFOUT_B52n DIFFOUT_B53p DIFFOUT_B53n DIFFOUT_B54p DIFFOUT_B54n DIFFOUT_B55p DIFFOUT_B55n DIFFOUT_B56p DIFFOUT_B56n DIFFOUT_B57p DIFFOUT_B57n DIFFOUT_B58p DIFFOUT_B58n DIFFOUT_B59p DIFFOUT_B59n DIFFOUT_B60p DIFFOUT_B60n DIFFOUT_B61p DIFFOUT_B61n DIFFOUT_B62p DIFFOUT_B62n DIFFOUT_B63p DIFFOUT_B63n DIFFOUT_B64p DIFFOUT_B64n DIFFOUT_B65p DIFFOUT_B65n DIFFOUT_B66p DIFFOUT_B66n DIFFOUT_B67p DIFFOUT_B67n DIFFOUT_B68p DIFFOUT_B68n DIFFOUT_B69p DIFFOUT_B69n DIFFOUT_B70p DIFFOUT_B70n DIFFOUT_B71p DIFFOUT_B71n DIFFOUT_B72p DIFFOUT_B72n DIFFOUT_B73p DIFFOUT_B73n DIFFOUT_B74p F1517 AW20 AW21 AV19 AW19 AR20 AT20 AN20 AP20 AU20 AV20 AH18 AH19 AT19 AU19 AD19 AG19 AE19 AF19 AG18 AE18 AT18 AU18 AT17 AW18 AU17 AV17 AN19 AM19 AN18 AP18 AR19 AP19 AK17 AL17 AJ16 AM17 AK16 AL16 AH17 AE17 AF17 AG17 AH16 AG16 AP17 AR17 AN16 AN17 AP16 AR16 AW16 Dynamic OCT Support No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 DQ14B DQ14B DQS14B DQSn14B DQ14B DQ14B DQ15B DQ15B DQ15B DQ15B DQS15B DQSn15B DQ16B DQ16B DQS16B DQSn16B DQ16B DQ16B DQ17B DQ17B DQ17B DQ17B DQS17B DQSn17B DQ18B DQ18B DQS18B DQSn18B DQ18B DQ18B DQ19B DQ19B DQ19B DQ19B DQS19B DQSn19B DQ20B DQ16B DQ16B DQ16B DQ16B DQS16B/CQ16B DQSn16B/DQ16B DQ16B DQ16B DQ16B/CQn16B DQ16B DQ16B DQ16B DQ19B DQ19B DQ19B DQ19B DQS19B/CQ19B DQSn19B/DQ19B DQ19B DQ19B DQ19B/CQn19B DQ19B DQ19B DQ19B DQ20B DQ20B DQ20B DQ20B DQS20B/CQ20B DQSn20B/DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQS20B/CQ20B DQSn20B/DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B DQ20B/CQn20B DQ20B DQ20B Page 6 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 4B 4B 4B 4B 4B 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 5A PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4BN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB5AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO nIO_PULLUP nCEO DCLK nCSO ASDO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B38p DIFFIO_RX_B38n DIFFIO_RX_B39p DIFFIO_RX_B39n DIFFIO_RX_B40p DIFFIO_RX_B40n DIFFIO_RX_B41p DIFFIO_RX_B41n DIFFIO_RX_B42p DIFFIO_RX_B42n DIFFIO_RX_B43p DIFFIO_RX_B43n DIFFIO_RX_B44p DIFFIO_RX_B44n DIFFIO_RX_B45p DIFFIO_RX_B45n DIFFIO_RX_B46p DIFFIO_RX_B46n DIFFIO_RX_B47p DIFFIO_RX_B47n RUP4A RDN4A DIFFIO_RX_B48p DIFFIO_RX_B48n Emulated LVDS Output Channel DIFFOUT_B74n DIFFOUT_B75p DIFFOUT_B75n DIFFOUT_B76p DIFFOUT_B76n DIFFOUT_B77p DIFFOUT_B77n DIFFOUT_B78p DIFFOUT_B78n DIFFOUT_B79p DIFFOUT_B79n DIFFOUT_B80p DIFFOUT_B80n DIFFOUT_B81p DIFFOUT_B81n DIFFOUT_B82p DIFFOUT_B82n DIFFOUT_B83p DIFFOUT_B83n DIFFOUT_B84p DIFFOUT_B84n DIFFOUT_B85p DIFFOUT_B85n DIFFOUT_B86p DIFFOUT_B86n DIFFOUT_B87p DIFFOUT_B87n DIFFOUT_B88p DIFFOUT_B88n DIFFOUT_B89p DIFFOUT_B89n DIFFOUT_B90p DIFFOUT_B90n DIFFOUT_B91p DIFFOUT_B91n DIFFOUT_B92p DIFFOUT_B92n DIFFOUT_B93p DIFFOUT_B93n DIFFOUT_B94p DIFFOUT_B94n DIFFOUT_B95p DIFFOUT_B95n DIFFOUT_B96p DIFFOUT_B96n nIO_PULLUP nCEO DCLK nCSO ASDO DIFFIO_TX_R1n Pin List DIFFOUT_R1n F1517 AT16 AU16 AV16 AU15 AT15 AN15 AP15 AE16 AF16 AV14 AW14 AT14 AU14 AV13 AW13 AW12 AW11 AU11 AV11 AT12 AU12 AP14 AR14 AP13 AN14 AR13 AT13 AN13 AL15 AL13 AM13 AL14 AM14 AJ13 AK13 AH13 AK14 AH14 AJ14 AG14 AG15 AE14 AF14 AD15 AE15 AM11 AT11 AR11 AP11 AN11 AM10 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No Yes DQS for X4 for F1517 DQ20B DQS20B DQSn20B DQ20B DQ20B DQS for X8/X9 for F1517 DQ20B DQ20B/CQn20B DQ20B DQ20B DQ20B DQS for X16/ X18 for F1517 DQ20B DQ20B DQ20B DQ20B DQ20B DQ21B DQ21B DQ21B DQ21B DQS21B DQSn21B DQ22B DQ22B DQS22B DQSn22B DQ22B DQ22B DQ23B DQ23B DQ23B DQ23B DQS23B DQSn23B DQ24B DQ24B DQS24B DQSn24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B DQSn25B DQ26B DQ26B DQS26B DQSn26B DQ26B DQ26B DQ24B DQ24B DQ24B DQ24B DQS24B/CQ24B DQSn24B/DQ24B DQ24B DQ24B DQ24B/CQn24B DQ24B DQ24B DQ24B DQ25B DQ25B DQ25B DQ25B DQS25B/CQ25B DQSn25B/DQ25B DQ25B DQ25B DQ25B/CQn25B DQ25B DQ25B DQ25B DQ26B DQ26B DQ26B DQ26B DQS26B/CQ26B DQSn26B/DQ26B DQ26B DQ26B DQ26B/CQn26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQS26B/CQ26B DQSn26B/DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B/CQn26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B DQ26B Page 7 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5C 5C 5C 5C 5C 5C PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) RDN5A RUP5A Configuration Function Dedicated Tx/Rx Channel DIFFIO_TX_R1p DIFFIO_RX_R1n DIFFIO_RX_R1p DIFFIO_TX_R2n DIFFIO_TX_R2p DIFFIO_RX_R2n DIFFIO_RX_R2p DIFFIO_TX_R3n DIFFIO_TX_R3p DIFFIO_RX_R3n DIFFIO_RX_R3p DIFFIO_TX_R4n DIFFIO_TX_R4p DIFFIO_RX_R4n DIFFIO_RX_R4p DIFFIO_TX_R5n DIFFIO_TX_R5p DIFFIO_RX_R5n DIFFIO_RX_R5p DIFFIO_TX_R6n DIFFIO_TX_R6p DIFFIO_RX_R6n DIFFIO_RX_R6p DIFFIO_TX_R7n DIFFIO_TX_R7p DIFFIO_RX_R7n DIFFIO_RX_R7p DIFFIO_TX_R8n DIFFIO_TX_R8p DIFFIO_RX_R8n DIFFIO_RX_R8p DIFFIO_TX_R9n DIFFIO_TX_R9p DIFFIO_RX_R9n DIFFIO_RX_R9p DIFFIO_TX_R10n DIFFIO_TX_R10p DIFFIO_RX_R10n DIFFIO_RX_R10p DIFFIO_TX_R11n DIFFIO_TX_R11p DIFFIO_TX_R12n DIFFIO_TX_R12p DIFFIO_RX_R12n DIFFIO_RX_R12p DIFFIO_TX_R13n DIFFIO_TX_R13p DIFFIO_RX_R13p DIFFIO_TX_R14n DIFFIO_TX_R14p DIFFIO_RX_R14p Pin List Emulated LVDS Output Channel DIFFOUT_R1p DIFFOUT_R2n DIFFOUT_R2p DIFFOUT_R3n DIFFOUT_R3p DIFFOUT_R4n DIFFOUT_R4p DIFFOUT_R5n DIFFOUT_R5p DIFFOUT_R6n DIFFOUT_R6p DIFFOUT_R7n DIFFOUT_R7p DIFFOUT_R8n DIFFOUT_R8p DIFFOUT_R9n DIFFOUT_R9p DIFFOUT_R10n DIFFOUT_R10p DIFFOUT_R11n DIFFOUT_R11p DIFFOUT_R12n DIFFOUT_R12p DIFFOUT_R13n DIFFOUT_R13p DIFFOUT_R14n DIFFOUT_R14p DIFFOUT_R15n DIFFOUT_R15p DIFFOUT_R16n DIFFOUT_R16p DIFFOUT_R17n DIFFOUT_R17p DIFFOUT_R18n DIFFOUT_R18p DIFFOUT_R19n DIFFOUT_R19p DIFFOUT_R20n DIFFOUT_R20p DIFFOUT_R21n DIFFOUT_R21p DIFFOUT_R23n DIFFOUT_R23p DIFFOUT_R24n DIFFOUT_R24p DIFFOUT_R25n DIFFOUT_R25p DIFFOUT_R26p DIFFOUT_R27n DIFFOUT_R27p DIFFOUT_R28p F1517 AL10 AW7 AV7 AP10 AN10 AW8 AV8 AJ11 AH11 AU10 AT10 AH12 AG12 AW10 AV10 AG13 AF13 AU9 AT9 AP9 AN9 AU8 AT8 AP7 AN7 AR8 AP8 AL9 AK9 AU7 AT7 AM8 AL8 AU6 AT6 AJ10 AH10 AW4 AV5 AE12 AE13 AD12 AD13 AW5 AW6 AH8 AH9 AP6 AK7 AK8 AM6 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 DQ1R DQ1R DQSn1R DQS1R DQ1R DQ1R DQSn2R DQS2R DQ2R DQ2R DQ2R DQ2R DQ3R DQ3R DQSn3R DQS3R DQ3R DQ3R DQSn4R DQS4R DQ4R DQ4R DQ4R DQ4R DQ5R DQ5R DQSn5R DQS5R DQ5R DQ5R DQSn6R DQS6R DQ6R DQ6R DQ6R DQ6R DQ7R DQ7R DQ7R DQ7R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ2R DQ2R DQ2R DQ2R/CQn2R DQ2R DQ2R DQSn2R/DQ2R DQS2R/CQ2R DQ2R DQ2R DQ2R DQ2R DQ3R DQ3R DQ3R DQ3R/CQn3R DQ3R DQ3R DQSn3R/DQ3R DQS3R/CQ3R DQ3R DQ3R DQ3R DQ3R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ8R DQ8R DQS8R DQ8R DQ8R DQS9R DQ8R DQ8R DQ8R/CQn8R DQ8R DQ8R DQS8R/CQ8R DQ8R DQ8R DQ8R DQ8R DQ8R DQ8R/CQn8R Page 8 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK8n CLK8p CLK10p CLK10n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) PLL_R3_CLKOUT0n PLL_R3_FB_CLKOUT0p CLK8n CLK8p CLK10p CLK10n PLL_R2_FB_CLKOUT0p PLL_R2_CLKOUT0n Configuration Function Dedicated Tx/Rx Channel DIFFIO_TX_R15n DIFFIO_TX_R15p DIFFIO_RX_R15p DIFFIO_TX_R16n DIFFIO_TX_R16p DIFFIO_RX_R16p DIFFIO_TX_R17p DIFFIO_RX_R17p DIFFIO_TX_R18p DIFFIO_TX_R20n DIFFIO_TX_R20p DIFFIO_TX_R21n DIFFIO_TX_R21p DIFFIO_TX_R22n DIFFIO_TX_R22p Emulated LVDS Output Channel DIFFOUT_R29n DIFFOUT_R29p DIFFOUT_R30p DIFFOUT_R31n DIFFOUT_R31p DIFFOUT_R32p DIFFOUT_R33p DIFFOUT_R34p DIFFOUT_R35p DIFFOUT_R39n DIFFOUT_R39p DIFFOUT_R41n DIFFOUT_R41p DIFFOUT_R43n DIFFOUT_R43p DIFFIO_TX_R23p DIFFIO_TX_R23n DIFFIO_TX_R24p DIFFIO_TX_R24n DIFFIO_TX_R25p DIFFIO_TX_R26p DIFFIO_TX_R27p DIFFIO_TX_R27n DIFFIO_TX_R28p DIFFIO_TX_R28n DIFFIO_RX_R29p DIFFIO_RX_R30p DIFFIO_RX_R30n DIFFIO_TX_R30p DIFFIO_TX_R30n DIFFIO_RX_R31p DIFFIO_TX_R31p DIFFIO_TX_R31n DIFFIO_RX_R32p DIFFIO_TX_R32p DIFFIO_TX_R32n DIFFIO_RX_R33p DIFFIO_RX_R33n DIFFIO_TX_R33p DIFFIO_TX_R33n DIFFIO_RX_R34p DIFFIO_RX_R34n DIFFIO_TX_R34p DIFFIO_TX_R34n DIFFIO_TX_R35p DIFFIO_TX_R35n DIFFIO_RX_R36p DIFFOUT_R46p DIFFOUT_R46n DIFFOUT_R48p DIFFOUT_R48n DIFFOUT_R50p DIFFOUT_R52p DIFFOUT_R54p DIFFOUT_R54n DIFFOUT_R56p DIFFOUT_R56n DIFFOUT_R57p DIFFOUT_R59p DIFFOUT_R59n DIFFOUT_R60p DIFFOUT_R60n DIFFOUT_R61p DIFFOUT_R62p DIFFOUT_R62n DIFFOUT_R63p DIFFOUT_R64p DIFFOUT_R64n DIFFOUT_R65p DIFFOUT_R65n DIFFOUT_R66p DIFFOUT_R66n DIFFOUT_R67p DIFFOUT_R67n DIFFOUT_R68p DIFFOUT_R68n DIFFOUT_R70p DIFFOUT_R70n DIFFOUT_R71p Pin List F1517 AE10 AE11 AN6 AF10 AF11 AL6 AG10 AK6 AD10 AB10 AB11 AB12 AB13 AC10 AC11 AH6 AJ6 P6 N6 W12 W11 V12 V11 U10 V10 N9 P8 T10 R10 M6 N8 N7 M8 M7 K6 L8 L7 J6 K7 J7 G8 F8 T13 T12 F7 E7 H7 G7 R13 P13 G6 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1517 DQ9R DQ9R DQ9R DQ10R DQ10R DQS10R DQ10R DQS11R DQ11R DQ12R DQ12R DQ13R DQ13R DQS for X8/X9 for F1517 DQ8R DQ8R DQ8R DQ9R DQ9R DQ9R/CQn9R DQ9R DQS9R/CQ9R DQ9R DQ10R DQ10R DQ10R DQ10R DQ14R DQ14R DQ15R DQ15R DQ16R DQ16R DQ17R DQ17R DQS17R DQ18R DQ18R DQ18R DQ18R DQS18R DQ19R DQ19R DQS19R DQ19R DQ19R DQ17R DQ17R DQ17R DQ17R DQ18R DQ18R DQ18R DQ18R DQ18R/CQn18R DQ19R DQ19R DQ19R DQ19R DQS19R/CQ19R DQ19R DQ19R DQ19R/CQn19R DQ19R DQ19R DQ20R DQ20R DQS20R DQSn20R DQ20R DQ20R DQ21R DQ21R DQS21R DQ24R DQ24R DQS24R/CQ24R DQS for X16/ X18 for F1517 DQ8R DQ8R DQ8R DQ8R DQ8R DQS8R/CQ8R DQ8R DQ8R DQ8R DQ19R DQ19R DQ19R DQ19R DQS19R/CQ19R DQ19R DQ19R DQ19R DQ19R DQ19R/CQn19R DQ19R DQ19R DQ19R DQ19R DQ19R Page 9 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL2 MSEL1 MSEL0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function RUP6A RDN6A Dedicated Tx/Rx Channel DIFFIO_RX_R36n DIFFIO_TX_R36p DIFFIO_TX_R36n DIFFIO_RX_R37p DIFFIO_RX_R37n DIFFIO_TX_R37p DIFFIO_TX_R37n DIFFIO_RX_R38p DIFFIO_RX_R38n DIFFIO_TX_R38p DIFFIO_TX_R38n DIFFIO_RX_R39p DIFFIO_RX_R39n DIFFIO_TX_R39p DIFFIO_TX_R39n DIFFIO_RX_R40p DIFFIO_RX_R40n DIFFIO_TX_R40p DIFFIO_TX_R40n DIFFIO_RX_R41p DIFFIO_RX_R41n DIFFIO_TX_R41p DIFFIO_TX_R41n DIFFIO_TX_R42p DIFFIO_TX_R42n DIFFIO_RX_R43p DIFFIO_RX_R43n DIFFIO_TX_R43p DIFFIO_TX_R43n DIFFIO_RX_R44p DIFFIO_RX_R44n DIFFIO_TX_R44p DIFFIO_TX_R44n Emulated LVDS Output Channel DIFFOUT_R71n DIFFOUT_R72p DIFFOUT_R72n DIFFOUT_R73p DIFFOUT_R73n DIFFOUT_R74p DIFFOUT_R74n DIFFOUT_R75p DIFFOUT_R75n DIFFOUT_R76p DIFFOUT_R76n DIFFOUT_R77p DIFFOUT_R77n DIFFOUT_R78p DIFFOUT_R78n DIFFOUT_R79p DIFFOUT_R79n DIFFOUT_R80p DIFFOUT_R80n DIFFOUT_R81p DIFFOUT_R81n DIFFOUT_R82p DIFFOUT_R82n DIFFOUT_R84p DIFFOUT_R84n DIFFOUT_R85p DIFFOUT_R85n DIFFOUT_R86p DIFFOUT_R86n DIFFOUT_R87p DIFFOUT_R87n DIFFOUT_R88p DIFFOUT_R88n MSEL2 MSEL1 MSEL0 RDN7A RUP7A DIFFIO_RX_T1n DIFFIO_RX_T1p DIFFIO_RX_T2n DIFFIO_RX_T2p DIFFIO_RX_T3n DIFFIO_RX_T3p DIFFIO_RX_T4n Pin List DIFFOUT_T1n DIFFOUT_T1p DIFFOUT_T2n DIFFOUT_T2p DIFFOUT_T3n DIFFOUT_T3p DIFFOUT_T4n DIFFOUT_T4p DIFFOUT_T5n DIFFOUT_T5p DIFFOUT_T6n DIFFOUT_T6p DIFFOUT_T7n DIFFOUT_T7p DIFFOUT_T8n F1517 F6 R12 R11 G9 F9 N11 N10 F10 E10 M10 L10 D7 C7 K9 J9 D8 C8 K8 J8 D9 C9 M11 L11 N12 M12 D10 C10 K10 J10 D6 C6 H10 G10 A8 H11 J11 M13 N13 N14 P14 N15 R14 K13 L13 K12 M14 K14 L14 J13 J12 G13 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1517 DQSn21R DQ22R DQ22R DQS22R DQSn22R DQ22R DQ22R DQ23R DQ23R DQ23R DQ23R DQS23R DQSn23R DQ24R DQ24R DQS24R DQSn24R DQ24R DQ24R DQ25R DQ25R DQ25R DQ25R DQ26R DQ26R DQS26R DQSn26R DQ26R DQ26R DQS for X8/X9 for F1517 DQSn24R/DQ24R DQ24R DQ24R DQ24R/CQn24R DQ24R DQ24R DQ24R DQ25R DQ25R DQ25R DQ25R DQS25R/CQ25R DQSn25R/DQ25R DQ25R DQ25R DQ25R/CQn25R DQ25R DQ25R DQ25R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R/CQn26R DQ26R DQ26R DQ26R DQS for X16/ X18 for F1517 DQ1T DQ1T DQSn1T DQS1T DQ1T DQ1T DQSn2T DQS2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQSn3T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T/DQ1T DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQS26R/CQ26R DQSn26R/DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R DQ26R Page 10 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7B 7C 7C PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7BN0 VREFB7CN0 VREFB7CN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T4p DIFFIO_RX_T5n DIFFIO_RX_T5p DIFFIO_RX_T6n DIFFIO_RX_T6p DIFFIO_RX_T7n DIFFIO_RX_T7p DIFFIO_RX_T8n DIFFIO_RX_T8p DIFFIO_RX_T9n DIFFIO_RX_T9p DIFFIO_RX_T10n DIFFIO_RX_T10p DIFFIO_RX_T11n DIFFIO_RX_T11p DIFFIO_RX_T12n DIFFIO_RX_T12p DIFFIO_RX_T13n DIFFIO_RX_T13p DIFFIO_RX_T14n DIFFIO_RX_T14p DIFFIO_RX_T15n DIFFIO_RX_T15p DIFFIO_RX_T16n DIFFIO_RX_T16p Pin List Emulated LVDS Output Channel DIFFOUT_T8p DIFFOUT_T9n DIFFOUT_T9p DIFFOUT_T10n DIFFOUT_T10p DIFFOUT_T11n DIFFOUT_T11p DIFFOUT_T12n DIFFOUT_T12p DIFFOUT_T13n DIFFOUT_T13p DIFFOUT_T14n DIFFOUT_T14p DIFFOUT_T15n DIFFOUT_T15p DIFFOUT_T16n DIFFOUT_T16p DIFFOUT_T17n DIFFOUT_T17p DIFFOUT_T18n DIFFOUT_T18p DIFFOUT_T19n DIFFOUT_T19p DIFFOUT_T20n DIFFOUT_T20p DIFFOUT_T21n DIFFOUT_T21p DIFFOUT_T22n DIFFOUT_T22p DIFFOUT_T23n DIFFOUT_T23p DIFFOUT_T24n DIFFOUT_T24p DIFFOUT_T25n DIFFOUT_T25p DIFFOUT_T26n DIFFOUT_T26p DIFFOUT_T27n DIFFOUT_T27p DIFFOUT_T28n DIFFOUT_T28p DIFFOUT_T29n DIFFOUT_T29p DIFFOUT_T30n DIFFOUT_T30p DIFFOUT_T31n DIFFOUT_T31p DIFFOUT_T32n DIFFOUT_T32p DIFFOUT_T33n DIFFOUT_T33p F1517 H13 G14 H14 E13 F13 D13 F12 E14 F14 C11 A10 A11 B11 B10 D11 C14 D14 C13 C12 A13 B13 J15 K15 A14 B14 G15 E16 F16 G16 G17 F15 C15 D15 A16 D16 B16 C16 P16 P17 M16 N16 N17 M17 J16 K16 K17 L16 H17 J17 C17 F17 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1517 DQS3T DQ3T DQ3T DQSn4T DQS4T DQ4T DQ4T DQ4T DQ4T DQ5T DQ5T DQSn5T DQS5T DQ5T DQ5T DQSn6T DQS6T DQ6T DQ6T DQ6T DQ6T DQS for X8/X9 for F1517 DQ2T/CQn2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQ3T DQ3T/CQn3T DQ3T DQ3T DQSn3T/DQ3T DQS3T/CQ3T DQ3T DQ3T DQ3T DQ3T DQS for X16/ X18 for F1517 DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ7T DQ7T DQSn7T DQS7T DQ7T DQ7T DQSn8T DQS8T DQ8T DQ8T DQ8T DQ8T DQ9T DQ9T DQSn9T DQS9T DQ9T DQ9T DQSn10T DQS10T DQ10T DQ10T DQ10T DQ10T DQ11T DQ11T DQ7T DQ7T DQ7T DQ7T/CQn7T DQ7T DQ7T DQSn7T/DQ7T DQS7T/CQ7T DQ7T DQ7T DQ7T DQ7T DQ8T DQ8T DQ8T DQ8T/CQn8T DQ8T DQ8T DQSn8T/DQ8T DQS8T/CQ8T DQ8T DQ8T DQ8T DQ8T DQ11T DQ11T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T/CQn7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQSn7T/DQ7T DQS7T/CQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T DQ7T Page 11 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T17n DIFFIO_RX_T17p DIFFIO_RX_T18n DIFFIO_RX_T18p DIFFIO_RX_T19n DIFFIO_RX_T19p DIFFIO_RX_T20n DIFFIO_RX_T20p DIFFIO_RX_T21n DIFFIO_RX_T21p PLL_T2_CLKOUT4 PLL_T2_CLKOUT3 DIFFIO_RX_T22n DIFFIO_RX_T22p PLL_T2_CLKOUT0n PLL_T2_CLKOUT0p PLL_T2_FBn/CLKOUT2 PLL_T2_FBp/CLKOUT1 CLK13n CLK13p CLK12n CLK12p CLK14p CLK14n CLK15p CLK15n PLL_T1_FBp/CLKOUT1 PLL_T1_FBn/CLKOUT2 PLL_T1_CLKOUT0p PLL_T1_CLKOUT0n DIFFIO_RX_T23n DIFFIO_RX_T23p DIFFIO_RX_T24n DIFFIO_RX_T24p DIFFIO_RX_T25p DIFFIO_RX_T25n DIFFIO_RX_T26p DIFFIO_RX_T26n DIFFIO_RX_T27p DIFFIO_RX_T27n PLL_T1_CLKOUT3 PLL_T1_CLKOUT4 DIFFIO_RX_T28p DIFFIO_RX_T28n DIFFIO_RX_T29p DIFFIO_RX_T29n DIFFIO_RX_T30p Pin List Emulated LVDS Output Channel DIFFOUT_T34n DIFFOUT_T34p DIFFOUT_T35n DIFFOUT_T35p DIFFOUT_T36n DIFFOUT_T36p DIFFOUT_T37n DIFFOUT_T37p DIFFOUT_T38n DIFFOUT_T38p DIFFOUT_T39n DIFFOUT_T39p DIFFOUT_T40n DIFFOUT_T40p DIFFOUT_T41n DIFFOUT_T41p DIFFOUT_T42n DIFFOUT_T42p DIFFOUT_T43n DIFFOUT_T43p DIFFOUT_T44n DIFFOUT_T44p DIFFOUT_T45n DIFFOUT_T45p DIFFOUT_T46n DIFFOUT_T46p DIFFOUT_T47n DIFFOUT_T47p DIFFOUT_T48n DIFFOUT_T48p DIFFOUT_T49p DIFFOUT_T49n DIFFOUT_T50p DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T51n DIFFOUT_T52p DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T53n DIFFOUT_T54p DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T55n DIFFOUT_T56p DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T57n DIFFOUT_T58p DIFFOUT_T58n DIFFOUT_T59p F1517 D17 E17 C18 D18 F18 G18 G20 F20 F19 G19 R18 J18 A17 B17 H19 P18 A18 B19 M19 L19 C19 D19 N19 P19 C20 D20 A19 B20 A20 A21 B22 A22 B23 A23 G21 F21 M20 L20 D21 C22 N20 P20 A25 A24 M21 R20 D24 C24 N21 M22 J22 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1517 DQSn11T DQS11T DQ11T DQ11T DQSn12T DQS12T DQ12T DQ12T DQ12T DQ12T DQ13T DQ13T DQSn13T DQS13T DQ13T DQ13T DQ14T DQ14T DQS14T DQSn14T DQ14T DQ14T DQ15T DQS for X8/X9 for F1517 DQ11T DQ11T/CQn11T DQ11T DQ11T DQSn11T/DQ11T DQS11T/CQ11T DQ11T DQ11T DQ11T DQ11T DQS for X16/ X18 for F1517 DQ16T Page 12 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8B 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8BN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T30n DIFFIO_RX_T31p DIFFIO_RX_T31n DIFFIO_RX_T32p DIFFIO_RX_T32n DIFFIO_RX_T33p DIFFIO_RX_T33n DIFFIO_RX_T34p DIFFIO_RX_T34n DIFFIO_RX_T35p DIFFIO_RX_T35n DIFFIO_RX_T36p DIFFIO_RX_T36n DIFFIO_RX_T37p DIFFIO_RX_T37n DIFFIO_RX_T38p DIFFIO_RX_T38n DIFFIO_RX_T39p DIFFIO_RX_T39n DIFFIO_RX_T40p DIFFIO_RX_T40n DIFFIO_RX_T41p DIFFIO_RX_T41n DIFFIO_RX_T42p DIFFIO_RX_T42n Pin List Emulated LVDS Output Channel DIFFOUT_T59n DIFFOUT_T60p DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T61n DIFFOUT_T62p DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T63n DIFFOUT_T64p DIFFOUT_T64n DIFFOUT_T65p DIFFOUT_T65n DIFFOUT_T66p DIFFOUT_T66n DIFFOUT_T67p DIFFOUT_T67n DIFFOUT_T68p DIFFOUT_T68n DIFFOUT_T69p DIFFOUT_T69n DIFFOUT_T70p DIFFOUT_T70n DIFFOUT_T71p DIFFOUT_T71n DIFFOUT_T72p DIFFOUT_T72n DIFFOUT_T73p DIFFOUT_T73n DIFFOUT_T74p DIFFOUT_T74n DIFFOUT_T75p DIFFOUT_T75n DIFFOUT_T76p DIFFOUT_T76n DIFFOUT_T77p DIFFOUT_T77n DIFFOUT_T78p DIFFOUT_T78n DIFFOUT_T79p DIFFOUT_T79n DIFFOUT_T80p DIFFOUT_T80n DIFFOUT_T81p DIFFOUT_T81n DIFFOUT_T82p DIFFOUT_T82n DIFFOUT_T83p DIFFOUT_T83n DIFFOUT_T84p DIFFOUT_T84n F1517 H22 G22 K22 J23 H23 E22 D22 E23 D23 G23 F23 K24 J24 M24 J25 L23 K23 N22 M23 P23 N23 R22 P22 G24 F24 G25 D25 F25 E25 C25 B25 C26 B26 A26 D26 G26 F26 P24 R24 A28 A27 C27 D27 C28 B28 B31 A31 B29 A29 C29 C30 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1517 DQ15T DQ15T DQ15T DQS15T DQSn15T DQ16T DQ16T DQS16T DQSn16T DQ16T DQ16T DQ17T DQ17T DQ17T DQ17T DQS17T DQSn17T DQ18T DQ18T DQS18T DQSn18T DQ18T DQ18T DQ19T DQ19T DQ19T DQ19T DQS19T DQSn19T DQ20T DQ20T DQS20T DQSn20T DQ20T DQ20T DQS for X8/X9 for F1517 DQ16T DQ16T DQ16T DQS16T/CQ16T DQSn16T/DQ16T DQ16T DQ16T DQ16T/CQn16T DQ16T DQ16T DQ16T DQ19T DQ19T DQ19T DQ19T DQS19T/CQ19T DQSn19T/DQ19T DQ19T DQ19T DQ19T/CQn19T DQ19T DQ19T DQ19T DQ20T DQ20T DQ20T DQ20T DQS20T/CQ20T DQSn20T/DQ20T DQ20T DQ20T DQ20T/CQn20T DQ20T DQ20T DQ20T DQ21T DQ21T DQ21T DQ21T DQS21T DQSn21T DQ22T DQ22T DQS22T DQSn22T DQ22T DQ22T DQ24T DQ24T DQ24T DQ24T DQS24T/CQ24T DQSn24T/DQ24T DQ24T DQ24T DQ24T/CQn24T DQ24T DQ24T DQ24T DQS for X16/ X18 for F1517 DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQS20T/CQ20T DQSn20T/DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T/CQn20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T DQ20T Page 13 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL2 QL1 QL1 QL1 PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GXB_TX_L11p GXB_TX_L11n GXB_RX_L11p GXB_RX_L11n GXB_TX_L10p GXB_TX_L10n GXB_RX_L10p GXB_RX_L10n GXB_CMUTX_L5p GXB_CMUTX_L5n REFCLK_L5p,GXB_CMURX_L5p REFCLK_L5n,GXB_CMURX_L5n GXB_CMUTX_L4p GXB_CMUTX_L4n REFCLK_L4p,GXB_CMURX_L4p REFCLK_L4n,GXB_CMURX_L4n GXB_TX_L9p GXB_TX_L9n GXB_RX_L9p GXB_RX_L9n GXB_TX_L8p GXB_TX_L8n GXB_RX_L8p GXB_RX_L8n GXB_TX_L7p GXB_TX_L7n GXB_RX_L7p Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T43p DIFFIO_RX_T43n DIFFIO_RX_T44p DIFFIO_RX_T44n DIFFIO_RX_T45p DIFFIO_RX_T45n DIFFIO_RX_T46p DIFFIO_RX_T46n DIFFIO_RX_T47p DIFFIO_RX_T47n RUP8A RDN8A DIFFIO_RX_T48p DIFFIO_RX_T48n Pin List Emulated LVDS Output Channel DIFFOUT_T85p DIFFOUT_T85n DIFFOUT_T86p DIFFOUT_T86n DIFFOUT_T87p DIFFOUT_T87n DIFFOUT_T88p DIFFOUT_T88n DIFFOUT_T89p DIFFOUT_T89n DIFFOUT_T90p DIFFOUT_T90n DIFFOUT_T91p DIFFOUT_T91n DIFFOUT_T92p DIFFOUT_T92n DIFFOUT_T93p DIFFOUT_T93n DIFFOUT_T94p DIFFOUT_T94n DIFFOUT_T95p DIFFOUT_T95n DIFFOUT_T96p DIFFOUT_T96n F1517 F28 E28 D28 F27 E29 D29 G27 H26 H28 G28 J26 G29 L26 K26 L25 K28 K27 J27 M25 N25 P26 N26 P25 M27 B36 B37 C38 C39 D36 D37 E38 E39 F36 F37 G38 G39 H36 H37 J38 J39 K36 K37 L38 L39 M36 M37 N38 N39 P36 P37 R38 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQ23T DQ23T DQ23T DQ23T DQS23T DQSn23T DQ24T DQ24T DQS24T DQSn24T DQ24T DQ24T DQ25T DQ25T DQ25T DQ25T DQS25T DQSn25T DQ26T DQ26T DQS26T DQSn26T DQ26T DQ26T DQS for X8/X9 for F1517 DQ25T DQ25T DQ25T DQ25T DQS25T/CQ25T DQSn25T/DQ25T DQ25T DQ25T DQ25T/CQn25T DQ25T DQ25T DQ25T DQ26T DQ26T DQ26T DQ26T DQS26T/CQ26T DQSn26T/DQ26T DQ26T DQ26T DQ26T/CQn26T DQ26T DQ26T DQ26T DQS for X16/ X18 for F1517 DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQS26T/CQ26T DQSn26T/DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T/CQn26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T DQ26T Page 14 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QR0 QR0 QR0 QR0 QR0 QR0 PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function GXB_RX_L7n GXB_TX_L6p GXB_TX_L6n GXB_RX_L6p GXB_RX_L6n GXB_CMUTX_L3p GXB_CMUTX_L3n REFCLK_L3p,GXB_CMURX_L3p REFCLK_L3n,GXB_CMURX_L3n GXB_CMUTX_L2p GXB_CMUTX_L2n REFCLK_L2p,GXB_CMURX_L2p REFCLK_L2n,GXB_CMURX_L2n GXB_TX_L5p GXB_TX_L5n GXB_RX_L5p GXB_RX_L5n GXB_TX_L4p GXB_TX_L4n GXB_RX_L4p GXB_RX_L4n GXB_TX_L3p GXB_TX_L3n GXB_RX_L3p GXB_RX_L3n GXB_TX_L2p GXB_TX_L2n GXB_RX_L2p GXB_RX_L2n GXB_CMUTX_L1p GXB_CMUTX_L1n REFCLK_L1p,GXB_CMURX_L1p REFCLK_L1n,GXB_CMURX_L1n GXB_CMUTX_L0p GXB_CMUTX_L0n REFCLK_L0p,GXB_CMURX_L0p REFCLK_L0n,GXB_CMURX_L0n GXB_TX_L1p GXB_TX_L1n GXB_RX_L1p GXB_RX_L1n GXB_TX_L0p GXB_TX_L0n GXB_RX_L0p GXB_RX_L0n GXB_RX_R0n GXB_RX_R0p GXB_TX_R0n GXB_TX_R0p GXB_RX_R1n GXB_RX_R1p Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 R39 T36 T37 U38 U39 V36 V37 W38 W39 Y36 Y37 AA38 AA39 AB36 AB37 AC38 AC39 AD36 AD37 AE38 AE39 AF36 AF37 AG38 AG39 AH36 AH37 AJ38 AJ39 AK36 AK37 AL38 AL39 AM36 AM37 AN38 AN39 AP36 AP37 AR38 AR39 AT36 AT37 AU38 AU39 AU1 AU2 AT3 AT4 AR1 AR2 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 15 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function GXB_TX_R1n GXB_TX_R1p REFCLK_R0n,GXB_CMURX_R0n REFCLK_R0p,GXB_CMURX_R0p GXB_CMUTX_R0n GXB_CMUTX_R0p REFCLK_R1n,GXB_CMURX_R1n REFCLK_R1p,GXB_CMURX_R1p GXB_CMUTX_R1n GXB_CMUTX_R1p GXB_RX_R2n GXB_RX_R2p GXB_TX_R2n GXB_TX_R2p GXB_RX_R3n GXB_RX_R3p GXB_TX_R3n GXB_TX_R3p GXB_RX_R4n GXB_RX_R4p GXB_TX_R4n GXB_TX_R4p GXB_RX_R5n GXB_RX_R5p GXB_TX_R5n GXB_TX_R5p REFCLK_R2n,GXB_CMURX_R2n REFCLK_R2p,GXB_CMURX_R2p GXB_CMUTX_R2n GXB_CMUTX_R2p REFCLK_R3n,GXB_CMURX_R3n REFCLK_R3p,GXB_CMURX_R3p GXB_CMUTX_R3n GXB_CMUTX_R3p GXB_RX_R6n GXB_RX_R6p GXB_TX_R6n GXB_TX_R6p GXB_RX_R7n GXB_RX_R7p GXB_TX_R7n GXB_TX_R7p GXB_RX_R8n GXB_RX_R8p GXB_TX_R8n GXB_TX_R8p GXB_RX_R9n GXB_RX_R9p GXB_TX_R9n GXB_TX_R9p REFCLK_R4n,GXB_CMURX_R4n Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 AP3 AP4 AN1 AN2 AM3 AM4 AL1 AL2 AK3 AK4 AJ1 AJ2 AH3 AH4 AG1 AG2 AF3 AF4 AE1 AE2 AD3 AD4 AC1 AC2 AB3 AB4 AA1 AA2 Y3 Y4 W1 W2 V3 V4 U1 U2 T3 T4 R1 R2 P3 P4 N1 N2 M3 M4 L1 L2 K3 K4 J1 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 16 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 QR2 PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function REFCLK_R4p,GXB_CMURX_R4p GXB_CMUTX_R4n GXB_CMUTX_R4p REFCLK_R5n,GXB_CMURX_R5n REFCLK_R5p,GXB_CMURX_R5p GXB_CMUTX_R5n GXB_CMUTX_R5p GXB_RX_R10n GXB_RX_R10p GXB_TX_R10n GXB_TX_R10p GXB_RX_R11n GXB_RX_R11p GXB_TX_R11n GXB_TX_R11p GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 J2 H3 H4 G1 G2 F3 F4 E1 E2 D3 D4 C1 C2 B3 B4 AL11 Y21 B27 AV6 AV9 AV12 AV15 AV18 AV21 AV24 AV27 AV30 AV33 AR6 AR9 AR12 AR15 AR18 AR21 AR24 AR27 AR30 AR33 AM7 AM9 AM12 AM15 AM18 AM21 AM24 AM27 AM30 AM33 AJ7 AJ9 AJ12 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 17 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 AJ15 AJ18 AJ21 AJ24 AJ27 AJ30 AJ33 AF9 AF12 AF15 AF18 AF21 AF24 AF27 AF30 AD23 AC7 AC9 AC12 AC14 AC16 AC18 AC20 AC22 AC24 AC27 AC30 AC33 AB15 AB17 AB19 AB21 AB23 AB25 AA14 AA16 AA18 AA22 AA24 Y12 Y15 Y17 Y19 Y23 Y25 Y27 Y30 W10 W14 W16 W18 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 18 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 W20 W22 W24 V15 V17 V19 V21 V23 V25 U9 U12 U14 U16 U18 U20 U22 U24 U26 U28 U30 T15 T17 T19 T21 T23 T25 P7 P9 P12 P15 P21 P27 P30 P33 N18 N24 L6 L9 L12 L15 L18 L21 L24 L27 L30 L33 H6 H9 H12 H15 H18 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 19 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 H21 H24 H27 H30 H33 E6 E9 E12 E15 E18 E21 E24 E27 E30 E33 B9 B12 B15 B18 B21 B24 B30 A38 A37 A36 A35 A33 B39 B38 B35 B34 B33 C37 C36 D39 D38 E37 E36 F39 T34 AW37 AV37 AV38 AV39 AU36 AU37 AT38 AT39 AR36 AR37 AP38 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 20 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 AP39 AN36 AN37 AM38 AM39 AL36 AL37 AK38 AK39 AJ36 AJ37 AH38 AH39 AG36 AG37 AF33 AF38 AF39 AE36 AE37 AD32 AD34 AD38 AD39 AC36 AC37 AB33 AB38 AB39 AA36 AA37 Y32 Y34 Y38 Y39 W36 W37 V33 V38 V39 U36 U37 T32 T38 T39 R36 R37 P38 P39 N36 N37 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 21 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 M38 M39 L36 L37 K38 K39 J36 J37 H38 H39 G36 G37 F38 F35 G35 H35 J35 AR35 T31 R33 R32 AF34 AG34 AC31 AC32 AB31 AJ35 AH35 AK35 AG31 AG32 AL35 AN35 AD31 AM35 AE31 AP35 AA35 AB34 AC34 A7 A5 A4 A3 A2 B7 B6 B5 B2 B1 C4 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 22 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 C3 D2 D1 E4 E3 F2 T8 AW3 AV1 AV2 AV3 AU3 AU4 AT1 AT2 AR3 AR4 AP1 AP2 AN3 AN4 AM1 AM2 AL3 AL4 AK1 AK2 AJ3 AJ4 AH1 AH2 AG3 AG4 AF1 AF2 AF7 AE3 AE4 AD1 AD2 AD6 AD8 AC3 AC4 AB1 AB2 AB7 AA3 AA4 Y1 Y2 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 23 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 Y6 Y8 W3 W4 V1 V2 V7 U3 U4 T1 T2 T6 R3 R4 P1 P2 N3 N4 M1 M2 L3 L4 K1 K2 J3 J4 H1 H2 G3 G4 F1 AT5 AR5 AP5 AM5 AL5 AG9 AK5 AD9 AJ5 AG7 AG8 AC8 AB9 AH5 AG6 AF6 W6 W5 W8 W7 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 24 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 V6 U5 T9 R6 R5 V9 R7 N5 R9 R8 K5 J5 G5 F5 D5 C5 AN5 AC6 AB6 AA5 Y20 AC15 AC17 AC25 AB14 AB16 AB18 AB20 AB22 AB24 AA15 AA19 AA21 AA25 Y14 Y16 Y18 Y22 Y24 W15 W19 W21 W25 V14 V16 V18 V20 V22 V24 V26 U15 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 25 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPT VCCPT VCCPT VCCPT VCCPT VCCPT DNU VCCPGM VCCPGM TEMPDIODEn TEMPDIODEp VCC_CLKIN3C VCC_CLKIN4C VCC_CLKIN7C VCC_CLKIN8C VCCBAT VCCA_PLL_B1 VCCA_PLL_B2 VCCA_PLL_L2 VCCA_PLL_L3 Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 U19 U21 U25 T14 T16 T24 T26 T18 AC19 AC21 AC23 AA17 AA23 W17 W23 U17 U23 T20 T22 AF32 AE32 AB32 AA32 V32 U32 AB8 AF8 AE8 AA8 V8 U8 AA27 AA26 AM20 AA12 Y13 H20 AA20 AK28 AK12 E11 A9 AK21 AK18 K18 K21 K11 AL20 AL19 Y29 AA29 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 26 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function VCCA_PLL_R2 VCCA_PLL_R3 VCCA_PLL_T1 VCCA_PLL_T2 VCCD_PLL_B1 VCCD_PLL_B2 VCCD_PLL_L2 VCCD_PLL_L3 VCCD_PLL_R2 VCCD_PLL_R3 VCCD_PLL_T1 VCCD_PLL_T2 VCCIO1A VCCIO1A VCCIO1A VCCIO1A VCCIO1A VCCIO1C VCCIO1C VCCIO1C VCCIO1C VCCIO2A VCCIO2A VCCIO2A VCCIO2A VCCIO2A VCCIO2C VCCIO2C VCCIO2C VCCIO2C VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3B VCCIO3B VCCIO3C VCCIO3C VCCIO3C VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4B VCCIO4B VCCIO4C VCCIO4C VCCIO4C VCCIO5A VCCIO5A VCCIO5A Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 Y10 AA10 J20 J19 AK20 AK19 Y28 AA28 Y11 AA11 K20 K19 E35 J31 G32 G34 D32 K33 AA30 T29 N32 AJ28 AT35 AP31 AM32 AG26 AF31 AL33 AH31 AG33 AH25 AU30 AR29 AL26 AG23 AR26 AH21 AW24 AK22 AH15 AU13 AP12 AK15 AJ17 AW15 AJ19 AW17 AU21 AK10 AW9 AR7 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 27 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. VREF Pin Name/Function VCCIO5A VCCIO5A VCCIO5C VCCIO5C VCCIO5C VCCIO5C VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6A VCCIO6C VCCIO6C VCCIO6C VCCIO6C VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7B VCCIO7B VCCIO7C VCCIO7C VCCIO7C VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8B VCCIO8B VCCIO8C VCCIO8C VCCIO8C VCCPD1A VCCPD1C VCCPD2A VCCPD2C VCCPD3A VCCPD3B VCCPD3C VCCPD4A VCCPD4B VCCPD4C VCCPD5A VCCPD5C VCCPD6A VCCPD6C VCCPD7A VCCPD7B VCCPD7C VCCPD8A Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List Emulated LVDS Output Channel F1517 AR10 AN8 AE9 AL7 AJ8 AH7 B8 M9 H8 E5 E8 H5 V13 T11 P10 A12 M15 J14 D12 A15 L17 C21 M18 E19 A30 M26 J28 D30 E26 K25 C23 L22 F22 U27 W27 AB26 Y26 AD24 AD22 AD20 AD14 AD16 AD18 AC13 AA13 U13 W13 R15 R17 R19 R25 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 28 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number VREF 1A 1C 2A 2C 3A 3B 3C 4A 4B 4C 5A 5C 6A 6C 7A 7B 7C 8A 8B 8C VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 VREFB4AN0 VREFB4BN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0 VREFB7CN0 VREFB8AN0 VREFB8BN0 VREFB8CN0 PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. Pin Name/Function VCCPD8B VCCPD8C VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 VREFB4AN0 VREFB4BN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0 VREFB7CN0 VREFB8AN0 VREFB8BN0 VREFB8CN0 NC NC NC NC NC NC NC NC NC NC NC VCCAUX VCCAUX VCCAUX VCCAUX VCCA_L VCCA_L VCCA_L VCCA_L VCCA_R VCCA_R VCCA_R VCCA_R VCCH_GXBL0 VCCH_GXBL1 VCCH_GXBL2 VCCH_GXBR0 VCCH_GXBR1 VCCH_GXBR2 Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 VREFB4AN0 VREFB4BN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7BN0 VREFB7CN0 VREFB8AN0 VREFB8BN0 VREFB8CN0 Pin List Emulated LVDS Output Channel F1517 R23 R21 P28 U29 AF28 AB29 AN28 AL24 AP22 AN12 AM16 AL18 AG11 AD11 P11 U11 G12 H16 E20 F29 H25 J21 L28 AM28 AK11 F11 AV36 AU35 AU5 AV4 AD17 R16 R26 H29 AL28 AL12 G11 AF35 M35 K35 AG35 AF5 M5 AG5 L5 AE34 AA34 U34 AE6 AA6 U6 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Page 29 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Bank Number VREF Pin Name/Function VCCL_GXBL0 VCCL_GXBL0 VCCL_GXBL1 VCCL_GXBL1 VCCL_GXBL2 VCCL_GXBL2 VCCL_GXBR0 VCCL_GXBR0 VCCL_GXBR1 VCCL_GXBR1 VCCL_GXBR2 VCCL_GXBR2 VCCR_L VCCR_L VCCR_L VCCR_L VCCR_R VCCR_R VCCR_R VCCR_R VCCT_L VCCT_L VCCT_L VCCT_L VCCT_R VCCT_R VCCT_R VCCT_R VCCHIP_L VCCHIP_L VCCHIP_L VCCHIP_R VCCHIP_R VCCHIP_R RREF_L0 RREF_L1 RREF_R0 RREF_R1 Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1517 AD33 AE33 AA33 Y33 T33 U33 AE7 AD7 Y7 AA7 T7 U7 Y35 AD35 T35 AE35 Y5 AD5 T5 AE5 V35 AB35 P35 AC35 V5 AB5 P5 AC5 W31 AA31 Y31 Y9 AA9 W9 AW38 A34 AW2 A6 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1517 DQS for X8/X9 for F1517 DQS for X16/ X18 for F1517 Note: (1) If the p pin or n pin is not available, the particular differential pair is not supported. PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. Pin List Page 30 of 35 ® Pin Information for the Stratix IV GT EP4S40G2 Device Version 1.2 Notes (1), (2), (5) Pin Name Pin Type (1st and 2nd Function) Pin Description CLK[1,3,8,10]p CLK[1,3,8,10]n CLK[4:7,9, 11:15]p CLK[4:7,12:15]n PLL_[L4,R4]_CLKp PLL_[L4,R4]_CLKn PLL_[L1, L2, L4]_CLKOUT0n PLL_[R1, R2, R3, R4]_CLKOUT0n PLL_[L1, L2, L4]_FB_CLKOUT0p PLL_[R1, R2, R3, R4]_FB_CLKOUT0p PLL_[T1,T2,B1,B2]_FBp/CLKOUT1 PLL_[T1,T2,B1,B2]_FBn/CLKOUT2 PLL_[T1,T2,B1,B2]_CLKOUT[3,4] PLL_[T1,T2,B1,B2]_CLKOUT0p PLL_[T1,T2,B1,B2]_CLKOUT0n Clock, Input Clock, Input I/O, Clock I/O, Clock Clock, Input Clock, Input I/O, Clock nIO_PULLUP Input TEMPDIODEp TEMPDIODEn MSEL[0:2] nCE nCONFIG Input Input Input Input Input CONF_DONE Bidirectional (open-drain) nCEO nSTATUS Output Bidirectional (open-drain) PORSEL Input nCSO ASDO DCLK Output Output Input (PS, FPP) Output (AS) Input Input Input Output Input TCK TMS TDI TDO TRST CRC_ERROR I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock DEV_CLRn (Note 6) I/O, Output (open-drain) I/O, Input DEV_OE (Note 6) I/O, Input DATA0 (Note 6) DATA[1:7] (Note 6) I/O, Input I/O, Input PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. Clock and PLL Pins Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these pins. Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on these pins. These pins can be used as I/O pins or clock input pins. OCT Rd is not supported on these pins. These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is not supported on these pins. Dedicated clock input pins to PLL L4 and R4 respectively. Dedicated negative clock input pins for differential clock input to PLL L4 and R4 respectively. Each left and right PLL supports 2 clock I/O pins, configured either as 2 single ended I/O or one differential I/O pair. When using both pins as single ended I/Os, PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin. Dual purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin. These pins can be used as I/O pins or two single-ended clock output pins. I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. Dedicated Configuration/JTAG Pins Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins (DATA[0:7], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn) are on or off before and during configuration. A logic high turns off the weak pull-up, while a logic low turns them on. Pin used in conjunction with the temperature sensing diode (bias-high input) inside the FPGA. Pin used in conjunction with the temperature sensing diode (bias-low input) inside the FPGA. Configuration input pins that set the FPGA device configuration scheme. Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA to lose its configuration data, enter a reset state, and tristate all I/O pins. Returning this pin to a logic high level will initiate reconfiguration. This is a dedicated configuration done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. It is not available as a user I/O pin. Output that drives low when device configuration is complete. This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as a user I/O pin. Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high selects a POR time of 12 ms and a logic low selects POR time of 100 ms. Dedicated output control signal from the FPGA to the serial configuration device in AS mode that enables the configuration device. Control signal from the FPGA to the serial configuration device in AS mode used to read out configuration data. Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the FPGA. In AS mode, DCLK is an output from the FPGA that provides timing for the configuration interface. Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG output pin. Dedicated active low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit. Optional/Dual-Purpose Configuration Pins Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled. Optional pin that allows designers to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high (VCCPGM), all registers behave as programmed. Optional pin that allows designers to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high (VCCPGM), all I/O pins behave as defined in the design. Dual-purpose configuration data input pin. The DATA0 pin can be used for bit-wide configuration or as an I/O pin after configuration is complete. Dual-purpose configuration input data pins. The DATA[0:7] pins can be used for byte-wide configuration or as regular I/O pins. These pins can also be used as user I/O pins after configuration. Pin Definitions Page 31 of 35 ® Pin Information for the Stratix IV GT EP4S40G2 Device Version 1.2 Notes (1), (2), (5) Pin Name INIT_DONE CLKUSR (Note 6) DIFFIO_RX[##]p, DIFFIO_RX[##]n Pin Type (1st and 2nd Function) Pin Description I/O, Output This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin (open-drain) indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration. I/O, Input Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin. Differential I/O Pins I/O, RX channel These are true LVDS receiver channels on side and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DIFFIO_TX[##]p, DIFFIO_TX[##]n I/O, TX channel These are true LVDS transmitter channels on side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DIFFOUT_[##]p, DIFFOUT_[##]n I/O, TX channel These are emulated LVDS output channels. On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os, including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DQS[##][T,B], DQS[##][L,R] DQSn[##][T,B], DQSn[##][L,R] I/O,DQS DQ[##][T,B], DQ[##][L,R] I/O,DQ CQ[##][T,B], CQ[##][L,R] DQS Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list. Optional data strobe signal for use in QDR II SRAM. These are the pins for echo clocks. CQn[##][T,B], CQn[##][L,R] DQS Optional complementary data strobe signal for use in QDR II SRAM. These are the pins for echo clocks. RUP[1:8]A, (Note 7) RUP[3,8]C RDN[1:8]A, (Note 7) RDN[3,8]C DNU NC I/O, Input VCC VCCD_PLL_[L,R][1:4], VCCD_PLL_[T,B][1:2] VCCPT VCCA_PLL_[L,R][1:4], VCCA_PLL_[T,B][1:2] VCCAUX VCCIO[1:8][A,C], VCCIO[2,3,4,5,7,8]B Power Power VCCPGM VCCPD[1:8][A,C], VCCPD[2,3,4,5,7,8]B VCC_CLKIN[3,4,7,8]C VCCBAT Power Power Configuration pins power supply. Dedicated power pins. This supply is used to power the I/O pre-drivers. Power Power Differential clock input power supply for top and bottom I/O banks. Battery back-up power supply for design security volatile key register. PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. I/O,DQSn I/O, Input Do Not Use No Connect Power Power Power Power External Memory Interface Pins Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic. Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. Reference Pins Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin. Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin. Do not connect to power or ground or any other signal; must be left floating. Do not drive signals into these pins. Supply Pins VCC supplies power to the core and periphery. Digital power for PLL[L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in data sheet, even if the PLL is not used. Power supply for the programmable power technology. Analog power for PLL [L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in data sheet, even if the PLL is not used. It is advised to keep this pin isolated from other VCC for better jitter performance. Auxiliary supply for the programmable power technology. These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all LVDS, LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), HSTL(12, 15, 18), SSTL(15, 18, 2), 3.0 V PCI/PCI-X I/O as well as LVTTL 3.3 V I/O standards. VCCIO also supplies power to the input buffers used for LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), 3.0 V PCI/PCI-X and LVTTL 3.3 V I/O standards. Pin Definitions Page 32 of 35 ® Pin Information for the Stratix IV GT EP4S40G2 Device Version 1.2 Notes (1), (2), (5) Pin Name GND VREF[1:8][A,C]N0, VREF[2,3,4,5,7,8]BN0 VCCHIP_[L,R] VCCR_[L,R] VCCT_[L,R] VCCL_GXB[L,R][0:3] VCCH_GXB[L,R][0:3] VCCA_[L,R] GXB_RX_[L,R][0:15]p (Note 3) GXB_RX_[L,R][0:15]n (Note 3) GXB_TX_[L,R][0:15]p (Note 3) GXB_TX_[L,R][0:15]n (Note 3) REFCLK_[L,R][0:7]p, GXB_CMURX_[L,R][0:7]p (Note 3 and 4) REFCLK_[L,R][0:7]n, GXB_CMURX_[L,R][0:7]n (Note 3 and 4) GXB_CMUTX_[L,R][0:7]p, (Note 4) GXB_CMUTX_[L,R][0:7]n RREF_[L,R][0:1] Pin Type (1st and 2nd Function) Pin Description Device ground pins. Ground Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for Power the bank. Transceiver (I/O Banks) Pins Power PCIe Hard IP digital power supply, specific to the left (L) side or right (R) side of the device. Power Analog power, receiver, specific to the left (L) side or right (R) side of the device. Power Analog power, transmitter, specific to the left (L) side or right (R) side of the device. Power Analog power, block level clock distribution. Power Analog power, block level TX buffers, specific to left (L) side and right (R) side. Power Analog power, TX driver, RX receiver, CDR, specific to the left (L) side or right (R) side of the device. Input High speed positive differential receiver channels. Specific to the left (L) side or right (R) side of the device. Input High speed negative differential receiver channels. Specific to the left (L) side or right (R) side of the device. Output High speed positive differential transmitter channels. Specific to the left (L) side or right (R) side of the device. Output High speed negative differential transmitter channels. Specific to the left (L) side or right (R) side of the device. Input High speed differential reference clock positive, or CMU receiver channels, specific to the left (L) side or right (R) side of the device. Input High speed differential reference clock complement, or CMU complementary receiver channel, specific to the left (L) side or right (R) side of the device. Output CMU transmitter channels, specific to the left (L) side or right (R) side of the device. Input Reference resistor for transceiver, specific to the left (L) side or right (R) side of the device. Notes: 1. This pin definition is prepared based on the EP4S100G5. 2. Some of the pull-up /pull-down resisitors mentioned in the table above may not be required, depending on the exact device configuration scheme. The ability to NC or short them may be valuable during the debug phase, should you be required to use a different configuration scheme. Refer to the Configuring Stratix IV GX Devices chapter in the Stratix IV GX Device Handbook for more information. 3. Transceiver signals GXB_RX[15..0] and GXB_TX[15..0] are device specific. 4. Dual purpose CMU Receiver channels. Can be used either as reference clock or CMU receiver channels in devices with 5th and 6th channels. 5. Refer to pin connections guidelines and data sheet for the recommended operating voltage. 6. Although some configuration pins may indicate that they serve as dual purpose (I/O and configuration) pins, this functionality is device dependent. Refer to the pin list to determine if the regular I/O function is available for the specific dual-purpose configuration pin. 7. The regular I/O function is not available for some of these reference pins. The availability of the regular I/O function on these reference pins is device dependent. Refer to the pin list to determine if the regular I/O function is available for the specific reference pin. PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. Pin Definitions Page 33 of 35 7A VREFB7CN0 VREFB7BN0 VREFB7AN0 VREFB3AN0 VREFB3BN0 VREFB3CN0 PLL_B1 PLL_B2 4C 4B 4A VREFB4CN0 VREFB4BN0 VREFB4AN0 VREFB5CN0 3C VREFB5AN0 3B 5C 3A 5A 2C PLL_R3 2A PLL_L3 VREFB2CN0 PLL_R2 Transceiver Block (QR2) 7B Transceiver Block (QR1) VREFB8CN0 7C Transceiver Block (QR0) VREFB8BN0 PLL_T2 VREFB6AN0 VREFB8AN0 PLL_T1 VREFB6CN0 8C 6A 1A 1C 8B 6C VREFB1AN0 VREFB1CN0 8A PLL_L2 VREFB2AN0 Transceiver Block (QL0) Transceiver Block (QL1) Transceiver Block (QL2) Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Note (1) Note: 1. This is only a pictorial representation to provide an idea of placement on the device. Refer to the pin list and the Quartus® II software for exact locations. PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. Bank & PLL Diagram Page 34 of 35 Pin Information for the Stratix® IV GT EP4S40G2 Device Version 1.2 Version Number 1.0 Date 9/18/2009 1.1 12/3/2009 1.2 2/4/2015 PT-EP4S40G2-1.2 Copyright © 2015 Altera Corp. Changes Made Initial release. Added bank number for JTAG pins. Added Note (6) and Note (7) in Pin Definitions. Grouped nCSO, ASDO, and DCLK into dedicated configuration/JTAG pins in Pin Definitions. Added the Dynamic OCT Support column in the Pin List. Revision History Page 35 of 35