Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C VREF VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 Pin Name/Function TDI TMS TRST TCK TDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function TDI TMS TRST TCK TDO RDN1A RUP1A CLKUSR DATA0 DATA1 DATA2 DATA3 DATA4 Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_TX_L1n DIFFIO_TX_L1p DIFFIO_RX_L1n DIFFIO_RX_L1p DIFFIO_TX_L2n DIFFIO_TX_L2p DIFFIO_RX_L2n DIFFIO_RX_L2p DIFFIO_TX_L3n DIFFIO_TX_L3p DIFFIO_RX_L3n DIFFIO_RX_L3p DIFFIO_TX_L4n DIFFIO_TX_L4p DIFFIO_RX_L4n DIFFIO_RX_L4p DIFFIO_TX_L5n DIFFIO_TX_L5p DIFFIO_RX_L5n DIFFIO_RX_L5p DIFFIO_TX_L6n DIFFIO_TX_L6p DIFFIO_RX_L6n DIFFIO_RX_L6p DIFFIO_TX_L7n DIFFIO_TX_L7p DIFFIO_RX_L7n DIFFIO_RX_L7p DIFFIO_TX_L8n DIFFIO_TX_L8p DIFFIO_RX_L8n DIFFIO_RX_L8p DIFFIO_TX_L9n DIFFIO_TX_L9p DIFFIO_RX_L9n DIFFIO_RX_L9p DIFFIO_TX_L10n DIFFIO_TX_L10p DIFFIO_RX_L10n DIFFIO_RX_L10p DIFFIO_TX_L11n DIFFIO_TX_L11p DIFFIO_RX_L11n DIFFIO_RX_L11p DIFFIO_TX_L12n DIFFOUT_L1n DIFFOUT_L1p DIFFOUT_L2n DIFFOUT_L2p DIFFOUT_L3n DIFFOUT_L3p DIFFOUT_L4n DIFFOUT_L4p DIFFOUT_L5n DIFFOUT_L5p DIFFOUT_L6n DIFFOUT_L6p DIFFOUT_L7n DIFFOUT_L7p DIFFOUT_L8n DIFFOUT_L8p DIFFOUT_L9n DIFFOUT_L9p DIFFOUT_L10n DIFFOUT_L10p DIFFOUT_L11n DIFFOUT_L11p DIFFOUT_L12n DIFFOUT_L12p DIFFOUT_L13n DIFFOUT_L13p DIFFOUT_L14n DIFFOUT_L14p DIFFOUT_L15n DIFFOUT_L15p DIFFOUT_L16n DIFFOUT_L16p DIFFOUT_L17n DIFFOUT_L17p DIFFOUT_L18n DIFFOUT_L18p DIFFOUT_L19n DIFFOUT_L19p DIFFOUT_L20n DIFFOUT_L20p DIFFOUT_L21n DIFFOUT_L21p DIFFOUT_L22n DIFFOUT_L22p DIFFOUT_L23n Pin List F780 F780 J20 G23 D26 D25 E25 H23 H22 D28 D27 G25 G24 B28 C28 F26 F25 E28 E27 H25 H24 G27 G26 K24 K23 F28 G28 K22 K21 J26 J25 L21 L20 H28 H27 L23 L22 K26 K25 L24 M23 L26 L25 N21 N20 J28 K28 N23 N22 L28 K27 P21 Dynamic OCT Support No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X8/X9 for DQS for X4 for F780 F780 DQS for X16/X18 for F780 DQ1L DQ1L DQSn1L DQS1L DQ1L DQ1L DQSn2L DQS2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQSn3L DQS3L DQ3L DQ3L DQSn4L DQS4L DQ4L DQ4L DQ4L DQ4L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ2L DQ2L/CQn2L DQ2L DQ2L DQSn2L/DQ2L DQS2L/CQ2L DQ2L DQ2L DQ2L DQ2L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn5L DQS5L DQ5L DQ5L DQ5L DQ5L DQ6L DQ6L DQSn6L DQS6L DQ6L DQ5L DQ5L DQ5L DQ5L/CQn5L DQ5L Page 1 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A VREF VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO CLK1n CLK1p CLK3p CLK3n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) PLL_L2_CLKOUT0n PLL_L2_FB_CLKOUT0p CLK0n CLK0p CLK1n CLK1p CLK3p CLK3n CLK2p CLK2n Configuration Function DATA5 DATA6 DATA7 INIT_DONE CRC_ERROR DEV_OE DEV_CLRn Dedicated Tx/Rx Channel DIFFIO_TX_L12p DIFFIO_RX_L12n DIFFIO_RX_L12p DIFFIO_TX_L13n DIFFIO_TX_L13p DIFFIO_RX_L13n DIFFIO_RX_L13p DIFFIO_TX_L14n DIFFIO_TX_L14p DIFFIO_RX_L14n DIFFIO_RX_L14p Emulated LVDS Output Channel DIFFOUT_L23p DIFFOUT_L24n DIFFOUT_L24p DIFFOUT_L25n DIFFOUT_L25p DIFFOUT_L26n DIFFOUT_L26p DIFFOUT_L27n DIFFOUT_L27p DIFFOUT_L28n DIFFOUT_L28p DIFFIO_RX_L15p DIFFIO_RX_L15n DIFFIO_TX_L15p DIFFIO_TX_L15n DIFFIO_RX_L16p DIFFIO_RX_L16n DIFFIO_TX_L16p DIFFIO_TX_L16n DIFFIO_RX_L17p DIFFIO_RX_L17n DIFFIO_TX_L17p DIFFIO_TX_L17n DIFFIO_RX_L18p DIFFIO_RX_L18n DIFFIO_TX_L18p DIFFIO_TX_L18n DIFFIO_RX_L19p DIFFIO_RX_L19n DIFFIO_TX_L19p DIFFIO_TX_L19n DIFFIO_RX_L20p DIFFIO_RX_L20n DIFFIO_TX_L20p DIFFIO_TX_L20n DIFFIO_RX_L21p DIFFIO_RX_L21n DIFFIO_TX_L21p DIFFIO_TX_L21n DIFFIO_RX_L22p DIFFIO_RX_L22n DIFFIO_TX_L22p DIFFIO_TX_L22n DIFFIO_RX_L23p DIFFIO_RX_L23n DIFFIO_TX_L23p DIFFOUT_L29p DIFFOUT_L29n DIFFOUT_L30p DIFFOUT_L30n DIFFOUT_L31p DIFFOUT_L31n DIFFOUT_L32p DIFFOUT_L32n DIFFOUT_L33p DIFFOUT_L33n DIFFOUT_L34p DIFFOUT_L34n DIFFOUT_L35p DIFFOUT_L35n DIFFOUT_L36p DIFFOUT_L36n DIFFOUT_L37p DIFFOUT_L37n DIFFOUT_L38p DIFFOUT_L38n DIFFOUT_L39p DIFFOUT_L39n DIFFOUT_L40p DIFFOUT_L40n DIFFOUT_L41p DIFFOUT_L41n DIFFOUT_L42p DIFFOUT_L42n DIFFOUT_L43p DIFFOUT_L43n DIFFOUT_L44p DIFFOUT_L44n DIFFOUT_L45p DIFFOUT_L45n DIFFOUT_L46p Pin List F780 F780 P20 M26 M25 N25 N24 M28 L27 P26 P25 N28 N27 P28 P27 T28 R28 T27 U28 R25 R26 T25 U26 R20 T21 U27 V28 T22 T23 U25 V26 T20 U21 W27 W28 U23 U24 V25 W26 V22 V23 Y27 Y28 W24 W25 AB28 AA28 W22 W23 AB27 AC28 V20 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X8/X9 for DQS for X4 for F780 F780 DQ6L DQ5L DQSn7L DQSn5L/DQ5L DQS7L DQS5L/CQ5L DQ7L DQ5L DQ7L DQ5L DQ7L DQ5L DQ7L DQ5L DQ8L DQ8L DQ8L DQ8L DQS8L DQSn8L DQ9L DQ9L DQS9L DQSn9L DQ9L DQ9L DQ10L DQ10L DQ10L DQ10L DQS10L DQSn10L DQ10L DQ10L DQ10L DQ10L DQS10L/CQ10L DQSn10L/DQ10L DQ10L DQ10L DQ10L/CQn10L DQ10L DQ10L DQ10L DQ11L DQ11L DQ11L DQ11L DQS11L DQSn11L DQ12L DQ13L DQ13L DQ13L DQ13L DQS13L/CQ13L DQSn13L/DQ13L DQ13L DQS for X16/X18 for F780 DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L Page 2 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A VREF VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO nCONFIG nSTATUS CONF_DONE PORSEL nCE IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function RUP2A RDN2A Dedicated Tx/Rx Channel DIFFIO_TX_L23n DIFFIO_RX_L24p DIFFIO_RX_L24n DIFFIO_TX_L24p DIFFIO_TX_L24n DIFFIO_RX_L25p DIFFIO_RX_L25n DIFFIO_TX_L25p DIFFIO_TX_L25n DIFFIO_RX_L26p DIFFIO_RX_L26n DIFFIO_TX_L26p DIFFIO_TX_L26n DIFFIO_RX_L27p DIFFIO_RX_L27n DIFFIO_TX_L27p DIFFIO_TX_L27n DIFFIO_RX_L28p DIFFIO_RX_L28n DIFFIO_TX_L28p DIFFIO_TX_L28n Emulated LVDS Output Channel DIFFOUT_L46n DIFFOUT_L47p DIFFOUT_L47n DIFFOUT_L48p DIFFOUT_L48n DIFFOUT_L49p DIFFOUT_L49n DIFFOUT_L50p DIFFOUT_L50n DIFFOUT_L51p DIFFOUT_L51n DIFFOUT_L52p DIFFOUT_L52n DIFFOUT_L53p DIFFOUT_L53n DIFFOUT_L54p DIFFOUT_L54n DIFFOUT_L55p DIFFOUT_L55n DIFFOUT_L56p DIFFOUT_L56n nCONFIG nSTATUS CONF_DONE nCE RDN3A RUP3A DIFFIO_RX_B1n DIFFIO_RX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_RX_B3n DIFFIO_RX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_RX_B5n DIFFIO_RX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p Pin List F780 DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p F780 W21 AC27 AD28 Y25 Y26 AA25 AA26 AB25 AC26 AE27 AE28 Y23 Y24 AF27 AF28 AB23 AB24 AH27 AG28 AC25 AD26 AA22 AC23 AC24 W20 Y21 AB21 AC21 AD22 AC22 AA20 AB20 AE23 AD23 AE24 AE25 AG23 AF24 AF25 AF26 AH25 AG25 AG26 AH26 AH24 AH23 AG22 AH22 AF22 AE22 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X8/X9 for DQS for X4 for F780 F780 DQ12L DQ13L DQS12L DQ13L/CQn13L DQSn12L DQ13L DQ12L DQ13L DQ12L DQ13L DQ13L DQ14L DQ13L DQ14L DQ13L DQ14L DQ13L DQ14L DQS13L DQS14L/CQ14L DQSn13L DQSn14L/DQ14L DQ14L DQ14L DQ14L DQ14L DQS14L DQ14L/CQn14L DQSn14L DQ14L DQ14L DQ14L DQ14L DQ14L DQS for X16/X18 for F780 DQ14L DQS14L/CQ14L DQSn14L/DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L/CQn14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ1B DQ1B DQSn1B DQS1B DQ1B DQ1B DQSn2B DQS2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQSn3B DQS3B DQ3B DQ3B DQSn4B DQS4B DQ4B DQ4B DQ4B DQ4B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B Page 3 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C VREF VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_RX_B8n DIFFIO_RX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_RX_B10n DIFFIO_RX_B10p DIFFIO_RX_B11n DIFFIO_RX_B11p DIFFIO_RX_B12n DIFFIO_RX_B12p DIFFIO_RX_B13n DIFFIO_RX_B13p PLL_B1_CLKOUT4 PLL_B1_CLKOUT3 DIFFIO_RX_B14n DIFFIO_RX_B14p PLL_B1_CLKOUT0n PLL_B1_CLKOUT0p PLL_B1_FBn/CLKOUT2 PLL_B1_FBp/CLKOUT1 CLK5n CLK5p CLK4n CLK4p CLK6p CLK6n CLK7p CLK7n DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_RX_B16n DIFFIO_RX_B16p DIFFIO_RX_B17p DIFFIO_RX_B17n DIFFIO_RX_B18p DIFFIO_RX_B18n DIFFIO_RX_B19p DIFFIO_RX_B19n Pin List F780 Emulated LVDS Output Channel DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B21p DIFFOUT_B22n DIFFOUT_B22p DIFFOUT_B23n DIFFOUT_B23p DIFFOUT_B24n DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B25p DIFFOUT_B26n DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B27p DIFFOUT_B28n DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B29p DIFFOUT_B30n DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B31p DIFFOUT_B32n DIFFOUT_B32p DIFFOUT_B33p DIFFOUT_B33n DIFFOUT_B34p DIFFOUT_B34n DIFFOUT_B35p DIFFOUT_B35n DIFFOUT_B36p DIFFOUT_B36n DIFFOUT_B37p DIFFOUT_B37n F780 AH20 AH21 AF21 AE21 AG19 AG20 AF19 AE20 AD19 AC19 AE19 AD20 AA19 AB18 Y18 Y17 AA17 AA16 AC18 AB17 Y15 Y16 AH19 AH18 AE17 AG17 AF18 AE18 AD17 AD16 AF16 AE16 AC16 AB15 AF15 AE15 AH17 AG16 AH16 AH15 AG14 AH14 AH12 AH13 AF14 AG13 Y13 Y14 AA13 AA14 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes DQS for X8/X9 for DQS for X4 for F780 F780 DQ5B DQ3B DQ5B DQ3B DQSn5B DQ3B DQS5B DQ3B/CQn3B DQ5B DQ3B DQ5B DQ3B DQSn6B DQSn3B/DQ3B DQS6B DQS3B/CQ3B DQ6B DQ3B DQ6B DQ3B DQ6B DQ3B DQ6B DQ3B DQ7B DQ7B DQSn7B DQS7B DQ7B DQ7B DQSn8B DQS8B DQ8B DQ8B DQ8B DQ8B DQS for X16/X18 for F780 DQ7B DQ7B DQ7B DQ7B/CQn7B DQ7B DQ7B DQSn7B/DQ7B DQS7B/CQ7B DQ7B DQ7B DQ7B DQ7B DQ9B DQ9B DQS9B DQSn9B Page 4 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A VREF VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B20p DIFFIO_RX_B20n DIFFIO_RX_B21p DIFFIO_RX_B21n DIFFIO_RX_B22p DIFFIO_RX_B22n DIFFIO_RX_B23p DIFFIO_RX_B23n DIFFIO_RX_B24p DIFFIO_RX_B24n DIFFIO_RX_B25p DIFFIO_RX_B25n DIFFIO_RX_B26p DIFFIO_RX_B26n DIFFIO_RX_B27p DIFFIO_RX_B27n DIFFIO_RX_B28p DIFFIO_RX_B28n DIFFIO_RX_B29p DIFFIO_RX_B29n DIFFIO_RX_B30p DIFFIO_RX_B30n DIFFIO_RX_B31p DIFFIO_RX_B31n Pin List F780 Emulated LVDS Output Channel DIFFOUT_B38p DIFFOUT_B38n DIFFOUT_B39p DIFFOUT_B39n DIFFOUT_B40p DIFFOUT_B40n DIFFOUT_B41p DIFFOUT_B41n DIFFOUT_B42p DIFFOUT_B42n DIFFOUT_B43p DIFFOUT_B43n DIFFOUT_B44p DIFFOUT_B44n DIFFOUT_B45p DIFFOUT_B45n DIFFOUT_B46p DIFFOUT_B46n DIFFOUT_B47p DIFFOUT_B47n DIFFOUT_B48p DIFFOUT_B48n DIFFOUT_B49p DIFFOUT_B49n DIFFOUT_B50p DIFFOUT_B50n DIFFOUT_B51p DIFFOUT_B51n DIFFOUT_B52p DIFFOUT_B52n DIFFOUT_B53p DIFFOUT_B53n DIFFOUT_B54p DIFFOUT_B54n DIFFOUT_B55p DIFFOUT_B55n DIFFOUT_B56p DIFFOUT_B56n DIFFOUT_B57p DIFFOUT_B57n DIFFOUT_B58p DIFFOUT_B58n DIFFOUT_B59p DIFFOUT_B59n DIFFOUT_B60p DIFFOUT_B60n DIFFOUT_B61p DIFFOUT_B61n DIFFOUT_B62p DIFFOUT_B62n F780 AB12 AB11 AD13 AE12 AE13 AE14 AC12 AD11 AF12 AH11 AE11 AF11 AH10 AG11 Y12 AA11 Y10 Y11 AC10 AD10 AB9 AB10 AE9 AE10 AF10 AF9 AG8 AH8 AH9 AG10 AG7 AH6 AH5 AH7 AF6 AG5 AE7 AE8 AE6 AF7 AD7 AD8 AG4 AH4 AF3 AF4 AH2 AH3 AC6 AC8 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X8/X9 for DQS for X4 for F780 F780 DQ9B DQ9B DQ10B DQ11B DQ10B DQ11B DQ10B DQ11B DQ10B DQ11B DQS10B DQS11B/CQ11B DQSn10B DQSn11B/DQ11B DQ11B DQ11B DQ11B DQ11B DQS11B DQ11B/CQn11B DQSn11B DQ11B DQ11B DQ11B DQ11B DQ11B DQ12B DQ12B DQ12B DQ12B DQS12B DQSn12B DQ13B DQ13B DQS13B DQSn13B DQ13B DQ13B DQ14B DQ14B DQ14B DQ14B DQS14B DQSn14B DQ15B DQ15B DQS15B DQSn15B DQ15B DQ15B DQ16B DQ16B DQ16B DQ16B DQS16B DQSn16B DQ17B DQ17B DQ15B DQ15B DQ15B DQ15B DQS15B/CQ15B DQSn15B/DQ15B DQ15B DQ15B DQ15B/CQn15B DQ15B DQ15B DQ15B DQ16B DQ16B DQ16B DQ16B DQS16B/CQ16B DQSn16B/DQ16B DQ16B DQ16B DQ16B/CQn16B DQ16B DQ16B DQ16B DQ17B DQ17B DQ17B DQ17B DQS17B/CQ17B DQSn17B/DQ17B DQ17B DQ17B DQS for X16/X18 for F780 DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQS17B/CQ17B DQSn17B/DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B/CQn17B DQ17B DQ17B DQ17B Page 5 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 4A 4A 4A 4A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A VREF VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 Pin Name/Function IO IO IO IO nIO_PULLUP nCEO DCLK nCSO ASDO MSEL2 MSEL1 MSEL0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) RUP4A RDN4A Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B32p DIFFIO_RX_B32n Emulated LVDS Output Channel DIFFOUT_B63p DIFFOUT_B63n DIFFOUT_B64p DIFFOUT_B64n nIO_PULLUP nCEO DCLK nCSO ASDO MSEL2 MSEL1 MSEL0 RDN7A RUP7A DIFFIO_RX_T1n DIFFIO_RX_T1p DIFFIO_RX_T2n DIFFIO_RX_T2p DIFFIO_RX_T3n DIFFIO_RX_T3p DIFFIO_RX_T4n DIFFIO_RX_T4p DIFFIO_RX_T5n DIFFIO_RX_T5p DIFFIO_RX_T6n DIFFIO_RX_T6p DIFFIO_RX_T7n DIFFIO_RX_T7p DIFFIO_RX_T8n DIFFIO_RX_T8p DIFFIO_RX_T9n DIFFIO_RX_T9p Pin List F780 DIFFOUT_T1n DIFFOUT_T1p DIFFOUT_T2n DIFFOUT_T2p DIFFOUT_T3n DIFFOUT_T3p DIFFOUT_T4n DIFFOUT_T4p DIFFOUT_T5n DIFFOUT_T5p DIFFOUT_T6n DIFFOUT_T6p DIFFOUT_T7n DIFFOUT_T7p DIFFOUT_T8n DIFFOUT_T8p DIFFOUT_T9n DIFFOUT_T9p DIFFOUT_T10n DIFFOUT_T10p DIFFOUT_T11n DIFFOUT_T11p DIFFOUT_T12n DIFFOUT_T12p DIFFOUT_T13n DIFFOUT_T13p DIFFOUT_T14n DIFFOUT_T14p DIFFOUT_T15n DIFFOUT_T15p DIFFOUT_T16n DIFFOUT_T16p DIFFOUT_T17n DIFFOUT_T17p DIFFOUT_T18n DIFFOUT_T18p DIFFOUT_T19n DIFFOUT_T19p F780 AA8 AB7 Y9 AA10 Y8 W6 Y6 W7 Y7 J7 J9 K9 F7 G8 E7 F8 G9 H9 D6 E6 D5 F6 C4 C5 A2 B3 A3 B4 A5 A4 A6 B6 C7 D7 A7 B7 B9 A8 C8 D8 B10 A9 D10 E9 F10 E10 C10 D9 H10 G11 Dynamic OCT Support Yes Yes Yes Yes No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X8/X9 for DQS for X4 for F780 F780 DQS17B DQ17B/CQn17B DQSn17B DQ17B DQ17B DQ17B DQ17B DQ17B DQS for X16/X18 for F780 DQ17B DQ17B DQ17B DQ17B DQ1T DQ1T DQSn1T DQS1T DQ1T DQ1T DQSn2T DQS2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQSn3T DQS3T DQ3T DQ3T DQSn4T DQS4T DQ4T DQ4T DQ4T DQ4T DQ5T DQ5T DQSn5T DQS5T DQ5T DQ5T DQSn6T DQS6T DQ6T DQ6T DQ6T DQ6T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ2T/CQn2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQ3T DQ3T/CQn3T DQ3T DQ3T DQSn3T/DQ3T DQS3T/CQ3T DQ3T DQ3T DQ3T DQ3T Page 6 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 7A 7A 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C VREF VREFB7AN0 VREFB7AN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T10n DIFFIO_RX_T10p DIFFIO_RX_T11n DIFFIO_RX_T11p DIFFIO_RX_T12n DIFFIO_RX_T12p DIFFIO_RX_T13n DIFFIO_RX_T13p DIFFIO_RX_T14n DIFFIO_RX_T14p DIFFIO_RX_T15n DIFFIO_RX_T15p CLK13n CLK13p CLK12n CLK12p CLK14p CLK14n CLK15p CLK15n PLL_T1_FBp/CLKOUT1 PLL_T1_FBn/CLKOUT2 PLL_T1_CLKOUT0p PLL_T1_CLKOUT0n DIFFIO_RX_T16n DIFFIO_RX_T16p DIFFIO_RX_T17p DIFFIO_RX_T17n DIFFIO_RX_T18p DIFFIO_RX_T18n DIFFIO_RX_T19p DIFFIO_RX_T19n PLL_T1_CLKOUT3 PLL_T1_CLKOUT4 DIFFIO_RX_T20p DIFFIO_RX_T20n DIFFIO_RX_T21p DIFFIO_RX_T21n DIFFIO_RX_T22p DIFFIO_RX_T22n Pin List F780 Emulated LVDS Output Channel DIFFOUT_T20n DIFFOUT_T20p DIFFOUT_T21n DIFFOUT_T21p DIFFOUT_T22n DIFFOUT_T22p DIFFOUT_T23n DIFFOUT_T23p DIFFOUT_T24n DIFFOUT_T24p DIFFOUT_T25n DIFFOUT_T25p DIFFOUT_T26n DIFFOUT_T26p DIFFOUT_T27n DIFFOUT_T27p DIFFOUT_T28n DIFFOUT_T28p DIFFOUT_T29n DIFFOUT_T29p DIFFOUT_T30n DIFFOUT_T30p DIFFOUT_T31n DIFFOUT_T31p DIFFOUT_T32n DIFFOUT_T32p DIFFOUT_T33p DIFFOUT_T33n DIFFOUT_T34p DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T35n DIFFOUT_T36p DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T37n DIFFOUT_T38p DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T39n DIFFOUT_T40p DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T41n DIFFOUT_T42p DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T43n DIFFOUT_T44p DIFFOUT_T44n F780 J11 J12 A11 A10 C11 D11 B12 D12 E12 F11 F13 E13 C13 D13 H12 G12 G14 H13 J14 J13 C14 D14 A14 B13 A12 A13 B15 A15 B16 A16 D15 C15 J15 H15 E16 D16 J16 H16 A19 A18 A17 B18 C18 C17 G17 D17 F17 E18 D18 F18 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X8/X9 for DQS for X4 for F780 F780 DQ7T DQ7T DQSn7T DQS7T DQ7T DQ7T DQSn8T DQS8T DQ8T DQ8T DQ8T DQ8T DQ9T DQ9T DQSn9T DQS9T DQ9T DQ9T DQ7T DQ7T DQ7T DQ7T/CQn7T DQ7T DQ7T DQSn7T/DQ7T DQS7T/CQ7T DQ7T DQ7T DQ7T DQ7T DQ10T DQ10T DQ10T DQ10T DQS10T DQSn10T DQ11T DQ11T DQS11T DQSn11T DQ11T DQ11T DQ11T DQ11T DQ11T DQ11T DQS11T/CQ11T DQSn11T/DQ11T DQ11T DQ11T DQ11T/CQn11T DQ11T DQ11T DQ11T DQS for X16/X18 for F780 Page 7 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 VREF VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GXB_RX_R0p GXB_RX_R0n GXB_TX_R0p GXB_TX_R0n GXB_RX_R1p GXB_RX_R1n GXB_TX_R1p GXB_TX_R1n REFCLK_R0p,GXB_CMURX_R0p REFCLK_R0n,GXB_CMURX_R0n PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T23p DIFFIO_RX_T23n DIFFIO_RX_T24p DIFFIO_RX_T24n DIFFIO_RX_T25p DIFFIO_RX_T25n DIFFIO_RX_T26p DIFFIO_RX_T26n DIFFIO_RX_T27p DIFFIO_RX_T27n DIFFIO_RX_T28p DIFFIO_RX_T28n DIFFIO_RX_T29p DIFFIO_RX_T29n DIFFIO_RX_T30p DIFFIO_RX_T30n DIFFIO_RX_T31p DIFFIO_RX_T31n RUP8A RDN8A DIFFIO_RX_T32p DIFFIO_RX_T32n Pin List F780 Emulated LVDS Output Channel DIFFOUT_T45p DIFFOUT_T45n DIFFOUT_T46p DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T47n DIFFOUT_T48p DIFFOUT_T48n DIFFOUT_T49p DIFFOUT_T49n DIFFOUT_T50p DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T51n DIFFOUT_T52p DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T53n DIFFOUT_T54p DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T55n DIFFOUT_T56p DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T57n DIFFOUT_T58p DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T59n DIFFOUT_T60p DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T61n DIFFOUT_T62p DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T63n DIFFOUT_T64p DIFFOUT_T64n F780 J17 H18 H19 J18 C19 B19 A20 A21 C20 B21 F19 G19 E19 D19 D20 F20 D21 C21 A22 A23 C22 B22 H21 E21 E22 D22 G21 F21 B24 A24 D24 C25 D23 C24 A26 C26 B25 A25 A27 B27 AD2 AD1 AC4 AC3 AB2 AB1 AA4 AA3 Y2 Y1 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No DQS for X8/X9 for DQS for X4 for F780 F780 DQS for X16/X18 for F780 DQ12T DQ12T DQ12T DQ12T DQS12T DQSn12T DQ13T DQ13T DQS13T DQSn13T DQ13T DQ13T DQ14T DQ14T DQ14T DQ14T DQS14T DQSn14T DQ15T DQ15T DQS15T DQSn15T DQ15T DQ15T DQ16T DQ16T DQ16T DQ16T DQS16T DQSn16T DQ17T DQ17T DQS17T DQSn17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQS17T/CQ17T DQSn17T/DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T/CQn17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ15T DQ15T DQ15T DQ15T DQS15T/CQ15T DQSn15T/DQ15T DQ15T DQ15T DQ15T/CQn15T DQ15T DQ15T DQ15T DQ16T DQ16T DQ16T DQ16T DQS16T/CQ16T DQSn16T/DQ16T DQ16T DQ16T DQ16T/CQn16T DQ16T DQ16T DQ16T DQ17T DQ17T DQ17T DQ17T DQS17T/CQ17T DQSn17T/DQ17T DQ17T DQ17T DQ17T/CQn17T DQ17T DQ17T DQ17T Page 8 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 VREF Pin Name/Function REFCLK_R1p,GXB_CMURX_R1p REFCLK_R1n,GXB_CMURX_R1n GXB_RX_R2p GXB_RX_R2n GXB_TX_R2p GXB_TX_R2n GXB_RX_R3p GXB_RX_R3n GXB_TX_R3p GXB_TX_R3n GXB_RX_R4p GXB_RX_R4n GXB_TX_R4p GXB_TX_R4n GXB_RX_R5p GXB_RX_R5n GXB_TX_R5p GXB_TX_R5n REFCLK_R2p,GXB_CMURX_R2p REFCLK_R2n,GXB_CMURX_R2n REFCLK_R3p,GXB_CMURX_R3p REFCLK_R3n,GXB_CMURX_R3n GXB_RX_R6p GXB_RX_R6n GXB_TX_R6p GXB_TX_R6n GXB_RX_R7p GXB_RX_R7n GXB_TX_R7p GXB_TX_R7n GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List F780 Emulated LVDS Output Channel F780 W4 W3 V2 V1 U4 U3 T2 T1 R4 R3 P2 P1 N4 N3 M2 M1 L4 L3 K2 K1 J4 J3 H2 H1 G4 G3 F2 F1 E4 E3 W8 P15 AG3 AG6 AG9 AG12 AG15 AG18 AG21 AG24 AG27 AD6 AD9 AD12 AD15 AD18 AD21 AD24 AD27 AA6 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X8/X9 for DQS for X4 for F780 F780 DQS for X16/X18 for F780 Page 9 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List F780 Emulated LVDS Output Channel F780 AA9 AA12 AA15 AA18 AA21 AA24 AA27 W12 W14 W16 W18 W19 V9 V11 V13 V15 V17 V19 V21 V24 V27 U12 U14 U16 U18 T11 T13 T15 T17 T19 R12 R16 R18 R21 R24 R27 P11 P13 P17 P19 N12 N14 N16 N18 M11 M13 M15 M17 M19 M21 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X8/X9 for DQS for X4 for F780 F780 DQS for X16/X18 for F780 Page 10 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List F780 Emulated LVDS Output Channel F780 M24 M27 L8 L12 L14 L16 L18 K11 K13 K15 K17 K19 J21 J24 J27 H5 H8 H11 H14 H17 H20 F24 F27 E5 E8 E11 E14 E17 E20 E23 C27 B2 B5 B8 B11 B14 B17 B20 B23 B26 C2 C1 D4 D3 D2 E2 E1 F4 F3 G2 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X8/X9 for DQS for X4 for F780 F780 DQS for X16/X18 for F780 Page 11 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List F780 Emulated LVDS Output Channel F780 G1 H4 H3 J2 J1 K4 K3 L5 L2 L1 M6 M4 M3 N7 N5 N2 N1 P8 P6 P4 P3 R7 R5 R2 R1 T8 T6 T4 T3 U5 U2 U1 V6 V4 V3 W2 W1 Y4 Y3 AA2 AA1 AB4 AB3 AC2 AC1 AD4 AD3 AE2 AE1 AF2 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X8/X9 for DQS for X4 for F780 F780 DQS for X16/X18 for F780 Page 12 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF Pin Name/Function GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPT VCCPT VCCPT VCCPT VCCPT VCCPT DNU VCCPGM VCCPGM TEMPDIODEn TEMPDIODEp VCC_CLKIN3C PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List F780 Emulated LVDS Output Channel F780 AG2 AG1 P14 V14 V18 U11 U13 U15 U17 T12 T14 T16 R13 R15 R17 P12 P16 N13 N15 N17 M12 M14 M16 P18 L11 L17 L13 L15 N11 M18 R11 T18 V12 V16 U7 U8 M7 M8 R22 P22 AB14 R10 P10 G15 R14 Y20 W9 H7 G6 AD14 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X8/X9 for DQS for X4 for F780 F780 DQS for X16/X18 for F780 Page 13 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF Pin Name/Function VCC_CLKIN4C VCC_CLKIN7C VCC_CLKIN8C VCCBAT VCCA_PLL_B1 VCCA_PLL_L2 VCCA_PLL_T1 VCCD_PLL_B1 VCCD_PLL_L2 VCCD_PLL_T1 VCCIO1A VCCIO1A VCCIO1A VCCIO1C VCCIO1C VCCIO2A VCCIO2A VCCIO2A VCCIO2C VCCIO2C VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3C VCCIO3C VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4C VCCIO4C VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7C VCCIO7C VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8C VCCIO8C VCCPD1A VCCPD1C VCCPD2A VCCPD2C VCCPD3A VCCPD3C PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List F780 Emulated LVDS Output Channel F780 AC13 F14 F16 H6 AC14 R23 E15 AC15 P23 F15 J23 H26 E26 P24 N26 AD25 AB26 AA23 T24 T26 AF20 AF23 AC20 Y19 AF17 AC17 AF5 AF8 AC7 AC9 AF13 AC11 J10 F9 C6 C9 F12 C12 J19 F22 E24 C23 G18 C16 L19 N19 U19 R19 W17 W15 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X8/X9 for DQS for X4 for F780 F780 DQS for X16/X18 for F780 Page 14 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF 1A 1C 2A 2C 3A 3C 4A 4C 7A 7C 8A 8C VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 Pin Name/Function VCCPD4A VCCPD4C VCCPD7A VCCPD7C VCCPD8A VCCPD8C VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 Pin List F780 Emulated LVDS Output Channel F780 W11 W13 K12 K14 K18 K16 J22 M22 Y22 U22 AB19 AB16 AB8 AB13 G10 G13 G20 G16 F23 AE26 AB6 J8 AE4 AE3 AE5 AD5 AC5 AB5 AA5 Y5 W5 W10 V7 V8 V10 U9 U10 U20 T9 T10 N10 M9 M10 M20 L7 L9 L10 K5 K6 K7 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X8/X9 for DQS for X4 for F780 F780 DQS for X16/X18 for F780 Page 15 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF Pin Name/Function NC NC NC NC NC NC NC NC NC VCCAUX VCCAUX VCCAUX VCCAUX VCCA_R VCCA_R VCCH_GXBR0 VCCH_GXBR1 VCCL_GXBR0 VCCL_GXBR0 VCCL_GXBR1 VCCL_GXBR1 VCCR_R VCCR_R VCCT_R VCCT_R VCCHIP_R VCCHIP_R VCCHIP_R RREF_R0 RREF_R1 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Pin List F780 Emulated LVDS Output Channel F780 K8 K10 K20 J5 J6 G5 F5 C3 B1 G22 AB22 AA7 G7 N6 T5 V5 L6 R8 T7 N8 P7 M5 R6 P5 U6 N9 P9 R9 AF1 D1 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X8/X9 for DQS for X4 for F780 F780 DQS for X16/X18 for F780 Page 16 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C VREF VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function TDI TMS TRST TCK TDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function TDI TMS TRST TCK TDO RDN1A RUP1A CLKUSR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 INIT_DONE CRC_ERROR DEV_OE Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_TX_L1n DIFFIO_TX_L1p DIFFIO_RX_L1n DIFFIO_RX_L1p DIFFIO_TX_L2n DIFFIO_TX_L2p DIFFIO_RX_L2n DIFFIO_RX_L2p DIFFIO_TX_L3n DIFFIO_TX_L3p DIFFIO_RX_L3n DIFFIO_RX_L3p DIFFIO_TX_L4n DIFFIO_TX_L4p DIFFIO_RX_L4n DIFFIO_RX_L4p DIFFIO_TX_L5n DIFFIO_TX_L5p DIFFIO_RX_L5n DIFFIO_RX_L5p DIFFIO_TX_L6n DIFFIO_TX_L6p DIFFIO_RX_L6n DIFFIO_RX_L6p DIFFIO_TX_L7n DIFFIO_TX_L7p DIFFIO_RX_L7n DIFFIO_RX_L7p DIFFIO_TX_L8n DIFFIO_TX_L8p DIFFIO_RX_L8n DIFFIO_RX_L8p DIFFIO_TX_L9n DIFFIO_TX_L9p DIFFIO_RX_L9n DIFFIO_RX_L9p DIFFIO_TX_L10n DIFFIO_TX_L10p DIFFIO_RX_L10n DIFFIO_RX_L10p DIFFIO_TX_L11n DIFFIO_TX_L11p DIFFIO_RX_L11n DIFFIO_RX_L11p DIFFIO_TX_L12n DIFFIO_TX_L12p DIFFIO_RX_L12n DIFFIO_RX_L12p DIFFIO_TX_L13n DIFFIO_TX_L13p DIFFIO_RX_L13n DIFFOUT_L1n DIFFOUT_L1p DIFFOUT_L2n DIFFOUT_L2p DIFFOUT_L3n DIFFOUT_L3p DIFFOUT_L4n DIFFOUT_L4p DIFFOUT_L5n DIFFOUT_L5p DIFFOUT_L6n DIFFOUT_L6p DIFFOUT_L7n DIFFOUT_L7p DIFFOUT_L8n DIFFOUT_L8p DIFFOUT_L9n DIFFOUT_L9p DIFFOUT_L10n DIFFOUT_L10p DIFFOUT_L11n DIFFOUT_L11p DIFFOUT_L12n DIFFOUT_L12p DIFFOUT_L13n DIFFOUT_L13p DIFFOUT_L14n DIFFOUT_L14p DIFFOUT_L15n DIFFOUT_L15p DIFFOUT_L16n DIFFOUT_L16p DIFFOUT_L17n DIFFOUT_L17p DIFFOUT_L18n DIFFOUT_L18p DIFFOUT_L19n DIFFOUT_L19p DIFFOUT_L20n DIFFOUT_L20p DIFFOUT_L21n DIFFOUT_L21p DIFFOUT_L22n DIFFOUT_L22p DIFFOUT_L23n DIFFOUT_L23p DIFFOUT_L24n DIFFOUT_L24p DIFFOUT_L25n DIFFOUT_L25p DIFFOUT_L26n Pin List F1152 F1152 Note(1), (2) G28 H28 K26 F29 G29 G30 H29 E31 E30 J29 J28 C32 D32 K28 L27 B34 A33 L26 M25 C34 B33 N25 N24 F32 F31 K29 L28 D34 D33 H31 H30 G32 G31 K30 L29 E34 E33 T23 U23 N32 N31 P29 R29 M34 N33 T29 T28 P32 P31 T27 T26 N34 P33 V25 U24 R32 Dynamic OCT Support No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 DQ1L DQ1L DQSn1L DQS1L DQ1L DQ1L DQSn2L DQS2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQSn3L DQS3L DQ3L DQ3L DQSn4L DQS4L DQ4L DQ4L DQ4L DQ4L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ2L DQ2L/CQn2L DQ2L DQ2L DQSn2L/DQ2L DQS2L/CQ2L DQ2L DQ2L DQ2L DQ2L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn5L DQS5L DQ5L DQ5L DQ5L DQ5L DQ6L DQ6L DQSn6L DQS6L DQ6L DQ6L DQSn7L DQS7L DQ7L DQ7L DQ7L DQ5L DQ5L DQ5L DQ5L/CQn5L DQ5L DQ5L DQSn5L/DQ5L DQS5L/CQ5L DQ5L DQ5L DQ5L Page 17 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 1C 1C 1C 1C 1C 1C 1C 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3C 3C 3C 3C VREF VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3AN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO CLK1n CLK1p nCONFIG nSTATUS CONF_DONE PORSEL nCE IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function DEV_CLRn PLL_L2_CLKOUT0n PLL_L2_FB_CLKOUT0p CLK0n CLK0p CLK1n CLK1p Dedicated Tx/Rx Channel DIFFIO_RX_L13p DIFFIO_TX_L14n DIFFIO_TX_L14p DIFFIO_RX_L14n DIFFIO_RX_L14p Emulated LVDS Output Channel DIFFOUT_L26p DIFFOUT_L27n DIFFOUT_L27p DIFFOUT_L28n DIFFOUT_L28p nCONFIG nSTATUS CONF_DONE nCE RDN3A RUP3A DIFFIO_RX_B1n DIFFIO_RX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_RX_B3n DIFFIO_RX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_RX_B5n DIFFIO_RX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_RX_B8n DIFFIO_RX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_RX_B10n DIFFIO_RX_B10p DIFFIO_RX_B11n DIFFIO_RX_B11p DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B21p DIFFOUT_B22n DIFFOUT_B22p Pin List F1152 F1152 Note(1), (2) R31 V23 W23 T31 T30 P34 R34 AC27 AM30 AN30 AL28 AM29 AA25 AB25 AC26 AC25 AB24 AC24 AE25 AD26 AD23 AE24 AE27 AE26 AG26 AF24 AH27 AH26 AJ27 AG25 AH25 AH24 AJ25 AK26 AG23 AF23 AL27 AM27 AM26 AL26 AK25 AN28 AP32 AP31 AP28 AP27 AP30 AP29 AB23 AA23 AD22 AC22 AM22 AP22 AP23 AN23 Dynamic OCT Support Yes No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 DQ7L DQS for X8/X9 for F1152 DQ5L DQS for X16/X18 for F1152 DQ1B DQ1B DQSn1B DQS1B DQ1B DQ1B DQSn2B DQS2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQSn3B DQS3B DQ3B DQ3B DQSn4B DQS4B DQ4B DQ4B DQ4B DQ4B DQ5B DQ5B DQSn5B DQS5B DQ5B DQ5B DQSn6B DQS6B DQ6B DQ6B DQ6B DQ6B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQ3B DQ3B/CQn3B DQ3B DQ3B DQSn3B/DQ3B DQS3B/CQ3B DQ3B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ7B DQ7B DQSn7B DQS7B DQ7B DQ7B DQ7B DQ7B/CQn7B Page 18 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A VREF VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B12n DIFFIO_RX_B12p DIFFIO_RX_B13n DIFFIO_RX_B13p PLL_B1_CLKOUT4 PLL_B1_CLKOUT3 DIFFIO_RX_B14n DIFFIO_RX_B14p PLL_B1_CLKOUT0n PLL_B1_CLKOUT0p PLL_B1_FBn/CLKOUT2 PLL_B1_FBp/CLKOUT1 CLK5n CLK5p CLK4n CLK4p CLK6p CLK6n CLK7p CLK7n DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_RX_B16n DIFFIO_RX_B16p DIFFIO_RX_B17p DIFFIO_RX_B17n DIFFIO_RX_B18p DIFFIO_RX_B18n DIFFIO_RX_B19p DIFFIO_RX_B19n DIFFIO_RX_B20p DIFFIO_RX_B20n DIFFIO_RX_B21p DIFFIO_RX_B21n DIFFIO_RX_B22p DIFFIO_RX_B22n DIFFIO_RX_B23p DIFFIO_RX_B23n DIFFIO_RX_B24p DIFFIO_RX_B24n DIFFIO_RX_B25p DIFFIO_RX_B25n Emulated LVDS Output Channel DIFFOUT_B23n DIFFOUT_B23p DIFFOUT_B24n DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B25p DIFFOUT_B26n DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B27p DIFFOUT_B28n DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B29p DIFFOUT_B30n DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B31p DIFFOUT_B32n DIFFOUT_B32p DIFFOUT_B33p DIFFOUT_B33n DIFFOUT_B34p DIFFOUT_B34n DIFFOUT_B35p DIFFOUT_B35n DIFFOUT_B36p DIFFOUT_B36n DIFFOUT_B37p DIFFOUT_B37n DIFFOUT_B38p DIFFOUT_B38n DIFFOUT_B39p DIFFOUT_B39n DIFFOUT_B40p DIFFOUT_B40n DIFFOUT_B41p DIFFOUT_B41n DIFFOUT_B42p DIFFOUT_B42n DIFFOUT_B43p DIFFOUT_B43n DIFFOUT_B44p DIFFOUT_B44n DIFFOUT_B45p DIFFOUT_B45n DIFFOUT_B46p DIFFOUT_B46n DIFFOUT_B47p DIFFOUT_B47n DIFFOUT_B48p DIFFOUT_B48n DIFFOUT_B49p DIFFOUT_B49n DIFFOUT_B50p DIFFOUT_B50n Pin List F1152 F1152 Note(1), (2) AP21 AN22 AM21 AL21 AJ21 AK20 AM20 AL20 AD19 AC18 AG20 AF19 AE19 AE18 AM18 AL18 AP20 AP19 AP18 AP17 AP15 AP16 AM17 AN17 AG16 AH16 AJ16 AK16 AM15 AM16 AL16 AH15 AP13 AP14 AP12 AN14 AM13 AN13 AL15 AJ15 AK14 AL14 AJ14 AM14 Y12 AA12 AC12 AD13 AP5 AP6 AN7 AP7 AP3 AP4 AP8 AL9 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 DQ7B DQ7B DQSn8B DQS8B DQ8B DQ8B DQ8B DQ8B DQS for X8/X9 for F1152 DQ7B DQ7B DQSn7B/DQ7B DQS7B/CQ7B DQ7B DQ7B DQ7B DQ7B DQ9B DQ9B DQS9B DQSn9B DQ9B DQ9B DQ10B DQ10B DQ10B DQ10B DQS10B DQSn10B DQ11B DQ11B DQS11B DQSn11B DQ11B DQ11B DQ11B DQ11B DQ11B DQ11B DQS11B/CQ11B DQSn11B/DQ11B DQ11B DQ11B DQ11B/CQn11B DQ11B DQ11B DQ11B DQ12B DQ12B DQ12B DQ12B DQS12B DQSn12B DQ13B DQ13B DQ15B DQ15B DQ15B DQ15B DQS15B/CQ15B DQSn15B/DQ15B DQ15B DQ15B DQS for X16/X18 for F1152 Page 19 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C VREF VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO nIO_PULLUP nCEO DCLK nCSO ASDO CLK10p CLK10n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B26p DIFFIO_RX_B26n DIFFIO_RX_B27p DIFFIO_RX_B27n DIFFIO_RX_B28p DIFFIO_RX_B28n DIFFIO_RX_B29p DIFFIO_RX_B29n DIFFIO_RX_B30p DIFFIO_RX_B30n DIFFIO_RX_B31p DIFFIO_RX_B31n RUP4A RDN4A DIFFIO_RX_B32p DIFFIO_RX_B32n Emulated LVDS Output Channel DIFFOUT_B51p DIFFOUT_B51n DIFFOUT_B52p DIFFOUT_B52n DIFFOUT_B53p DIFFOUT_B53n DIFFOUT_B54p DIFFOUT_B54n DIFFOUT_B55p DIFFOUT_B55n DIFFOUT_B56p DIFFOUT_B56n DIFFOUT_B57p DIFFOUT_B57n DIFFOUT_B58p DIFFOUT_B58n DIFFOUT_B59p DIFFOUT_B59n DIFFOUT_B60p DIFFOUT_B60n DIFFOUT_B61p DIFFOUT_B61n DIFFOUT_B62p DIFFOUT_B62n DIFFOUT_B63p DIFFOUT_B63n DIFFOUT_B64p DIFFOUT_B64n nIO_PULLUP nCEO DCLK nCSO ASDO CLK10p CLK10n CLK11p CLK11n PLL_R2_FB_CLKOUT0p PLL_R2_CLKOUT0n DIFFIO_RX_R15p DIFFIO_RX_R15n DIFFIO_TX_R15p DIFFIO_TX_R15n DIFFIO_RX_R16p DIFFIO_RX_R16n DIFFIO_TX_R16p DIFFIO_TX_R16n DIFFIO_RX_R17p DIFFIO_RX_R17n DIFFIO_TX_R17p DIFFIO_TX_R17n DIFFIO_RX_R18p DIFFIO_RX_R18n DIFFIO_TX_R18p DIFFIO_TX_R18n DIFFIO_RX_R19p DIFFIO_RX_R19n DIFFIO_TX_R19p DIFFIO_TX_R19n DIFFIO_RX_R20p DIFFOUT_R29p DIFFOUT_R29n DIFFOUT_R30p DIFFOUT_R30n DIFFOUT_R31p DIFFOUT_R31n DIFFOUT_R32p DIFFOUT_R32n DIFFOUT_R33p DIFFOUT_R33n DIFFOUT_R34p DIFFOUT_R34n DIFFOUT_R35p DIFFOUT_R35n DIFFOUT_R36p DIFFOUT_R36n DIFFOUT_R37p DIFFOUT_R37n DIFFOUT_R38p DIFFOUT_R38n DIFFOUT_R39p Pin List F1152 F1152 Note(1), (2) AM8 AN8 AL7 AL8 AJ10 AK10 AH11 AJ11 AF12 AG11 AJ9 AG10 AJ8 AK8 AH8 AH9 AD9 AE9 AE11 AE12 AD11 AE10 AB11 AB12 AB10 AC10 AA10 AA11 AM6 AE8 AM5 AD8 AN5 P1 R1 R3 R2 U12 V12 T5 T4 V11 U10 P4 P3 T9 T8 N2 N1 T11 T10 M2 M1 T7 T6 N4 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 DQS13B DQSn13B DQ13B DQ13B DQ14B DQ14B DQ14B DQ14B DQS14B DQSn14B DQ15B DQ15B DQS15B DQSn15B DQ15B DQ15B DQ16B DQ16B DQ16B DQ16B DQS16B DQSn16B DQ17B DQ17B DQS17B DQSn17B DQ17B DQ17B DQS for X8/X9 for F1152 DQ15B/CQn15B DQ15B DQ15B DQ15B DQ16B DQ16B DQ16B DQ16B DQS16B/CQ16B DQSn16B/DQ16B DQ16B DQ16B DQ16B/CQn16B DQ16B DQ16B DQ16B DQ17B DQ17B DQ17B DQ17B DQS17B/CQ17B DQSn17B/DQ17B DQ17B DQ17B DQ17B/CQn17B DQ17B DQ17B DQ17B DQ8R DQ8R DQ8R DQ8R DQS8R DQSn8R DQ9R DQ9R DQS9R DQSn9R DQ9R DQ9R DQ10R DQ10R DQ10R DQ10R DQS10R DQ10R DQ10R DQ10R DQ10R DQS10R/CQ10R DQSn10R/DQ10R DQ10R DQ10R DQ10R/CQn10R DQ10R DQ10R DQ10R DQS for X16/X18 for F1152 DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQS17B/CQ17B DQSn17B/DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B/CQn17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B Page 20 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 6C 6C 6C 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A VREF VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL2 MSEL1 MSEL0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function RUP6A RDN6A Dedicated Tx/Rx Channel DIFFIO_RX_R20n DIFFIO_TX_R20p DIFFIO_TX_R20n DIFFIO_RX_R21p DIFFIO_RX_R21n DIFFIO_TX_R21p DIFFIO_TX_R21n DIFFIO_RX_R22p DIFFIO_RX_R22n DIFFIO_TX_R22p DIFFIO_TX_R22n DIFFIO_RX_R23p DIFFIO_RX_R23n DIFFIO_TX_R23p DIFFIO_TX_R23n DIFFIO_RX_R24p DIFFIO_RX_R24n DIFFIO_TX_R24p DIFFIO_TX_R24n DIFFIO_RX_R25p DIFFIO_RX_R25n DIFFIO_TX_R25p DIFFIO_TX_R25n DIFFIO_RX_R26p DIFFIO_RX_R26n DIFFIO_TX_R26p DIFFIO_TX_R26n DIFFIO_RX_R27p DIFFIO_RX_R27n DIFFIO_TX_R27p DIFFIO_TX_R27n DIFFIO_RX_R28p DIFFIO_RX_R28n DIFFIO_TX_R28p DIFFIO_TX_R28n Emulated LVDS Output Channel DIFFOUT_R39n DIFFOUT_R40p DIFFOUT_R40n DIFFOUT_R41p DIFFOUT_R41n DIFFOUT_R42p DIFFOUT_R42n DIFFOUT_R43p DIFFOUT_R43n DIFFOUT_R44p DIFFOUT_R44n DIFFOUT_R45p DIFFOUT_R45n DIFFOUT_R46p DIFFOUT_R46n DIFFOUT_R47p DIFFOUT_R47n DIFFOUT_R48p DIFFOUT_R48n DIFFOUT_R49p DIFFOUT_R49n DIFFOUT_R50p DIFFOUT_R50n DIFFOUT_R51p DIFFOUT_R51n DIFFOUT_R52p DIFFOUT_R52n DIFFOUT_R53p DIFFOUT_R53n DIFFOUT_R54p DIFFOUT_R54n DIFFOUT_R55p DIFFOUT_R55n DIFFOUT_R56p DIFFOUT_R56n MSEL2 MSEL1 MSEL0 RDN7A RUP7A DIFFIO_RX_T1n DIFFIO_RX_T1p DIFFIO_RX_T2n DIFFIO_RX_T2p DIFFIO_RX_T3n DIFFIO_RX_T3p DIFFIO_RX_T4n DIFFIO_RX_T4p DIFFOUT_T1n DIFFOUT_T1p DIFFOUT_T2n DIFFOUT_T2p DIFFOUT_T3n DIFFOUT_T3p DIFFOUT_T4n DIFFOUT_T4p DIFFOUT_T5n DIFFOUT_T5p DIFFOUT_T6n DIFFOUT_T6p DIFFOUT_T7n DIFFOUT_T7p DIFFOUT_T8n DIFFOUT_T8p DIFFOUT_T9n DIFFOUT_T9p Pin List F1152 F1152 Note(1), (2) N3 R6 R5 H4 H3 K6 K5 F2 E1 N11 N10 G4 G3 N12 M11 D2 D1 J6 J5 C2 C1 M9 M8 E4 E3 K8 K7 D4 D3 F5 F4 A2 B1 H7 H6 K9 L10 J9 J11 K11 H12 J12 K12 L12 F8 G8 H9 G9 G10 H10 F7 F6 D6 E6 E7 D7 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 DQSn10R DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 DQ11R DQ11R DQ11R DQ11R DQS11R DQSn11R DQ12R DQ12R DQS12R DQSn12R DQ12R DQ12R DQ13R DQ13R DQ13R DQ13R DQS13R DQSn13R DQ14R DQ14R DQS14R DQSn14R DQ14R DQ14R DQ13R DQ13R DQ13R DQ13R DQS13R/CQ13R DQSn13R/DQ13R DQ13R DQ13R DQ13R/CQn13R DQ13R DQ13R DQ13R DQ14R DQ14R DQ14R DQ14R DQS14R/CQ14R DQSn14R/DQ14R DQ14R DQ14R DQ14R/CQn14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQS14R/CQ14R DQSn14R/DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R/CQn14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ1T DQ1T DQSn1T DQS1T DQ1T DQ1T DQSn2T DQS2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQSn3T DQS3T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ2T DQ2T/CQn2T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T Page 21 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C VREF VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T5n DIFFIO_RX_T5p DIFFIO_RX_T6n DIFFIO_RX_T6p DIFFIO_RX_T7n DIFFIO_RX_T7p DIFFIO_RX_T8n DIFFIO_RX_T8p DIFFIO_RX_T9n DIFFIO_RX_T9p DIFFIO_RX_T10n DIFFIO_RX_T10p DIFFIO_RX_T11n DIFFIO_RX_T11p DIFFIO_RX_T12n DIFFIO_RX_T12p DIFFIO_RX_T13n DIFFIO_RX_T13p DIFFIO_RX_T14n DIFFIO_RX_T14p DIFFIO_RX_T15n DIFFIO_RX_T15p CLK13n CLK13p CLK12n CLK12p CLK14p CLK14n CLK15p CLK15n PLL_T1_FBp/CLKOUT1 PLL_T1_FBn/CLKOUT2 PLL_T1_CLKOUT0p PLL_T1_CLKOUT0n DIFFIO_RX_T16n DIFFIO_RX_T16p DIFFIO_RX_T17p DIFFIO_RX_T17n DIFFIO_RX_T18p DIFFIO_RX_T18n DIFFIO_RX_T19p DIFFIO_RX_T19n Emulated LVDS Output Channel DIFFOUT_T10n DIFFOUT_T10p DIFFOUT_T11n DIFFOUT_T11p DIFFOUT_T12n DIFFOUT_T12p DIFFOUT_T13n DIFFOUT_T13p DIFFOUT_T14n DIFFOUT_T14p DIFFOUT_T15n DIFFOUT_T15p DIFFOUT_T16n DIFFOUT_T16p DIFFOUT_T17n DIFFOUT_T17p DIFFOUT_T18n DIFFOUT_T18p DIFFOUT_T19n DIFFOUT_T19p DIFFOUT_T20n DIFFOUT_T20p DIFFOUT_T21n DIFFOUT_T21p DIFFOUT_T22n DIFFOUT_T22p DIFFOUT_T23n DIFFOUT_T23p DIFFOUT_T24n DIFFOUT_T24p DIFFOUT_T25n DIFFOUT_T25p DIFFOUT_T26n DIFFOUT_T26p DIFFOUT_T27n DIFFOUT_T27p DIFFOUT_T28n DIFFOUT_T28p DIFFOUT_T29n DIFFOUT_T29p DIFFOUT_T30n DIFFOUT_T30p DIFFOUT_T31n DIFFOUT_T31p DIFFOUT_T32n DIFFOUT_T32p DIFFOUT_T33p DIFFOUT_T33n DIFFOUT_T34p DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T35n DIFFOUT_T36p DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T37n Pin List F1152 F1152 Note(1), (2) B4 C5 A5 A4 A3 B3 G11 E10 C8 D8 E9 F10 A6 B6 A7 C6 A8 B7 L13 M13 C9 D9 A13 A12 B13 C13 C12 B12 C14 D14 C15 A14 A15 B15 C16 D15 E15 F15 F16 E16 G16 H15 A16 B16 A17 A18 C18 B18 A20 A19 E18 D18 M19 L18 H19 G19 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No DQS for X4 for F1152 DQSn4T DQS4T DQ4T DQ4T DQ4T DQ4T DQ5T DQ5T DQSn5T DQS5T DQ5T DQ5T DQSn6T DQS6T DQ6T DQ6T DQ6T DQ6T DQS for X8/X9 for F1152 DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQ3T DQ3T/CQn3T DQ3T DQ3T DQSn3T/DQ3T DQS3T/CQ3T DQ3T DQ3T DQ3T DQ3T DQ7T DQ7T DQSn7T DQS7T DQ7T DQ7T DQSn8T DQS8T DQ8T DQ8T DQ8T DQ8T DQ9T DQ9T DQSn9T DQS9T DQ9T DQ9T DQ7T DQ7T DQ7T DQ7T/CQn7T DQ7T DQ7T DQSn7T/DQ7T DQS7T/CQ7T DQ7T DQ7T DQ7T DQ7T DQS for X16/X18 for F1152 DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T Page 22 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A QL1 QL1 VREF VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GXB_TX_L7n GXB_TX_L7p Optional Function(s) PLL_T1_CLKOUT3 PLL_T1_CLKOUT4 Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T20p DIFFIO_RX_T20n DIFFIO_RX_T21p DIFFIO_RX_T21n DIFFIO_RX_T22p DIFFIO_RX_T22n DIFFIO_RX_T23p DIFFIO_RX_T23n DIFFIO_RX_T24p DIFFIO_RX_T24n DIFFIO_RX_T25p DIFFIO_RX_T25n DIFFIO_RX_T26p DIFFIO_RX_T26n DIFFIO_RX_T27p DIFFIO_RX_T27n DIFFIO_RX_T28p DIFFIO_RX_T28n DIFFIO_RX_T29p DIFFIO_RX_T29n DIFFIO_RX_T30p DIFFIO_RX_T30n DIFFIO_RX_T31p DIFFIO_RX_T31n RUP8A RDN8A DIFFIO_RX_T32p DIFFIO_RX_T32n Emulated LVDS Output Channel DIFFOUT_T38p DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T39n DIFFOUT_T40p DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T41n DIFFOUT_T42p DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T43n DIFFOUT_T44p DIFFOUT_T44n DIFFOUT_T45p DIFFOUT_T45n DIFFOUT_T46p DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T47n DIFFOUT_T48p DIFFOUT_T48n DIFFOUT_T49p DIFFOUT_T49n DIFFOUT_T50p DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T51n DIFFOUT_T52p DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T53n DIFFOUT_T54p DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T55n DIFFOUT_T56p DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T57n DIFFOUT_T58p DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T59n DIFFOUT_T60p DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T61n DIFFOUT_T62p DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T63n DIFFOUT_T64p DIFFOUT_T64n Pin List F1152 F1152 Note(1), (2) L19 K20 A23 A22 B21 A21 C22 B22 F21 C20 E21 D21 D20 C21 M23 L22 L24 K25 B28 A29 A27 A28 C27 B27 E25 F24 D26 D27 F25 E27 A31 A32 A30 B30 C31 B31 E28 D28 D29 C29 D30 C30 G26 F26 G25 H25 G27 F27 J23 K23 J24 H24 J25 K24 V32 V31 Dynamic OCT Support No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQ10T DQ10T DQ10T DQ10T DQS10T DQSn10T DQ11T DQ11T DQS11T DQSn11T DQ11T DQ11T DQ11T DQ11T DQ11T DQ11T DQS11T/CQ11T DQSn11T/DQ11T DQ11T DQ11T DQ11T/CQn11T DQ11T DQ11T DQ11T DQ12T DQ12T DQ12T DQ12T DQS12T DQSn12T DQ13T DQ13T DQS13T DQSn13T DQ13T DQ13T DQ14T DQ14T DQ14T DQ14T DQS14T DQSn14T DQ15T DQ15T DQS15T DQSn15T DQ15T DQ15T DQ16T DQ16T DQ16T DQ16T DQS16T DQSn16T DQ17T DQ17T DQS17T DQSn17T DQ17T DQ17T DQ15T DQ15T DQ15T DQ15T DQS15T/CQ15T DQSn15T/DQ15T DQ15T DQ15T DQ15T/CQn15T DQ15T DQ15T DQ15T DQ16T DQ16T DQ16T DQ16T DQS16T/CQ16T DQSn16T/DQ16T DQ16T DQ16T DQ16T/CQn16T DQ16T DQ16T DQ16T DQ17T DQ17T DQ17T DQ17T DQS17T/CQ17T DQSn17T/DQ17T DQ17T DQ17T DQ17T/CQn17T DQ17T DQ17T DQ17T DQS for X16/X18 for F1152 DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQS17T/CQ17T DQSn17T/DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T/CQn17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T Page 23 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GXB_RX_L7n GXB_RX_L7p GXB_TX_L6n GXB_TX_L6p GXB_RX_L6n GXB_RX_L6p REFCLK_L3n,GXB_CMURX_L3n REFCLK_L3p,GXB_CMURX_L3p REFCLK_L2n,GXB_CMURX_L2n REFCLK_L2p,GXB_CMURX_L2p GXB_TX_L5n GXB_TX_L5p GXB_RX_L5n GXB_RX_L5p GXB_TX_L4n GXB_TX_L4p GXB_RX_L4n GXB_RX_L4p GXB_TX_L3n GXB_TX_L3p GXB_RX_L3n GXB_RX_L3p GXB_TX_L2n GXB_TX_L2p GXB_RX_L2n GXB_RX_L2p REFCLK_L1n,GXB_CMURX_L1n REFCLK_L1p,GXB_CMURX_L1p REFCLK_L0n,GXB_CMURX_L0n REFCLK_L0p,GXB_CMURX_L0p GXB_TX_L1n GXB_TX_L1p GXB_RX_L1n GXB_RX_L1p GXB_TX_L0n GXB_TX_L0p GXB_RX_L0n GXB_RX_L0p GXB_RX_R0p GXB_RX_R0n GXB_TX_R0p GXB_TX_R0n GXB_RX_R1p GXB_RX_R1n GXB_TX_R1p GXB_TX_R1n REFCLK_R0p,GXB_CMURX_R0p REFCLK_R0n,GXB_CMURX_R0n REFCLK_R1p,GXB_CMURX_R1p REFCLK_R1n,GXB_CMURX_R1n GXB_RX_R2p GXB_RX_R2n GXB_TX_R2p GXB_TX_R2n GXB_RX_R3p GXB_RX_R3n Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) U34 U33 Y32 Y31 W34 W33 AC30 AC29 AE30 AE29 AB32 AB31 AA34 AA33 AD32 AD31 AC34 AC33 AF32 AF31 AE34 AE33 AH32 AH31 AG34 AG33 AG30 AG29 AJ30 AJ29 AK32 AK31 AJ34 AJ33 AM32 AM31 AL34 AL33 AL2 AL1 AM4 AM3 AJ2 AJ1 AK4 AK3 AJ6 AJ5 AG6 AG5 AG2 AG1 AH4 AH3 AE2 AE1 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 24 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number QR0 QR0 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GXB_TX_R3p GXB_TX_R3n GXB_RX_R4p GXB_RX_R4n GXB_TX_R4p GXB_TX_R4n GXB_RX_R5p GXB_RX_R5n GXB_TX_R5p GXB_TX_R5n REFCLK_R2p,GXB_CMURX_R2p REFCLK_R2n,GXB_CMURX_R2n REFCLK_R3p,GXB_CMURX_R3p REFCLK_R3n,GXB_CMURX_R3n GXB_RX_R6p GXB_RX_R6n GXB_TX_R6p GXB_TX_R6n GXB_RX_R7p GXB_RX_R7n GXB_TX_R7p GXB_TX_R7n GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) AF4 AF3 AC2 AC1 AD4 AD3 AA2 AA1 AB4 AB3 AE6 AE5 AC6 AC5 W2 W1 Y4 Y3 U2 U1 V4 V3 AC8 U18 B11 AN6 AN9 AN12 AN15 AN18 AN21 AN24 AN27 AN29 AK9 AK12 AK15 AK18 AK21 AK24 AK27 AG9 AG12 AG15 AG18 AG21 AG24 AG27 AF8 AD12 AD15 AD18 AD21 AD24 AD27 AC9 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 25 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) AC11 AB13 AB15 AB17 AB19 AB21 AA14 AA16 AA18 AA20 AA22 AA24 Y11 Y13 Y15 Y17 Y19 Y21 W14 W16 W18 W20 W22 V13 V15 V19 V21 V24 U11 U14 U16 U20 U22 T13 T15 T17 T19 T21 R14 R16 R18 R20 R22 R24 R27 R30 R33 P2 P5 P8 P11 P13 P15 P17 P19 P21 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 26 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) N14 N16 N18 N20 N22 M24 M27 M30 M33 L2 L5 L8 L11 L14 L17 L20 L23 J27 J30 J33 H2 H5 H8 H11 H14 H17 H20 H23 H26 F30 F33 E2 E5 E8 E11 E14 E17 E20 E23 E26 E29 C33 B2 B5 B8 B14 B17 B20 B23 B26 B29 B32 T34 T33 T32 U32 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 27 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) U31 U29 U27 V34 V33 V30 V28 W32 W31 W29 W27 Y34 Y33 AP33 AN31 AN32 AN33 AM33 AM34 AL31 AL32 AK29 AK30 AK33 AK34 AJ31 AJ32 AH29 AH30 AH33 AH34 AG31 AG32 AF29 AF30 AF33 AF34 AE31 AE32 AD29 AD30 AD33 AD34 AC31 AC32 AB28 AB30 AB33 AB34 AA27 AA29 AA31 AA32 Y28 Y30 T3 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 28 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) T2 T1 U8 U6 U4 U3 V7 V5 V2 V1 W8 W6 W4 W3 Y7 Y5 Y2 Y1 AA8 AA6 AA4 AP2 AN2 AN3 AN4 AM1 AM2 AL3 AL4 AK1 AK2 AK5 AK6 AJ3 AJ4 AH1 AH2 AH5 AH6 AG3 AG4 AF1 AF2 AF5 AF6 AE3 AE4 AD1 AD2 AD5 AD6 AC3 AC4 AB1 AB2 AB5 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 29 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) AB7 AA3 U17 AB14 AB22 AA13 AA15 AA17 AA19 AA21 Y14 Y16 Y18 Y20 W15 W17 W19 W21 V14 V16 V18 V20 U15 U19 U21 T14 T16 T18 T20 R15 R17 R19 R21 P14 P16 P18 P20 P22 N13 N21 N19 AB16 AB18 AB20 Y22 W13 V22 U13 T22 R13 N15 N17 AB26 AB27 V26 U26 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 30 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function VCC VCC VCC VCC VCCPT VCCPT VCCPT VCCPT VCCPT VCCPT DNU VCCPGM VCCPGM TEMPDIODEn TEMPDIODEp VCC_CLKIN3C VCC_CLKIN4C VCC_CLKIN7C VCC_CLKIN8C VCCBAT VCCA_PLL_B1 VCCA_PLL_L2 VCCA_PLL_R2 VCCA_PLL_T1 VCCD_PLL_B1 VCCD_PLL_L2 VCCD_PLL_R2 VCCD_PLL_T1 VCCIO1A VCCIO1A VCCIO1A VCCIO1C VCCIO1C VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3C VCCIO3C VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4C VCCIO4C VCCIO6A VCCIO6A VCCIO6A VCCIO6C VCCIO6C VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7C VCCIO7C Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) AB8 AB9 V9 U9 Y23 Y24 AF17 W11 W12 J18 V17 AD25 AD10 C3 D5 AF18 AE17 J17 K18 G6 AJ18 W25 W10 G18 AH18 W24 V10 H18 P25 M28 K27 U25 L32 AM28 AJ26 AF25 AE23 AN19 AH20 AF11 AM7 AH10 AF9 AJ17 AN16 F3 L9 K4 R4 N7 C7 K10 F9 C4 D16 G15 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 31 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF 1A 1C 3A 3C 4A 4C 6A 6C 7A 7C 8A 8C VREFB1AN0 VREFB1CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function VCCIO8A VCCIO8A VCCIO8A VCCIO8A VCCIO8C VCCIO8C VCCPD1A VCCPD1C VCCPD3A VCCPD3C VCCPD4A VCCPD4C VCCPD6A VCCPD6C VCCPD7A VCCPD7C VCCPD8A VCCPD8C VREFB1AN0 VREFB1CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel VREFB1AN0 VREFB1CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 Pin List F1152 F1152 Note(1), (2) L25 G24 F28 C28 G21 B19 N23 R23 AC23 AC19 AC13 AC17 P12 T12 M12 M16 M22 M18 M26 R26 AF26 AF20 AF10 AF15 M10 R10 J10 J15 J26 J20 D31 AK28 AK7 G7 AL30 AL29 AL6 AL5 AP9 AP10 AP11 AP24 AP25 AP26 AN10 AN11 AN20 AN25 AN26 AM9 AM10 AM11 AM12 AM19 AM23 AM24 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 32 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) AM25 AL10 AL11 AL12 AL13 AL17 AL19 AL22 AL23 AL24 AL25 AK11 AK13 AK17 AK19 AK22 AK23 AJ7 AJ12 AJ13 AJ19 AJ20 AJ22 AJ23 AJ24 AJ28 AH7 AH12 AH13 AH14 AH17 AH19 AH21 AH22 AH23 AH28 AG7 AG13 AG14 AG17 AG19 AG22 AG28 AF7 AF13 AF14 AF16 AF21 AF22 AF28 AE7 AE13 AE14 AE15 AE16 AE20 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 33 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) AE21 AE22 AE28 AD7 AD14 AD16 AD17 AD20 AD28 AC7 AC14 AC15 AC16 AC20 AC21 AC28 T24 T25 R7 R8 R9 R11 R12 R25 R28 P6 P7 P9 P10 P23 P24 P26 P27 P28 P30 N5 N6 N8 N9 N26 N27 N28 N29 N30 M3 M4 M5 M6 M7 M14 M15 M17 M20 M21 M29 M31 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 34 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) M32 L1 L3 L4 L6 L7 L15 L16 L21 L30 L31 L33 L34 K1 K2 K3 K13 K14 K15 K16 K17 K19 K21 K22 K31 K32 K33 K34 J1 J2 J3 J4 J7 J13 J14 J16 J19 J21 J22 J31 J32 J34 H1 H13 H16 H21 H22 H32 H33 H34 G1 G2 G5 G12 G13 G14 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 35 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCAUX VCCAUX VCCAUX VCCAUX Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 F1152 Note(1), (2) G17 G20 G22 G23 G33 G34 F1 F11 F12 F13 F14 F17 F18 F19 F20 F22 F23 F34 E12 E13 E19 E22 E24 E32 D10 D11 D12 D13 D17 D19 D22 D23 D24 D25 C10 C11 C17 C19 C23 C24 C25 C26 B9 B10 B24 B25 A9 A10 A11 A24 A25 A26 H27 AF27 AG8 J8 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Page 36 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF Pin Name/Function VCCA_L VCCA_L VCCA_R VCCA_R VCCH_GXBL0 VCCH_GXBL1 VCCH_GXBR0 VCCH_GXBR1 VCCL_GXBL0 VCCL_GXBL0 VCCL_GXBL1 VCCL_GXBL1 VCCL_GXBR0 VCCL_GXBR0 VCCL_GXBR1 VCCL_GXBR1 VCCR_L VCCR_L VCCR_R VCCR_R VCCT_L VCCT_L VCCT_R VCCT_R VCCHIP_L VCCHIP_L VCCHIP_L VCCHIP_R VCCHIP_R VCCHIP_R RREF_L0 RREF_R0 Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 Note(1), (2) V29 Y29 V6 Y6 AA28 U28 AA7 U7 Y27 AA26 V27 W28 AA9 Y8 W7 V8 U30 AA30 AA5 U5 W30 AB29 W5 AB6 W26 Y26 Y25 W9 Y10 Y9 AN34 AN1 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 DQS for X8/X9 for F1152 DQS for X16/X18 for F1152 Notes: 1. EP4SGX110, EP4SGX180, EP4SGX230, EP4SGX290, and EP4SGX360 devices have two variants in the F1152 package option—one with no PMA-only transceiver channels (Transceiver Count of ordering code: F) and the other with eight PMA-only transceiver channels (Transceiver Count of ordering code: H). 2. Stratix IV GX devices without PMA transceiver channels do not have vertical migration to or from devices with PMA transceiver channels. PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin List F1152 Page 37 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1A 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C 1C VREF VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1AN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function TDI TMS TRST TCK TDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function TDI TMS TRST TCK TDO RDN1A RUP1A CLKUSR DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 INIT_DONE CRC_ERROR DEV_OE Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFIO_TX_L1n DIFFIO_TX_L1p DIFFIO_RX_L1n DIFFIO_RX_L1p DIFFIO_TX_L2n DIFFIO_TX_L2p DIFFIO_RX_L2n DIFFIO_RX_L2p DIFFIO_TX_L3n DIFFIO_TX_L3p DIFFIO_RX_L3n DIFFIO_RX_L3p DIFFIO_TX_L4n DIFFIO_TX_L4p DIFFIO_RX_L4n DIFFIO_RX_L4p DIFFIO_TX_L5n DIFFIO_TX_L5p DIFFIO_RX_L5n DIFFIO_RX_L5p DIFFIO_TX_L6n DIFFIO_TX_L6p DIFFIO_RX_L6n DIFFIO_RX_L6p DIFFIO_TX_L7n DIFFIO_TX_L7p DIFFIO_RX_L7n DIFFIO_RX_L7p DIFFIO_TX_L8n DIFFIO_TX_L8p DIFFIO_RX_L8n DIFFIO_RX_L8p DIFFIO_TX_L9n DIFFIO_TX_L9p DIFFIO_RX_L9n DIFFIO_RX_L9p DIFFIO_TX_L10n DIFFIO_TX_L10p DIFFIO_RX_L10n DIFFIO_RX_L10p DIFFIO_TX_L11n DIFFIO_TX_L11p DIFFIO_RX_L11n DIFFIO_RX_L11p DIFFIO_TX_L12n DIFFIO_TX_L12p DIFFIO_RX_L12n DIFFIO_RX_L12p DIFFIO_TX_L13n DIFFIO_TX_L13p DIFFIO_RX_L13n DIFFOUT_L1n DIFFOUT_L1p DIFFOUT_L2n DIFFOUT_L2p DIFFOUT_L3n DIFFOUT_L3p DIFFOUT_L4n DIFFOUT_L4p DIFFOUT_L5n DIFFOUT_L5p DIFFOUT_L6n DIFFOUT_L6p DIFFOUT_L7n DIFFOUT_L7p DIFFOUT_L8n DIFFOUT_L8p DIFFOUT_L9n DIFFOUT_L9p DIFFOUT_L10n DIFFOUT_L10p DIFFOUT_L11n DIFFOUT_L11p DIFFOUT_L12n DIFFOUT_L12p DIFFOUT_L13n DIFFOUT_L13p DIFFOUT_L14n DIFFOUT_L14p DIFFOUT_L15n DIFFOUT_L15p DIFFOUT_L16n DIFFOUT_L16p DIFFOUT_L17n DIFFOUT_L17p DIFFOUT_L18n DIFFOUT_L18p DIFFOUT_L19n DIFFOUT_L19p DIFFOUT_L20n DIFFOUT_L20p DIFFOUT_L21n DIFFOUT_L21p DIFFOUT_L22n DIFFOUT_L22p DIFFOUT_L23n DIFFOUT_L23p DIFFOUT_L24n DIFFOUT_L24p DIFFOUT_L25n DIFFOUT_L25p DIFFOUT_L26n Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) B32 A33 C32 B34 B33 K24 L24 D29 C28 L23 M23 E29 D28 J26 K25 C30 C29 K27 K26 F29 F28 P24 P23 G29 G28 J25 H24 H27 G26 J27 H26 G27 F26 M24 N23 J30 H29 N26 N25 J29 J28 N27 M26 L27 L26 P26 R25 K30 L30 U25 T24 K29 K28 R24 R23 M30 Dynamic OCT Support No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) DQ1L DQ1L DQSn1L DQS1L DQ1L DQ1L DQSn2L DQS2L DQ2L DQ2L DQ2L DQ2L DQ3L DQ3L DQSn3L DQS3L DQ3L DQ3L DQSn4L DQS4L DQ4L DQ4L DQ4L DQ4L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ2L DQ2L DQ2L DQ2L/CQn2L DQ2L DQ2L DQSn2L/DQ2L DQS2L/CQ2L DQ2L DQ2L DQ2L DQ2L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L/CQn1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn1L/DQ1L DQS1L/CQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQ1L DQSn5L DQS5L DQ5L DQ5L DQ5L DQ5L DQ6L DQ6L DQSn6L DQS6L DQ6L DQ6L DQSn7L DQS7L DQ7L DQ7L DQ7L DQ5L DQ5L DQ5L DQ5L/CQn5L DQ5L DQ5L DQSn5L/DQ5L DQS5L/CQ5L DQ5L DQ5L DQ5L Page 38 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 1C 1C 1C 1C 1C 1C 1C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2C 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A VREF VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB1CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2CN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO CLK1n CLK1p CLK3p CLK3n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) PLL_L2_CLKOUT0n PLL_L2_FB_CLKOUT0p CLK0n CLK0p CLK1n CLK1p CLK3p CLK3n CLK2p CLK2n Configuration Function DEV_CLRn Dedicated Tx/Rx Channel DIFFIO_RX_L13p DIFFIO_TX_L14n DIFFIO_TX_L14p DIFFIO_RX_L14n DIFFIO_RX_L14p Emulated LVDS Output Channel DIFFOUT_L26p DIFFOUT_L27n DIFFOUT_L27p DIFFOUT_L28n DIFFOUT_L28p DIFFIO_RX_L15p DIFFIO_RX_L15n DIFFIO_TX_L15p DIFFIO_TX_L15n DIFFIO_RX_L16p DIFFIO_RX_L16n DIFFIO_TX_L16p DIFFIO_TX_L16n DIFFIO_RX_L17p DIFFIO_RX_L17n DIFFIO_TX_L17p DIFFIO_TX_L17n DIFFIO_RX_L18p DIFFIO_RX_L18n DIFFIO_TX_L18p DIFFIO_TX_L18n DIFFIO_RX_L19p DIFFIO_RX_L19n DIFFIO_TX_L19p DIFFIO_TX_L19n DIFFIO_RX_L20p DIFFIO_RX_L20n DIFFIO_TX_L20p DIFFIO_TX_L20n DIFFIO_RX_L21p DIFFIO_RX_L21n DIFFIO_TX_L21p DIFFIO_TX_L21n DIFFIO_RX_L22p DIFFIO_RX_L22n DIFFIO_TX_L22p DIFFIO_TX_L22n DIFFIO_RX_L23p DIFFIO_RX_L23n DIFFIO_TX_L23p DIFFIO_TX_L23n DIFFIO_RX_L24p DIFFIO_RX_L24n DIFFIO_TX_L24p DIFFIO_TX_L24n DIFFIO_RX_L25p DIFFIO_RX_L25n DIFFIO_TX_L25p DIFFIO_TX_L25n DIFFIO_RX_L26p DIFFIO_RX_L26n DIFFIO_TX_L26p DIFFOUT_L29p DIFFOUT_L29n DIFFOUT_L30p DIFFOUT_L30n DIFFOUT_L31p DIFFOUT_L31n DIFFOUT_L32p DIFFOUT_L32n DIFFOUT_L33p DIFFOUT_L33n DIFFOUT_L34p DIFFOUT_L34n DIFFOUT_L35p DIFFOUT_L35n DIFFOUT_L36p DIFFOUT_L36n DIFFOUT_L37p DIFFOUT_L37n DIFFOUT_L38p DIFFOUT_L38n DIFFOUT_L39p DIFFOUT_L39n DIFFOUT_L40p DIFFOUT_L40n DIFFOUT_L41p DIFFOUT_L41n DIFFOUT_L42p DIFFOUT_L42n DIFFOUT_L43p DIFFOUT_L43n DIFFOUT_L44p DIFFOUT_L44n DIFFOUT_L45p DIFFOUT_L45n DIFFOUT_L46p DIFFOUT_L46n DIFFOUT_L47p DIFFOUT_L47n DIFFOUT_L48p DIFFOUT_L48n DIFFOUT_L49p DIFFOUT_L49n DIFFOUT_L50p DIFFOUT_L50n DIFFOUT_L51p DIFFOUT_L51n DIFFOUT_L52p Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) L29 M29 M28 T26 U26 N29 N28 AA28 AA29 AC29 AB29 W24 V25 AB27 AC28 AA26 AA27 AD26 AE27 Y22 W23 AC26 AD27 Y23 Y24 AF28 AE29 AC25 AB26 AE28 AD29 AA24 Y25 AG29 AF29 AE23 AD24 AJ26 AK27 AG24 AF25 AH26 AJ27 AG23 AF24 AH28 AH29 AF26 AF27 AJ28 AJ29 AG26 AG27 AM29 AM30 AF23 Dynamic OCT Support Yes No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 (with PMA Transceiver) DQ7L DQS for X8/X9 for F1152 (with PMA Transceiver) DQ5L DQ8L DQ8L DQ8L DQ8L DQS8L DQSn8L DQ9L DQ9L DQS9L DQSn9L DQ9L DQ9L DQ10L DQ10L DQ10L DQ10L DQS10L DQSn10L DQ10L DQ10L DQ10L DQ10L DQS10L/CQ10L DQSn10L/DQ10L DQ10L DQ10L DQ10L/CQn10L DQ10L DQ10L DQ10L DQ11L DQ11L DQ11L DQ11L DQS11L DQSn11L DQ12L DQ12L DQS12L DQSn12L DQ12L DQ12L DQ13L DQ13L DQ13L DQ13L DQS13L DQSn13L DQ14L DQ13L DQ13L DQ13L DQ13L DQS13L/CQ13L DQSn13L/DQ13L DQ13L DQ13L DQ13L/CQn13L DQ13L DQ13L DQ13L DQ14L DQ14L DQ14L DQ14L DQS14L/CQ14L DQSn14L/DQ14L DQ14L DQS for X16/X18 for F1152 (with PMA Transceiver) DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQS14L/CQ14L DQSn14L/DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L DQ14L/CQn14L DQ14L DQ14L Page 39 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 2A 2A 2A 2A 2A 2A 2A 2A 2A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3C 3C VREF VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 VREFB2AN0 Pin Name/Function IO IO IO IO IO IO IO IO IO nCONFIG nSTATUS CONF_DONE PORSEL nCE VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3AN0 IO VREFB3CN0 IO VREFB3CN0 IO PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Optional Function(s) Configuration Function RUP2A RDN2A Dedicated Tx/Rx Channel DIFFIO_TX_L26n DIFFIO_RX_L27p DIFFIO_RX_L27n DIFFIO_TX_L27p DIFFIO_TX_L27n DIFFIO_RX_L28p DIFFIO_RX_L28n DIFFIO_TX_L28p DIFFIO_TX_L28n Emulated LVDS Output Channel DIFFOUT_L52n DIFFOUT_L53p DIFFOUT_L53n DIFFOUT_L54p DIFFOUT_L54n DIFFOUT_L55p DIFFOUT_L55n DIFFOUT_L56p DIFFOUT_L56n nCONFIG nSTATUS CONF_DONE nCE RDN3A RUP3A DIFFIO_RX_B1n DIFFIO_RX_B1p DIFFIO_RX_B2n DIFFIO_RX_B2p DIFFIO_RX_B3n DIFFIO_RX_B3p DIFFIO_RX_B4n DIFFIO_RX_B4p DIFFIO_RX_B5n DIFFIO_RX_B5p DIFFIO_RX_B6n DIFFIO_RX_B6p DIFFIO_RX_B7n DIFFIO_RX_B7p DIFFIO_RX_B8n DIFFIO_RX_B8p DIFFIO_RX_B9n DIFFIO_RX_B9p DIFFIO_RX_B10n DIFFIO_RX_B10p DIFFOUT_B1n DIFFOUT_B1p DIFFOUT_B2n DIFFOUT_B2p DIFFOUT_B3n DIFFOUT_B3p DIFFOUT_B4n DIFFOUT_B4p DIFFOUT_B5n DIFFOUT_B5p DIFFOUT_B6n DIFFOUT_B6p DIFFOUT_B7n DIFFOUT_B7p DIFFOUT_B8n DIFFOUT_B8p DIFFOUT_B9n DIFFOUT_B9p DIFFOUT_B10n DIFFOUT_B10p DIFFOUT_B11n DIFFOUT_B11p DIFFOUT_B12n DIFFOUT_B12p DIFFOUT_B13n DIFFOUT_B13p DIFFOUT_B14n DIFFOUT_B14p DIFFOUT_B15n DIFFOUT_B15p DIFFOUT_B16n DIFFOUT_B16p DIFFOUT_B17n DIFFOUT_B17p DIFFOUT_B18n DIFFOUT_B18p DIFFOUT_B19n DIFFOUT_B19p DIFFOUT_B20n DIFFOUT_B20p DIFFOUT_B21n DIFFOUT_B21p Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) AE24 AM28 AL29 AB23 AA23 AL28 AK29 AD23 AC24 AM34 AM33 AL32 AN33 AN34 AP31 AP29 AP30 AN30 AN29 AP28 AP27 AN27 AM26 AP25 AP26 AN26 AL26 AL27 AM25 AL25 AJ25 AH25 AK23 AJ23 AH24 AH23 AL24 AK24 AL22 AJ21 AM23 AL23 AH22 AJ22 AP24 AN24 AM22 AP22 AP23 AN23 AH20 AF20 AG21 AF21 AN21 AP21 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 (with PMA Transceiver) DQ14L DQS14L DQSn14L DQ14L DQ14L DQS for X8/X9 for F1152 (with PMA Transceiver) DQ14L DQ14L/CQn14L DQ14L DQ14L DQ14L DQS for X16/X18 for F1152 (with PMA Transceiver) DQ14L DQ14L DQ14L DQ14L DQ14L DQ1B DQ1B DQSn1B DQS1B DQ1B DQ1B DQSn2B DQS2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQSn3B DQS3B DQ3B DQ3B DQSn4B DQS4B DQ4B DQ4B DQ4B DQ4B DQ5B DQ5B DQSn5B DQS5B DQ5B DQ5B DQSn6B DQS6B DQ6B DQ6B DQ6B DQ6B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ2B DQ2B DQ2B DQ2B/CQn2B DQ2B DQ2B DQSn2B/DQ2B DQS2B/CQ2B DQ2B DQ2B DQ2B DQ2B DQ3B DQ3B DQ3B DQ3B/CQn3B DQ3B DQ3B DQSn3B/DQ3B DQS3B/CQ3B DQ3B DQ3B DQ3B DQ3B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B/CQn1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQSn1B/DQ1B DQS1B/CQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ7B DQ7B DQ7B DQ7B Page 40 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 3C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4C 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A VREF VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB3CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4CN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B11n DIFFIO_RX_B11p DIFFIO_RX_B12n DIFFIO_RX_B12p DIFFIO_RX_B13n DIFFIO_RX_B13p PLL_B1_CLKOUT4 PLL_B1_CLKOUT3 DIFFIO_RX_B14n DIFFIO_RX_B14p PLL_B1_CLKOUT0n PLL_B1_CLKOUT0p PLL_B1_FBn/CLKOUT2 PLL_B1_FBp/CLKOUT1 CLK5n CLK5p CLK4n CLK4p CLK6p CLK6n CLK7p CLK7n DIFFIO_RX_B15n DIFFIO_RX_B15p DIFFIO_RX_B16n DIFFIO_RX_B16p DIFFIO_RX_B17p DIFFIO_RX_B17n DIFFIO_RX_B18p DIFFIO_RX_B18n DIFFIO_RX_B19p DIFFIO_RX_B19n DIFFIO_RX_B20p DIFFIO_RX_B20n DIFFIO_RX_B21p DIFFIO_RX_B21n DIFFIO_RX_B22p DIFFIO_RX_B22n DIFFIO_RX_B23p DIFFIO_RX_B23n DIFFIO_RX_B24p DIFFIO_RX_B24n DIFFIO_RX_B25p DIFFIO_RX_B25n Emulated LVDS Output Channel DIFFOUT_B22n DIFFOUT_B22p DIFFOUT_B23n DIFFOUT_B23p DIFFOUT_B24n DIFFOUT_B24p DIFFOUT_B25n DIFFOUT_B25p DIFFOUT_B26n DIFFOUT_B26p DIFFOUT_B27n DIFFOUT_B27p DIFFOUT_B28n DIFFOUT_B28p DIFFOUT_B29n DIFFOUT_B29p DIFFOUT_B30n DIFFOUT_B30p DIFFOUT_B31n DIFFOUT_B31p DIFFOUT_B32n DIFFOUT_B32p DIFFOUT_B33p DIFFOUT_B33n DIFFOUT_B34p DIFFOUT_B34n DIFFOUT_B35p DIFFOUT_B35n DIFFOUT_B36p DIFFOUT_B36n DIFFOUT_B37p DIFFOUT_B37n DIFFOUT_B38p DIFFOUT_B38n DIFFOUT_B39p DIFFOUT_B39n DIFFOUT_B40p DIFFOUT_B40n DIFFOUT_B41p DIFFOUT_B41n DIFFOUT_B42p DIFFOUT_B42n DIFFOUT_B43p DIFFOUT_B43n DIFFOUT_B44p DIFFOUT_B44n DIFFOUT_B45p DIFFOUT_B45n DIFFOUT_B46p DIFFOUT_B46n DIFFOUT_B47p DIFFOUT_B47n DIFFOUT_B48p DIFFOUT_B48n DIFFOUT_B49p DIFFOUT_B49n Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) AL21 AK21 AM21 AM20 AL20 AK20 AJ20 AJ19 AM19 AL19 AC18 AD18 AF19 AE19 AF18 AE18 AM18 AL18 AP20 AN20 AP18 AN18 AN15 AP15 AN17 AP17 AE17 AF17 AH16 AJ15 AE16 AF16 AD17 AK17 AL16 AM16 AM17 AL17 AK15 AL15 AM14 AM15 AK14 AL14 AN14 AP14 AE15 AF15 AF14 AG15 AN12 AP12 AM13 AP13 AN11 AP11 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 (with PMA Transceiver) DQSn7B DQS7B DQ7B DQ7B DQSn8B DQS8B DQ8B DQ8B DQ8B DQ8B DQS for X8/X9 for F1152 (with PMA Transceiver) DQ7B DQ7B/CQn7B DQ7B DQ7B DQSn7B/DQ7B DQS7B/CQ7B DQ7B DQ7B DQ7B DQ7B DQ9B DQ9B DQS9B DQSn9B DQ9B DQ9B DQ10B DQ10B DQ10B DQ10B DQS10B DQSn10B DQ11B DQ11B DQS11B DQSn11B DQ11B DQ11B DQ11B DQ11B DQ11B DQ11B DQS11B/CQ11B DQSn11B/DQ11B DQ11B DQ11B DQ11B/CQn11B DQ11B DQ11B DQ11B DQ12B DQ12B DQ12B DQ12B DQS12B DQSn12B DQ15B DQ15B DQ15B DQ15B DQS15B/CQ15B DQSn15B/DQ15B DQS for X16/X18 for F1152 (with PMA Transceiver) Page 41 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 4A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A VREF VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB4AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO nIO_PULLUP nCEO DCLK nCSO ASDO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_B26p DIFFIO_RX_B26n DIFFIO_RX_B27p DIFFIO_RX_B27n DIFFIO_RX_B28p DIFFIO_RX_B28n DIFFIO_RX_B29p DIFFIO_RX_B29n DIFFIO_RX_B30p DIFFIO_RX_B30n DIFFIO_RX_B31p DIFFIO_RX_B31n RUP4A RDN4A DIFFIO_RX_B32p DIFFIO_RX_B32n Emulated LVDS Output Channel DIFFOUT_B50p DIFFOUT_B50n DIFFOUT_B51p DIFFOUT_B51n DIFFOUT_B52p DIFFOUT_B52n DIFFOUT_B53p DIFFOUT_B53n DIFFOUT_B54p DIFFOUT_B54n DIFFOUT_B55p DIFFOUT_B55n DIFFOUT_B56p DIFFOUT_B56n DIFFOUT_B57p DIFFOUT_B57n DIFFOUT_B58p DIFFOUT_B58n DIFFOUT_B59p DIFFOUT_B59n DIFFOUT_B60p DIFFOUT_B60n DIFFOUT_B61p DIFFOUT_B61n DIFFOUT_B62p DIFFOUT_B62n DIFFOUT_B63p DIFFOUT_B63n DIFFOUT_B64p DIFFOUT_B64n nIO_PULLUP nCEO DCLK nCSO ASDO RDN5A RUP5A DIFFIO_TX_R1n DIFFIO_TX_R1p DIFFIO_RX_R1n DIFFIO_RX_R1p DIFFIO_TX_R2n DIFFIO_TX_R2p DIFFIO_RX_R2n DIFFIO_RX_R2p DIFFIO_TX_R3n DIFFIO_TX_R3p DIFFIO_RX_R3n DIFFIO_RX_R3p DIFFIO_TX_R4n DIFFIO_TX_R4p DIFFIO_RX_R4n DIFFIO_RX_R4p DIFFIO_TX_R5n DIFFIO_TX_R5p DIFFIO_RX_R5n DIFFIO_RX_R5p DIFFIO_TX_R6n DIFFOUT_R1n DIFFOUT_R1p DIFFOUT_R2n DIFFOUT_R2p DIFFOUT_R3n DIFFOUT_R3p DIFFOUT_R4n DIFFOUT_R4p DIFFOUT_R5n DIFFOUT_R5p DIFFOUT_R6n DIFFOUT_R6p DIFFOUT_R7n DIFFOUT_R7p DIFFOUT_R8n DIFFOUT_R8p DIFFOUT_R9n DIFFOUT_R9p DIFFOUT_R10n DIFFOUT_R10p DIFFOUT_R11n Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) AJ12 AL13 AL11 AM11 AK12 AL12 AH13 AJ13 AH11 AH12 AH14 AJ14 AJ10 AK11 AL10 AM10 AL9 AL8 AN9 AP9 AM8 AP10 AN8 AP8 AN6 AP7 AN5 AP5 AP4 AP6 AN2 AL3 AM3 AM2 AM1 AC11 AC12 AL6 AM7 AB12 AA12 AM5 AM6 AF11 AE12 AL5 AK6 AE8 AF9 AH7 AJ8 AE9 AE10 AJ6 AJ7 AG12 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 (with PMA Transceiver) DQ13B DQ13B DQS13B DQSn13B DQ13B DQ13B DQ14B DQ14B DQ14B DQ14B DQS14B DQSn14B DQ15B DQ15B DQS15B DQSn15B DQ15B DQ15B DQ16B DQ16B DQ16B DQ16B DQS16B DQSn16B DQ17B DQ17B DQS17B DQSn17B DQ17B DQ17B DQS for X8/X9 for F1152 (with PMA Transceiver) DQ15B DQ15B DQ15B/CQn15B DQ15B DQ15B DQ15B DQ16B DQ16B DQ16B DQ16B DQS16B/CQ16B DQSn16B/DQ16B DQ16B DQ16B DQ16B/CQn16B DQ16B DQ16B DQ16B DQ17B DQ17B DQ17B DQ17B DQS17B/CQ17B DQSn17B/DQ17B DQ17B DQ17B DQ17B/CQn17B DQ17B DQ17B DQ17B DQS for X16/X18 for F1152 (with PMA Transceiver) DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQS17B/CQ17B DQSn17B/DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B/CQn17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ17B DQ1R DQ1R DQSn1R DQS1R DQ1R DQ1R DQSn2R DQS2R DQ2R DQ2R DQ2R DQ2R DQ3R DQ3R DQSn3R DQS3R DQ3R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R DQ1R DQ1R DQ1R DQ2R DQ2R DQ2R DQ2R/CQn2R DQ2R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R/CQn1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQSn1R/DQ1R DQS1R/CQ1R DQ1R Page 42 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5A 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 5C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C 6C VREF VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5AN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB5CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK8n CLK8p CLK10p CLK10n IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) CLK9n CLK9p CLK8n CLK8p CLK10p CLK10n CLK11p CLK11n PLL_R2_FB_CLKOUT0p PLL_R2_CLKOUT0n Configuration Function Dedicated Tx/Rx Channel DIFFIO_TX_R6p DIFFIO_RX_R6n DIFFIO_RX_R6p DIFFIO_TX_R7n DIFFIO_TX_R7p DIFFIO_RX_R7n DIFFIO_RX_R7p DIFFIO_TX_R8n DIFFIO_TX_R8p DIFFIO_RX_R8n DIFFIO_RX_R8p DIFFIO_TX_R9n DIFFIO_TX_R9p DIFFIO_RX_R9n DIFFIO_RX_R9p DIFFIO_TX_R10n DIFFIO_TX_R10p DIFFIO_RX_R10n DIFFIO_RX_R10p DIFFIO_TX_R11n DIFFIO_TX_R11p DIFFIO_RX_R11n DIFFIO_RX_R11p DIFFIO_TX_R12n DIFFIO_TX_R12p DIFFIO_RX_R12n DIFFIO_RX_R12p DIFFIO_TX_R13n DIFFIO_TX_R13p DIFFIO_RX_R13n DIFFIO_RX_R13p DIFFIO_TX_R14n DIFFIO_TX_R14p DIFFIO_RX_R14n DIFFIO_RX_R14p Emulated LVDS Output Channel DIFFOUT_R11p DIFFOUT_R12n DIFFOUT_R12p DIFFOUT_R13n DIFFOUT_R13p DIFFOUT_R14n DIFFOUT_R14p DIFFOUT_R15n DIFFOUT_R15p DIFFOUT_R16n DIFFOUT_R16p DIFFOUT_R17n DIFFOUT_R17p DIFFOUT_R18n DIFFOUT_R18p DIFFOUT_R19n DIFFOUT_R19p DIFFOUT_R20n DIFFOUT_R20p DIFFOUT_R21n DIFFOUT_R21p DIFFOUT_R22n DIFFOUT_R22p DIFFOUT_R23n DIFFOUT_R23p DIFFOUT_R24n DIFFOUT_R24p DIFFOUT_R25n DIFFOUT_R25p DIFFOUT_R26n DIFFOUT_R26p DIFFOUT_R27n DIFFOUT_R27p DIFFOUT_R28n DIFFOUT_R28p DIFFIO_RX_R15p DIFFIO_RX_R15n DIFFIO_TX_R15p DIFFIO_TX_R15n DIFFIO_RX_R16p DIFFIO_RX_R16n DIFFIO_TX_R16p DIFFIO_TX_R16n DIFFIO_RX_R17p DIFFIO_RX_R17n DIFFIO_TX_R17p DIFFIO_TX_R17n DIFFIO_RX_R18p DIFFIO_RX_R18n DIFFIO_TX_R18p DIFFIO_TX_R18n DIFFIO_RX_R19p DIFFOUT_R29p DIFFOUT_R29n DIFFOUT_R30p DIFFOUT_R30n DIFFOUT_R31p DIFFOUT_R31n DIFFOUT_R32p DIFFOUT_R32n DIFFOUT_R33p DIFFOUT_R33n DIFFOUT_R34p DIFFOUT_R34n DIFFOUT_R35p DIFFOUT_R35n DIFFOUT_R36p DIFFOUT_R36n DIFFOUT_R37p Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) AF12 AH8 AJ9 AF10 AG11 AL7 AK8 AD11 AD12 AG8 AG9 AB10 AB11 AE6 AF7 AB9 AC10 AG6 AF6 Y10 AA11 AD6 AE7 Y12 W12 AD8 AD9 AA8 AA9 AC7 AB8 V10 W11 AC6 AB6 AA6 AA7 N7 N6 M6 M5 T9 U9 M7 L6 R11 R10 J5 K5 T11 U10 K6 L5 R13 R12 L9 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 (with PMA Transceiver) DQ3R DQSn4R DQS4R DQ4R DQ4R DQ4R DQ4R DQS for X8/X9 for F1152 (with PMA Transceiver) DQ2R DQSn2R/DQ2R DQS2R/CQ2R DQ2R DQ2R DQ2R DQ2R DQSn5R DQS5R DQ5R DQ5R DQ5R DQ5R DQ6R DQ6R DQSn6R DQS6R DQ6R DQ6R DQSn7R DQS7R DQ7R DQ7R DQ7R DQ7R DQ5R DQ5R DQ5R DQ5R/CQn5R DQ5R DQ5R DQSn5R/DQ5R DQS5R/CQ5R DQ5R DQ5R DQ5R DQ5R DQ8R DQ8R DQ8R DQ8R DQS8R DQSn8R DQ9R DQ9R DQS9R DQSn9R DQ9R DQ9R DQ10R DQS for X16/X18 for F1152 (with PMA Transceiver) DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ1R DQ10R DQ10R DQ10R DQ10R DQS10R/CQ10R DQSn10R/DQ10R DQ10R DQ10R DQ10R/CQn10R DQ10R DQ10R DQ10R Page 43 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 6C 6C 6C 6C 6C 6C 6C 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 6A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A VREF VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6CN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB6AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO MSEL2 MSEL1 MSEL0 IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function RUP6A RDN6A Dedicated Tx/Rx Channel DIFFIO_RX_R19n DIFFIO_TX_R19p DIFFIO_TX_R19n DIFFIO_RX_R20p DIFFIO_RX_R20n DIFFIO_TX_R20p DIFFIO_TX_R20n DIFFIO_RX_R21p DIFFIO_RX_R21n DIFFIO_TX_R21p DIFFIO_TX_R21n DIFFIO_RX_R22p DIFFIO_RX_R22n DIFFIO_TX_R22p DIFFIO_TX_R22n DIFFIO_RX_R23p DIFFIO_RX_R23n DIFFIO_TX_R23p DIFFIO_TX_R23n DIFFIO_RX_R24p DIFFIO_RX_R24n DIFFIO_TX_R24p DIFFIO_TX_R24n DIFFIO_RX_R25p DIFFIO_RX_R25n DIFFIO_TX_R25p DIFFIO_TX_R25n DIFFIO_RX_R26p DIFFIO_RX_R26n DIFFIO_TX_R26p DIFFIO_TX_R26n DIFFIO_RX_R27p DIFFIO_RX_R27n DIFFIO_TX_R27p DIFFIO_TX_R27n DIFFIO_RX_R28p DIFFIO_RX_R28n DIFFIO_TX_R28p DIFFIO_TX_R28n Emulated LVDS Output Channel DIFFOUT_R37n DIFFOUT_R38p DIFFOUT_R38n DIFFOUT_R39p DIFFOUT_R39n DIFFOUT_R40p DIFFOUT_R40n DIFFOUT_R41p DIFFOUT_R41n DIFFOUT_R42p DIFFOUT_R42n DIFFOUT_R43p DIFFOUT_R43n DIFFOUT_R44p DIFFOUT_R44n DIFFOUT_R45p DIFFOUT_R45n DIFFOUT_R46p DIFFOUT_R46n DIFFOUT_R47p DIFFOUT_R47n DIFFOUT_R48p DIFFOUT_R48n DIFFOUT_R49p DIFFOUT_R49n DIFFOUT_R50p DIFFOUT_R50n DIFFOUT_R51p DIFFOUT_R51n DIFFOUT_R52p DIFFOUT_R52n DIFFOUT_R53p DIFFOUT_R53n DIFFOUT_R54p DIFFOUT_R54n DIFFOUT_R55p DIFFOUT_R55n DIFFOUT_R56p DIFFOUT_R56n MSEL2 MSEL1 MSEL0 RDN7A RUP7A DIFFIO_RX_T1n DIFFIO_RX_T1p DIFFIO_RX_T2n DIFFIO_RX_T2p DIFFIO_RX_T3n DIFFIO_RX_T3p DIFFOUT_T1n DIFFOUT_T1p DIFFOUT_T2n DIFFOUT_T2p DIFFOUT_T3n DIFFOUT_T3p DIFFOUT_T4n DIFFOUT_T4p DIFFOUT_T5n DIFFOUT_T5p DIFFOUT_T6n DIFFOUT_T6p DIFFOUT_T7n DIFFOUT_T7p Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) M8 N9 N8 L8 K7 N10 P9 J7 H6 L11 M10 F9 G8 H9 J8 G9 H8 H11 J10 G7 G6 P12 P11 F7 F6 J9 K8 C6 C5 K11 K10 D7 E6 M12 M11 C7 D6 N12 N11 B1 C3 B2 A6 A4 A5 B5 A7 B6 A8 B8 A10 C9 A9 B9 E8 D8 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 (with PMA Transceiver) DQ10R DQ10R DQ10R DQS10R DQSn10R DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) DQ11R DQ11R DQ11R DQ11R DQS11R DQSn11R DQ12R DQ12R DQS12R DQSn12R DQ12R DQ12R DQ13R DQ13R DQ13R DQ13R DQS13R DQSn13R DQ14R DQ14R DQS14R DQSn14R DQ14R DQ14R DQ13R DQ13R DQ13R DQ13R DQS13R/CQ13R DQSn13R/DQ13R DQ13R DQ13R DQ13R/CQn13R DQ13R DQ13R DQ13R DQ14R DQ14R DQ14R DQ14R DQS14R/CQ14R DQSn14R/DQ14R DQ14R DQ14R DQ14R/CQn14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQS14R/CQ14R DQSn14R/DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R/CQn14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ14R DQ1T DQ1T DQSn1T DQS1T DQ1T DQ1T DQSn2T DQS2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ2T DQ2T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T/CQn1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T Page 44 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7A 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 7C 8C 8C 8C 8C 8C 8C VREF VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7AN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB7CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T4n DIFFIO_RX_T4p DIFFIO_RX_T5n DIFFIO_RX_T5p DIFFIO_RX_T6n DIFFIO_RX_T6p DIFFIO_RX_T7n DIFFIO_RX_T7p DIFFIO_RX_T8n DIFFIO_RX_T8p DIFFIO_RX_T9n DIFFIO_RX_T9p DIFFIO_RX_T10n DIFFIO_RX_T10p DIFFIO_RX_T11n DIFFIO_RX_T11p DIFFIO_RX_T12n DIFFIO_RX_T12p DIFFIO_RX_T13n DIFFIO_RX_T13p DIFFIO_RX_T14n DIFFIO_RX_T14p DIFFIO_RX_T15n DIFFIO_RX_T15p CLK13n CLK13p CLK12n CLK12p CLK14p CLK14n CLK15p CLK15n PLL_T1_FBp/CLKOUT1 PLL_T1_FBn/CLKOUT2 DIFFIO_RX_T16n DIFFIO_RX_T16p DIFFIO_RX_T17p DIFFIO_RX_T17n DIFFIO_RX_T18p DIFFIO_RX_T18n Emulated LVDS Output Channel DIFFOUT_T8n DIFFOUT_T8p DIFFOUT_T9n DIFFOUT_T9p DIFFOUT_T10n DIFFOUT_T10p DIFFOUT_T11n DIFFOUT_T11p DIFFOUT_T12n DIFFOUT_T12p DIFFOUT_T13n DIFFOUT_T13p DIFFOUT_T14n DIFFOUT_T14p DIFFOUT_T15n DIFFOUT_T15p DIFFOUT_T16n DIFFOUT_T16p DIFFOUT_T17n DIFFOUT_T17p DIFFOUT_T18n DIFFOUT_T18p DIFFOUT_T19n DIFFOUT_T19p DIFFOUT_T20n DIFFOUT_T20p DIFFOUT_T21n DIFFOUT_T21p DIFFOUT_T22n DIFFOUT_T22p DIFFOUT_T23n DIFFOUT_T23p DIFFOUT_T24n DIFFOUT_T24p DIFFOUT_T25n DIFFOUT_T25p DIFFOUT_T26n DIFFOUT_T26p DIFFOUT_T27n DIFFOUT_T27p DIFFOUT_T28n DIFFOUT_T28p DIFFOUT_T29n DIFFOUT_T29p DIFFOUT_T30n DIFFOUT_T30p DIFFOUT_T31n DIFFOUT_T31p DIFFOUT_T32n DIFFOUT_T32p DIFFOUT_T33p DIFFOUT_T33n DIFFOUT_T34p DIFFOUT_T34n DIFFOUT_T35p DIFFOUT_T35n Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) C10 D10 F10 D9 G12 H12 F13 G13 F11 G11 C12 D12 D11 E11 D13 E12 A11 B11 A13 C13 A12 B12 F14 H14 H15 J15 A14 B14 D14 E14 C15 C14 D15 E15 D17 C17 C16 D16 E17 L17 J16 K16 F15 G16 J17 K17 A17 B17 A15 B15 B18 A18 B20 A20 D18 C18 Dynamic OCT Support Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQSn3T DQS3T DQ3T DQ3T DQSn4T DQS4T DQ4T DQ4T DQ4T DQ4T DQ5T DQ5T DQSn5T DQS5T DQ5T DQ5T DQSn6T DQS6T DQ6T DQ6T DQ6T DQ6T DQS for X8/X9 for F1152 (with PMA Transceiver) DQ2T DQ2T/CQn2T DQ2T DQ2T DQSn2T/DQ2T DQS2T/CQ2T DQ2T DQ2T DQ2T DQ2T DQ3T DQ3T DQ3T DQ3T/CQn3T DQ3T DQ3T DQSn3T/DQ3T DQS3T/CQ3T DQ3T DQ3T DQ3T DQ3T DQ7T DQ7T DQSn7T DQS7T DQ7T DQ7T DQSn8T DQS8T DQ8T DQ8T DQ8T DQ8T DQ9T DQ9T DQSn9T DQS9T DQ9T DQ9T DQ7T DQ7T DQ7T DQ7T/CQn7T DQ7T DQ7T DQSn7T/DQ7T DQS7T/CQ7T DQ7T DQ7T DQ7T DQ7T DQS for X16/X18 for F1152 (with PMA Transceiver) DQSn1T/DQ1T DQS1T/CQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T DQ1T Page 45 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8C 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A 8A VREF VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8CN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 VREFB8AN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) PLL_T1_CLKOUT0p PLL_T1_CLKOUT0n Configuration Function Dedicated Tx/Rx Channel DIFFIO_RX_T19p DIFFIO_RX_T19n PLL_T1_CLKOUT3 PLL_T1_CLKOUT4 DIFFIO_RX_T20p DIFFIO_RX_T20n DIFFIO_RX_T21p DIFFIO_RX_T21n DIFFIO_RX_T22p DIFFIO_RX_T22n DIFFIO_RX_T23p DIFFIO_RX_T23n DIFFIO_RX_T24p DIFFIO_RX_T24n DIFFIO_RX_T25p DIFFIO_RX_T25n DIFFIO_RX_T26p DIFFIO_RX_T26n DIFFIO_RX_T27p DIFFIO_RX_T27n DIFFIO_RX_T28p DIFFIO_RX_T28n DIFFIO_RX_T29p DIFFIO_RX_T29n DIFFIO_RX_T30p DIFFIO_RX_T30n DIFFIO_RX_T31p DIFFIO_RX_T31n RUP8A RDN8A DIFFIO_RX_T32p DIFFIO_RX_T32n Emulated LVDS Output Channel DIFFOUT_T36p DIFFOUT_T36n DIFFOUT_T37p DIFFOUT_T37n DIFFOUT_T38p DIFFOUT_T38n DIFFOUT_T39p DIFFOUT_T39n DIFFOUT_T40p DIFFOUT_T40n DIFFOUT_T41p DIFFOUT_T41n DIFFOUT_T42p DIFFOUT_T42n DIFFOUT_T43p DIFFOUT_T43n DIFFOUT_T44p DIFFOUT_T44n DIFFOUT_T45p DIFFOUT_T45n DIFFOUT_T46p DIFFOUT_T46n DIFFOUT_T47p DIFFOUT_T47n DIFFOUT_T48p DIFFOUT_T48n DIFFOUT_T49p DIFFOUT_T49n DIFFOUT_T50p DIFFOUT_T50n DIFFOUT_T51p DIFFOUT_T51n DIFFOUT_T52p DIFFOUT_T52n DIFFOUT_T53p DIFFOUT_T53n DIFFOUT_T54p DIFFOUT_T54n DIFFOUT_T55p DIFFOUT_T55n DIFFOUT_T56p DIFFOUT_T56n DIFFOUT_T57p DIFFOUT_T57n DIFFOUT_T58p DIFFOUT_T58n DIFFOUT_T59p DIFFOUT_T59n DIFFOUT_T60p DIFFOUT_T60n DIFFOUT_T61p DIFFOUT_T61n DIFFOUT_T62p DIFFOUT_T62n DIFFOUT_T63p DIFFOUT_T63n Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) K18 J18 K19 J19 L18 M18 D19 C19 F19 F20 E20 D20 C20 C21 E21 D21 A21 B21 J21 H21 J20 G20 B23 A23 A22 C22 B24 A24 F22 G22 D23 C23 F21 D22 E24 D24 G23 G24 F23 E23 G25 F25 D25 C25 D27 D26 B26 A26 A25 C26 B27 A27 A28 B29 B30 A30 Dynamic OCT Support No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQ10T DQ10T DQ10T DQ10T DQS10T DQSn10T DQ11T DQ11T DQS11T DQSn11T DQ11T DQ11T DQ11T DQ11T DQ11T DQ11T DQS11T/CQ11T DQSn11T/DQ11T DQ11T DQ11T DQ11T/CQn11T DQ11T DQ11T DQ11T DQ12T DQ12T DQ12T DQ12T DQS12T DQSn12T DQ13T DQ13T DQS13T DQSn13T DQ13T DQ13T DQ14T DQ14T DQ14T DQ14T DQS14T DQSn14T DQ15T DQ15T DQS15T DQSn15T DQ15T DQ15T DQ16T DQ16T DQ16T DQ16T DQS16T DQSn16T DQ17T DQ17T DQS17T DQSn17T DQ15T DQ15T DQ15T DQ15T DQS15T/CQ15T DQSn15T/DQ15T DQ15T DQ15T DQ15T/CQn15T DQ15T DQ15T DQ15T DQ16T DQ16T DQ16T DQ16T DQS16T/CQ16T DQSn16T/DQ16T DQ16T DQ16T DQ16T/CQn16T DQ16T DQ16T DQ16T DQ17T DQ17T DQ17T DQ17T DQS17T/CQ17T DQSn17T/DQ17T DQ17T DQ17T DQ17T/CQn17T DQ17T DQS for X16/X18 for F1152 (with PMA Transceiver) DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQS17T/CQ17T DQSn17T/DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T DQ17T/CQn17T DQ17T DQ17T DQ17T DQ17T DQ17T Page 46 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number 8A 8A QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL1 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QL0 QR0 QR0 QR0 QR0 QR0 QR0 VREF VREFB8AN0 VREFB8AN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function IO IO GXB_TX_L7n GXB_TX_L7p GXB_RX_L7n GXB_RX_L7p GXB_TX_L6n GXB_TX_L6p GXB_RX_L6n GXB_RX_L6p GXB_CMUTX_L3n GXB_CMUTX_L3p REFCLK_L3n,GXB_CMURX_L3n REFCLK_L3p,GXB_CMURX_L3p GXB_CMUTX_L2n GXB_CMUTX_L2p REFCLK_L2n,GXB_CMURX_L2n REFCLK_L2p,GXB_CMURX_L2p GXB_TX_L5n GXB_TX_L5p GXB_RX_L5n GXB_RX_L5p GXB_TX_L4n GXB_TX_L4p GXB_RX_L4n GXB_RX_L4p GXB_TX_L3n GXB_TX_L3p GXB_RX_L3n GXB_RX_L3p GXB_TX_L2n GXB_TX_L2p GXB_RX_L2n GXB_RX_L2p GXB_CMUTX_L1n GXB_CMUTX_L1p REFCLK_L1n,GXB_CMURX_L1n REFCLK_L1p,GXB_CMURX_L1p GXB_CMUTX_L0n GXB_CMUTX_L0p REFCLK_L0n,GXB_CMURX_L0n REFCLK_L0p,GXB_CMURX_L0p GXB_TX_L1n GXB_TX_L1p GXB_RX_L1n GXB_RX_L1p GXB_TX_L0n GXB_TX_L0p GXB_RX_L0n GXB_RX_L0p GXB_RX_R0p GXB_RX_R0n GXB_TX_R0p GXB_TX_R0n GXB_RX_R1p GXB_RX_R1n Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel DIFFOUT_T64p DIFFOUT_T64n Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) A29 A31 E32 E31 F34 F33 G32 G31 H34 H33 J32 J31 K34 K33 L32 L31 M34 M33 N32 N31 P34 P33 R32 R31 T34 T33 U32 U31 V34 V33 W32 W31 Y34 Y33 AA32 AA31 AB34 AB33 AC32 AC31 AD34 AD33 AE32 AE31 AF34 AF33 AG32 AG31 AH34 AH33 AH2 AH1 AG4 AG3 AF2 AF1 Dynamic OCT Support Yes Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQ17T DQ17T DQS for X8/X9 for F1152 (with PMA Transceiver) DQ17T DQ17T DQS for X16/X18 for F1152 (with PMA Transceiver) DQ17T DQ17T Page 47 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR0 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 QR1 VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GXB_TX_R1p GXB_TX_R1n REFCLK_R0p,GXB_CMURX_R0p REFCLK_R0n,GXB_CMURX_R0n GXB_CMUTX_R0p GXB_CMUTX_R0n REFCLK_R1p,GXB_CMURX_R1p REFCLK_R1n,GXB_CMURX_R1n GXB_CMUTX_R1p GXB_CMUTX_R1n GXB_RX_R2p GXB_RX_R2n GXB_TX_R2p GXB_TX_R2n GXB_RX_R3p GXB_RX_R3n GXB_TX_R3p GXB_TX_R3n GXB_RX_R4p GXB_RX_R4n GXB_TX_R4p GXB_TX_R4n GXB_RX_R5p GXB_RX_R5n GXB_TX_R5p GXB_TX_R5n REFCLK_R2p,GXB_CMURX_R2p REFCLK_R2n,GXB_CMURX_R2n GXB_CMUTX_R2p GXB_CMUTX_R2n REFCLK_R3p,GXB_CMURX_R3p REFCLK_R3n,GXB_CMURX_R3n GXB_CMUTX_R3p GXB_CMUTX_R3n GXB_RX_R6p GXB_RX_R6n GXB_TX_R6p GXB_TX_R6n GXB_RX_R7p GXB_RX_R7n GXB_TX_R7p GXB_TX_R7n GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) AE4 AE3 AD2 AD1 AC4 AC3 AB2 AB1 AA4 AA3 Y2 Y1 W4 W3 V2 V1 U4 U3 T2 T1 R4 R3 P2 P1 N4 N3 M2 M1 L4 L3 K2 K1 J4 J3 H2 H1 G4 G3 F2 F1 E4 E3 AN1 U18 AN4 AN7 AN10 AN13 AN16 AN19 AN22 AN25 AN28 AN31 AK4 AK7 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) Page 48 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) AK10 AK13 AK16 AK19 AK22 AK25 AK28 AK31 AG7 AG10 AG13 AG16 AG19 AG22 AG25 AG28 AD7 AD10 AD13 AD16 AD19 AD22 AD25 AD28 AB7 AB13 AB15 AB17 AB19 AB21 AB28 AA10 AA14 AA16 AA18 AA20 AA22 AA25 Y13 Y15 Y17 Y19 Y21 W10 W14 W16 W18 W20 W22 W25 V13 V15 V19 V21 U14 U16 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) Page 49 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) U20 U22 T10 T13 T15 T17 T19 T21 T25 R14 R16 R18 R20 R22 P10 P13 P15 P17 P19 P21 P25 N14 N16 N18 N20 N22 L7 L10 L13 L16 L19 L22 L25 L28 H7 H10 H13 H16 H19 H22 H25 H28 E7 E10 E13 E16 E19 E22 E25 E28 B4 B7 B10 B13 B16 B19 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) Page 50 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) B22 B25 B28 B31 C34 C33 D33 D32 D31 D30 E34 E33 V27 AL33 AL34 AK30 AK33 AJ30 AJ33 AJ34 AH30 AH31 AH32 AG30 AG33 AG34 AF30 AF31 AF32 AE30 AE33 AE34 AD30 AD31 AD32 AC33 AC34 AB30 AB31 AB32 AA33 AA34 Y28 Y29 Y30 Y31 Y32 W33 W34 V29 V30 V31 V32 U28 U29 U33 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) Page 51 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) U34 T30 T31 T32 R27 R29 R33 R34 P27 P28 P29 P30 P31 P32 N33 N34 M31 M32 L33 L34 K31 K32 J33 J34 H30 H31 H32 G30 G33 G34 F30 F31 F32 E30 AL1 C2 D5 D4 D3 D2 E5 E2 C1 AL2 AK2 AK5 AJ1 AJ2 AJ5 AH3 AH4 AH5 AG1 AG2 AG5 AF3 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) Page 52 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) AF4 AF5 AE1 AE2 AE5 AD3 AD4 AD5 AC1 AC2 AB3 AB4 AB5 AA1 AA2 Y3 Y4 Y5 Y6 Y7 W1 W2 V3 V4 V5 V6 V8 U1 U2 U6 U7 T3 T4 T5 R1 R2 R6 R8 P3 P4 P5 P6 P7 P8 N1 N2 M3 M4 L1 L2 K3 K4 J1 J2 H3 H4 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) Page 53 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function GND GND GND GND GND GND GND GND VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCPT VCCPT VCCPT VCCPT VCCPT VCCPT DNU VCCPGM Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) H5 G1 G2 G5 F3 F4 F5 E1 U17 AA17 AA21 Y14 Y16 Y18 W17 W19 W21 V14 V16 V18 V20 U15 U19 U21 T14 T16 T18 R17 R19 R21 P14 P18 AA15 AA19 Y20 W15 T20 R15 P16 P20 U27 Y27 W27 T27 W8 Y8 U8 T8 U23 V23 AH17 V12 U12 G17 V17 AK26 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) Page 54 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function VCCPGM TEMPDIODEn TEMPDIODEp VCC_CLKIN3C VCC_CLKIN4C VCC_CLKIN7C VCC_CLKIN8C VCCBAT VCCA_PLL_B1 VCCA_PLL_L2 VCCA_PLL_R2 VCCA_PLL_T1 VCCD_PLL_B1 VCCD_PLL_L2 VCCD_PLL_R2 VCCD_PLL_T1 VCCIO1A VCCIO1A VCCIO1A VCCIO1C VCCIO1C VCCIO2A VCCIO2A VCCIO2A VCCIO2C VCCIO2C VCCIO3A VCCIO3A VCCIO3A VCCIO3A VCCIO3C VCCIO3C VCCIO4A VCCIO4A VCCIO4A VCCIO4A VCCIO4C VCCIO4C VCCIO5A VCCIO5A VCCIO5A VCCIO5C VCCIO5C VCCIO6A VCCIO6A VCCIO6A VCCIO6C VCCIO6C VCCIO7A VCCIO7A VCCIO7A VCCIO7A VCCIO7C VCCIO7C VCCIO8A VCCIO8A Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) AH10 A3 B3 AJ18 AG17 H17 F18 E9 AH18 U24 V11 G18 AG18 V24 U11 H18 N24 J24 F27 T23 M27 AH27 AE26 AC23 AC27 AB24 AH21 AM24 AM27 AJ24 AK18 AP19 AH15 AM9 AM12 AJ11 AJ17 AP16 AH6 AH9 AE11 AC8 Y11 J6 J11 F8 T12 M9 C11 G15 F12 C8 A16 F17 C27 G21 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) Page 55 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF 1A 1C 2A 2C 3A 3C 4A 4C 5A 5C 6A 6C 7A 7C 8A 8C VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function VCCIO8A VCCIO8A VCCIO8C VCCIO8C VCCPD1A VCCPD1C VCCPD2A VCCPD2C VCCPD3A VCCPD3C VCCPD4A VCCPD4C VCCPD5A VCCPD5C VCCPD6A VCCPD6C VCCPD7A VCCPD7C VCCPD8A VCCPD8C VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel VREFB1AN0 VREFB1CN0 VREFB2AN0 VREFB2CN0 VREFB3AN0 VREFB3CN0 VREFB4AN0 VREFB4CN0 VREFB5AN0 VREFB5CN0 VREFB6AN0 VREFB6CN0 VREFB7AN0 VREFB7CN0 VREFB8AN0 VREFB8CN0 Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) F24 C24 A19 E18 P22 T22 AB22 V22 AB20 AB18 AB14 AB16 AA13 W13 N13 U13 N15 N17 N21 N19 M25 R26 AE25 AB25 AG20 AH19 AG14 AJ16 AF8 AC9 K9 R9 G14 F16 H20 G19 A32 AP33 AP2 A2 AJ31 AJ32 AJ3 AJ4 AP3 AP32 AN3 AN32 AM4 AM31 AM32 AL4 AL30 AL31 AK3 AK32 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) Page 56 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Name/Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCAUX VCCAUX VCCAUX VCCAUX VCCA_L VCCA_L Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel Pin List F1152 (PMA Tranceiver) F1152 Note(1), (2) (with PMA Transceiver) AF13 AE13 AE14 AE20 AE21 AE22 AD14 AD15 AD20 AD21 AC13 AC14 AC15 AC16 AC17 AC19 AC20 AC21 AC22 M13 M14 M15 M16 M17 M19 M20 M21 M22 L12 L14 L15 L20 L21 K12 K13 K14 K15 K20 K21 K22 K23 J12 J13 J14 J23 H23 E26 E27 C4 C31 J22 AF22 AK9 G10 AC30 U30 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) Page 57 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Bank Number VREF Pin Name/Function VCCA_R VCCA_R VCCH_GXBL0 VCCH_GXBL1 VCCH_GXBR0 VCCH_GXBR1 VCCL_GXBL0 VCCL_GXBL0 VCCL_GXBL1 VCCL_GXBL1 VCCL_GXBR0 VCCL_GXBR0 VCCL_GXBR1 VCCL_GXBR1 VCCR_L VCCR_L VCCR_R VCCR_R VCCT_L VCCT_L VCCT_R VCCT_R VCCHIP_L VCCHIP_L VCCHIP_L VCCHIP_R VCCHIP_R VCCHIP_R RREF_L0 RREF_L1 RREF_R0 RREF_R1 Optional Function(s) Configuration Function Dedicated Tx/Rx Channel Emulated LVDS Output Channel F1152 Note(1), (2) (with PMA Transceiver) AC5 U5 W29 T29 W6 T6 V28 W28 T28 R28 W7 V7 T7 R7 N30 W30 W5 N5 R30 AA30 R5 AA5 V26 Y26 W26 W9 Y9 V9 AK34 D34 AK1 D1 Dynamic OCT Support No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No DQS for X4 for F1152 (with PMA Transceiver) DQS for X8/X9 for F1152 (with PMA Transceiver) DQS for X16/X18 for F1152 (with PMA Transceiver) Notes: 1. EP4SGX110, EP4SGX180, EP4SGX230, EP4SGX290, and EP4SGX360 devices have two variants in the F1152 package option—one with no PMA-only transceiver channels (Transceiver Count of ordering code: F) and the other with eight PMA-only transceiver channels (Transceiver Count of ordering code: H). 2. Stratix IV GX devices without PMA transceiver channels do not have vertical migration to or from devices with PMA transceiver channels. PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin List F1152 (PMA Tranceiver) Page 58 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Notes (1), (2), (7) Pin Name Pin Type (1st and 2nd Function) Pin Description CLK[1,3,8,10]p CLK[1,3,8,10]n CLK[0,2,9,11]p CLK[0,2,9,11]n CLK[4:7,12:15]p CLK[4:7,12:15]n PLL_[L1,L4,R1,R4]_CLKp PLL_[L1,L4,R1,R4]_CLKn PLL_[L1, L2, L3, L4]_CLKOUT0n PLL_[R1, R2, R3, R4]_CLKOUT0n PLL_[L1, L2, L3, L4]_FB_CLKOUT0p PLL_[R1, R2, R3, R4]_FB_CLKOUT0p PLL_[T1,T2,B1,B2]_FBp/CLKOUT1 PLL_[T1,T2,B1,B2]_FBn/CLKOUT2 PLL_[T1,T2,B1,B2]_CLKOUT[3,4] PLL_[T1,T2,B1,B2]_CLKOUT0p PLL_[T1,T2,B1,B2]_CLKOUT0n Clock, Input Clock, Input I/O, Clock I/O, Clock I/O, Clock I/O, Clock Clock, Input Clock, Input I/O, Clock nIO_PULLUP Input TEMPDIODEp TEMPDIODEn MSEL[0:2] nCE nCONFIG Input Input Input Input Input CONF_DONE Bidirectional (open-drain) nCEO nSTATUS Output Bidirectional (open-drain) PORSEL Input nCSO ASDO DCLK Output Output Input (PS, FPP) Output (AS) Input Input Input Output Input TCK TMS TDI TDO TRST CRC_ERROR (Note 6) I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock I/O, Clock DEV_CLRn (Note 6) I/O, Output (open-drain) I/O, Input DEV_OE (Note 6) I/O, Input PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Clock and PLL Pins Dedicated high speed clock input pins 1, 3, 8, and 10 that can also be used for data inputs. OCT Rd is not supported on these pins. Dedicated negative clock input pins for differential clock input that can also be used for data inputs. OCT Rd is not supported on these pins. These pins can be used as I/O pins or clock input pins. OCT Rd is supported on these pins. These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is supported on these pins. These pins can be used as I/O pins or clock input pins. OCT Rd is not supported on these pins. These pins can be used as I/O pins or negative clock input pins for differential clock inputs. OCT Rd is not supported on these pins. Dedicated clock input pins to PLL L1, L4, R1, and R4 respectively. Dedicated negative clock input pins for differential clock input to PLL L1, L4, R1, and R4 respectively. Each left and right PLL supports 2 clock I/O pins, configured either as 2 single ended I/O or one differential I/O pair. When using both pins as single ended I/Os, PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin. Dual purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin. These pins can be used as I/O pins or two single-ended clock output pins. I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. Dedicated Configuration/JTAG Pins Dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose I/O pins (DATA[0:7], CLKUSR, INIT_DONE, DEV_OE, DEV_CLRn) are on or off before and during configuration. A logic high turns off the weak pull-up, while a logic low turns them on. Pin used in conjunction with the temperature sensing diode (bias-high input) inside the FPGA. Pin used in conjunction with the temperature sensing diode (bias-low input) inside the FPGA. Configuration input pins that set the FPGA device configuration scheme. Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Dedicated configuration control input. Pulling this pin low during user-mode will cause the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level will initiate reconfiguration. This is a dedicated configuration done pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. It is not available as a user I/O pin. Output that drives low when device configuration is complete. This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as a user I/O pin. Dedicated input which selects between a POR time of 12 ms or 100 ms. A logic high selects a POR time of 12 ms and a logic low selects POR time of 100 ms. Dedicated output control signal from the FPGA to the serial configuration device in AS mode that enables the configuration device. Control signal from the FPGA to the serial configuration device in AS mode used to read out configuration data. Dedicated configuration clock pin. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the FPGA. In AS mode, DCLK is an output from the FPGA that provides timing for the configuration interface. Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG input pin. Dedicated JTAG output pin. Dedicated active low JTAG input pin. TRST is used to asynchronously reset the JTAG boundary-scan circuit. Optional/Dual-Purpose Configuration Pins Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled. Optional pin that allows designers to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high (VCCPGM), all registers behave as programmed. Optional pin that allows designers to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high (VCCPGM), all I/O pins behave as defined in the design. Pin Definitions Page 59 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Notes (1), (2), (7) Pin Name DATA0 (Note 6) DATA[1:7] (Note 6) INIT_DONE (Note 6) Pin Type (1st and 2nd Function) Pin Description I/O, Input Dual-purpose configuration data input pin. The DATA0 pin can be used for bit-wide configuration or as an I/O pin after configuration is complete. I/O, Input Dual-purpose configuration input data pins. The DATA[1:7] pins can be used for byte-wide configuration or as regular I/O pins. These pins can also be used as user I/O pins after configuration. I/O, Output This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when (open-drain) the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration. CLKUSR (Note 6) I/O, Input DIFFIO_RX[##]p, DIFFIO_RX[##]n DIFFIO_TX[##]p, DIFFIO_TX[##]n DIFFOUT_[##]p, DIFFOUT_[##]n I/O, RX channel DQS[1:38][T,B], DQS[1:34][L,R] I/O,DQS DQSn[1:38][T,B], DQSn[1:34][L,R] I/O,DQSn Optional complementary data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. DQ[1:38][T,B], DQ[1:34][L,R] I/O,DQ CQ[1:38][T,B], CQ[1:34][L,R] DQS Optional data signal for use in external memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list. Optional data strobe signal for use in QDR II SRAM. These are the pins for echo clocks. CQn[1:38][T,B], CQn[1:34][L,R] DQS Optional complementary data strobe signal for use in QDR II SRAM. These are the pins for echo clocks. RUP[1:8]A, RUP[3,8]C RDN[1:8]A, RDN[3,8]C DNU NC I/O, Input VCC VCCD_PLL_[L,R][1:4], VCCD_PLL_[T,B][1:2] VCCPT VCCA_PLL_[L,R][1:4], VCCA_PLL_[T,B][1:2] VCCAUX VCCIO[1:8][A,C], VCCIO[2,3,4,5,7,8]B Power Power PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. I/O, TX channel I/O, TX channel I/O, Input Do Not Use No Connect Power Power Power Power Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin. Differential I/O Pins These are true LVDS receiver channels on side and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. These are true LVDS transmitter channels on side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. These are emulated LVDS output channels. On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os, including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. External Memory Interface Pins Optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic. Reference Pins Reference pins for I/O banks. The RUP pins share the same VCCIO with the I/O bank where they are located. The external precision resistor RUP must be connected to the designated RUP pin within the bank. If not required, this pin is a regular I/O pin. Reference pins for I/O banks. The RDN pins share the same GND with the I/O bank where they are located. The external precision resistor RDN must be connected to the designated RDN pin within the bank. If not required, this pin is a regular I/O pin. Do not connect to power or ground or any other signal; must be left floating. Do not drive signals into these pins. Supply Pins VCC supplies power to the core and periphery. Digital power for PLL[L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in datasheet, even if the PLL is not used. Power supply for the programmable power technology. Analog power for PLL [L[1:4],R[1:4],T[1:2],B[1:2]]. The designer must connect these pins to the voltage level that recommended in datasheet, even if the PLL is not used. It is advised to keep this pin isolated from other VCC for better jitter performance. Auxiliary supply for the programmable power technology. These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all LVDS, LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), HSTL(12, 15, 18), SSTL(15, 18, 2), 3.0 V PCI/PCI-X I/O as well as LVTTL 3.3 V I/O standards. VCCIO also supplies power to the input buffers used for LVCMOS(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V), 3.0 V PCI/PCI-X and LVTTL 3.3 V I/O standards. Pin Definitions Page 60 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Notes (1), (2), (7) Pin Name VCCPGM VCCPD[1:8][A,C], VCCPD[2,3,4,5,7,8]B VCC_CLKIN[3,4,7,8]C VCCBAT GND VREFB[1:8][A,C]N0, VREFB[2,3,4,5,7,8]BN0 Pin Type (1st and 2nd Function) Pin Description Configuration pins power supply. Power Dedicated power pins. This supply is used to power the I/O pre-drivers. Power Power Power Ground Power Differential clock input power supply for top and bottom I/O banks. Battery back-up power supply for design security volatile key register. Device ground pins. Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-reference pins for the bank. Transceiver (I/O Banks) Pins VCCHIP_[L,R] Power PCIe Hard IP digital power supply, specific to the left (L) side or right (R) side of the device. VCCR_[L,R] Power Analog power, receiver, specific to the left (L) side or right (R) side of the device. VCCT_[L,R] Power Analog power, transmitter, specific to the left (L) side or right (R) side of the device. VCCL_GXB[L,R][0:3] Power Analog power, block level clock distribution. VCCH_GXB[L,R][0:3] Power Analog power, block level TX buffers. VCCA_[L,R] Power Analog power, TX driver, RX receiver, CDR, specific to the left (L) side or right (R) side of the device. GXB_RX_[L,R][0:15]p (Note 3) Input High speed positive differential receiver channels. Specific to the left (L) side or right (R) side of the device. GXB_RX_[L,R][0:15]n (Note 3) Input High speed negative differential receiver channels. Specific to the left (L) side or right (R) side of the device. GXB_TX_[L,R][0:15]p (Note 3) Output High speed positive differential transmitter channels. Specific to the left (L) side or right (R) side of the device. GXB_TX_[L,R][0:15]n (Note 3) Output High speed negative differential transmitter channels. Specific to the left (L) side or right (R) side of the device. REFCLK_[L,R][0:7]p Input High speed differential reference clock positive, or CMU receiver channels, specific to the left (L) side or right (R) side of the device. GXB_CMURX_[L,R][0:7]p (Note 4 and 5) REFCLK_[L,R][0:7]n Input High speed differential reference clock complement, or CMU complementary receiver channel, specific to the left (L) side or right (R) side of the device. GXB_CMURX_[L,R][0:7]n (Note 4 and 5) GXB_CMUTX_[L,R][0:7]p (Note 5) Output CMU transmitter channels, specific to the left (L) side or right (R) side of the device. GXB_CMUTX_[L,R][0:7]n RREF_[L,R][0:1] Input Reference resistor for transceiver, specific to the left (L) side or right (R) side of the device. Notes: 1. This pin definition is prepared based on the EP4SGX530. 2. Some of the pull-up /pull-down resisitors mentioned in the table above may not be required, depending on the exact device configuration scheme. The ability to NC or short them may be valuable during the debug phase, should you be required to use a different configuration scheme. Refer to the Configuring Stratix IV GX Devices chapter in the Stratix IV GX Device Handbook for more information. 3. Transceiver signals GXB_RX[0:15] and GXB_TX[0:15] are device specific. 4. Dual purpose CMU Receiver channels. Can be used either as reference clock or CMU receiver channels in devices with 5th and 6th channels. 5. Only available in package with 5th and 6th channels. 6. These dual purpose configuration pins can only be used as configuration pins but not regular I/O in F780 of EP4SGX360 and EP4SGX290. 7. Refer to Pin Connections Guidelines and datasheet for the recommended operating voltage. PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Pin Definitions Page 61 of 63 VREFB8AN0 VREFB8CN0 7C 7A VREFB7CN0 VREFB7AN0 6C 3C VREFB3AN0 VREFB3CN0 PLL_B1 4C 4A VREFB4CN0 VREFB4AN0 Transceiver Block (QR0) 5A 3A VREFB5AN0 VREFB5CN0 2C 5C PLL_R2 2A VREFB2AN0 VREFB2CN0 Transceiver Block (QL0) PLL_L2 Transceiver Block (QR1) PLL_T1 VREFB6CN0 VREFB6AN0 8C 6A 1A 8A 1C VREFB1CN0 VREFB1AN0 Transceiver Block (QL1) Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Note: 1. This is only a pictorial representation to provide an idea of placement on the device. Refer to the pin list and the Quartus® II software for exact locations. PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Bank & PLL Diagram Page 62 of 63 Pin Information for the Stratix® IV GX EP4SGX110 Device Version 1.4 Version Number 1.0 1.1 1.2 Date 9/29/2008 12/30/2008 6/9/2009 1.3 12/3/2009 1.4 2/4/2015 PT-EP4SGX110-1.4 Copyright © 2015 Altera Corp. Changes Made Initial release. Updated VCCBAT from 2.5 V to 3.0 V. Added F1152 (with PMA Transceiver) package and removed recommended operating voltage in pin definition. Added bank number for JTAG pins. Updated Note (1) in Pin List. Grouped nCSO, ASDO, and DCLK into dedicated configuration/JTAG pins in Pin Definitions. Added the Dynamic OCT Support columns in Pin List F780, Pin List F1152, and Pin List F1152 (with PMA Transceiver). Revision History Page 63 of 63