ATD250HVI

POSEICO SPA
Via Pillea 42-44, 16153 Genova - ITALY
Tel. + 39 010 8599400 - Fax + 39 010 8682006
Sales Office:
Tel. + 39 010 8599400 - Fax + 39 010 8681180
POSEICO
POSEICO SPA
POwer SEmiconductors Italian COrporation
PHASE CONTROL MODULE
*Full ermetic packaging
*Industrial compatible packaging
*Insulation using Aln substrate
*New G-K auxiliary output arrangement
*Contact screws avaliable on request
ATD250HVI
Repetitive voltage up to
Mean on-state current
Surge current
4500 V
250 A
6 kA
TARGET SPECIFICATION
gen 04 - ISSUE : 0
Symbol
Characteristic
Tj
[°C]
Conditions
Value
Unit
BLOCKING
V
RRM / DRM
Repetitive peak reverse/off-state voltage
125
4500
V
RSM
Non-repetitive peak reverse voltage
125
4600
V
I
RRM / DRM
Repetitive peak reverse/off-state current
125
75
mA
I
T (AV)
Mean on-state current
250
A
I
T (AV)
Mean on-state current
180° sin. 50Hz, Tc=55°C
I
TSM
Surge on-state current
sine wave, 10 ms
V
CONDUCTING
180° sin, 50Hz, Tc=85°C
370
A
125
5,9
kA
174 x1E3
A²s
25
3,338
I² t
I² t
without reverse voltage
V
T
On-state voltage
On-state current =
V
T(TO)
Threshold voltage
125
1,35
V
T
On-state slope resistance
125
1,335
mohm
r
1600 A
V
SWITCHING
di/dt
Critical rate of rise of on-state current, min.
From 75% VDRM up to 1050 A, gate 10V 5ohm
125
200
A/µs
dv/dt
Critical rate of rise of off-state voltage, min.
Linear ramp up to 70% of VDRM
125
500
V/µs
td
Gate controlled delay time, typical
VD=100V, gate source 25V, 10 ohm , tr=.5 µs
25
1,6
µs
tq
Circuit commutated turn-off time, typical
dV/dt = 20 V/µs linear up to 75% VDRM
320
µs
Q rr
Reverse recovery charge
di/dt=-20 A/µs, I= 700 A
I rr
Peak reverse recovery current
VR= 50 V
125
µC
I
H
Holding current, typical
VD=5V, gate open circuit
25
300
mA
I
L
Latching current, typical
VD=5V, tp=30µs
25
700
mA
25
3,5
V
mA
A
GATE
V
GT
Gate trigger voltage
VD=5V
I
GT
Gate trigger current
VD=5V
25
200
V
GD
Non-trigger gate voltage, min.
VD=VDRM
125
0,25
V
V
FGM
Peak gate voltage (forward)
30
V
I
FGM
Peak gate current
10
A
V
RGM
Peak gate voltage (reverse)
5
V
P
GM
Peak gate power dissipation
150
W
P
G
Average gate power dissipation
2
W
Pulse width 100 µs
MOUNTING
R
th(j-c)
Thermal impedance
Junction to case, per element
R
th(c-h)
Thermal impedance
Case to heatsink, per element
T
j
Operating junction temperature
V
ins
RMS insulation voltage
50Hz, circuit to base,all terminal shorted
Mounting tourque
Case to heatsink
Busbars to terminals
T
Mass
ORDERING INFORMATION : ATD250HVI S 45
standard specification
VDRM&VRRM/100
25
70
°C/kW
20
°C/kW
-30 / 125
°C
6000
V
4 to 6
12 to 18
1500
Nm
Nm
g
ATD250HVI PHASE CONTROL MODULE
TARGET SPECIFICATION
POSEICO
POSEICO SPA
POwer SEmiconductors Italian COrporation
gen 04 - ISSUE : 0
SURGE CHARACTERISTIC
Tj = 125 °C
800
7
700
6
600
5
500
ITSM [kA]
On-state Current [A]
ON-STATE CHARACTERISTIC
Tj = 125 °C
400
300
4
3
2
200
1
100
0
0
0
1
2
3
1
10
n°cycles
On-state Voltage [V]
TRANSIENT THERMAL IMPEDANCE
80,0
70,0
Zth j-c [°C/kW]
60,0
50,0
40,0
30,0
20,0
10,0
0,0
0,001
0,01
0,1
1
10
t[s]
Distributed by
All the characteristics given in this data sheet are guaranteed only with uniform
clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm
and roughness < 2 µm.
In the interest of product improvement POSEICO SPA reserves the right to change
any data given in this data sheet at any time without previous notice.
If not stated otherwise the maximum value of ratings (simbols over shaded
background) and characteristics is reported.
100