POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation PHASE CONTROL THYRISTOR POSEICO SPA Via N. Lorenzi 8, 16152 Genova - ITALY Tel. +39 010 6556234 - Fax +39 010 6557519 Sales Office: Tel. +39 010 6556775 - Fax +39 010 6442510 AT738LT Repetitive voltage up to Mean on-state current Surge current 2200 V 4050 A 60 kA FINAL SPECIFICATION apr 97 - ISSUE : 01 Symbol Characteristic Tj [°C] Conditions Value Unit BLOCKING V RRM Repetitive peak reverse voltage 125 2200 V V RSM Non-repetitive peak reverse voltage 125 2300 V V DRM Repetitive peak off-state voltage 125 2200 V I RRM Repetitive peak reverse current V=VRRM 125 200 mA I DRM Repetitive peak off-state current V=VDRM 125 200 mA A CONDUCTING I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, double side cooled 4050 I T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, double side cooled 3250 A I TSM Surge on-state current sine wave, 10 ms 60 kA 125 I² t I² t without reverse voltage V T On-state voltage On-state current = V T(TO) Threshold voltage 125 0,92 T On-state slope resistance 125 0,090 mohm From 75% VDRM up to 3000 A, gate 10V 5ohm 125 200 A/µs V/µs r 2000 A 18000 x1E3 25 1,1 A²s V V SWITCHING di/dt Critical rate of rise of on-state current, min. dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 75% of VDRM 125 500 td Gate controlled delay time, typical VD=100V, gate source 25V, 10 ohm , tr=.5 µs 25 3 tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 80% VDRM Q rr Reverse recovery charge di/dt=-20 A/µs, I= 2000 A 320 125 µs µs µC I rr Peak reverse recovery current VR= 50 V I H Holding current, typical VD=5V, gate open circuit 25 300 mA A I L Latching current, typical VD=5V, tp=30µs 25 700 mA GATE V GT Gate trigger voltage VD=5V 25 3,5 V I GT Gate trigger current VD=5V 25 350 mA VD=VDRM 125 V GD Non-trigger gate voltage, min. 0,25 V V FGM Peak gate voltage (forward) 30 V I FGM Peak gate current 10 A V RGM Peak gate voltage (reverse) P GM Peak gate power dissipation P G Average gate power dissipation R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled R th(c-h) Thermal impedance Case to heatsink, double side cooled T F j Operating junction temperature Mounting force Mass Pulse width 100 µs 5 V 150 W 2 W MOUNTING ORDERING INFORMATION : AT738LT S 22 standard specification VDRM&VRRM/100 9,5 °C/kW 2 °C/kW -30 / 125 40.0 / 50.0 1150 °C kN g AT738LT PHASE CONTROL THYRISTOR FINAL SPECIFICATION POSEICO POSEICO SPA POwer SEmiconductors Italian COrporation apr 97 - ISSUE : 01 SURGE CHARACTERISTIC Tj = 125 °C 14000 70 12000 60 10000 50 8000 40 ITSM [kA] On-state Current [A] ON-STATE CHARACTERISTIC Tj = 125 °C 6000 30 4000 20 2000 10 0 0,6 1,1 0 1,6 1 10 On-state Voltage [V] n° cycles TRANSIENT THERMAL IMPEDANCE DOUBLE SIDE COOLED 10,0 9,0 8,0 Zth j-h [°C/kW] 7,0 6,0 5,0 4,0 3,0 2,0 1,0 0,0 0,001 0,01 0,1 1 t[s] 10 100 Cathode terminal type DIN 46244 - A 4.8 - 0.8 Gate terminal type AMP 60598 - 1 Distributed by All the characteristics given in this data sheet are guaranteed only with uniform clamping force, cleaned and lubricated heatsink, surfaces with flatness < .03 mm and roughness < 2 µm. In the interest of product improvement POSEICO S.p.A reserves the right to change any data given in this data sheet at any time without previous notice. If not stated otherwise the maximum value of ratings (simbols over shaded background) and characteristics is reported. 100