Errata: CS4361 Rev A0 Silicon Reference CS4361 Data Sheet DS672A2 dated January '05 ! The analog THD+N performance, at 0 dBFS input, varies from channel to channel and decreases at higher temperatures and higher VA voltages. At +5 V VA supply and 25° C THD+N is typically -87 dB on the worst channel. Adding the recommended 130 kΩ resistor (See Figure 1.) from the FILT+ pin to GND improves the typical THD+N to -90 dB on the worst channel. The minimum guaranteed THD+N across all channels, temperature and voltage using the recommended resistor is -78 dB. Figures 2 through 4 show the channel variance, voltage and temperature drift when using the recommended resistor on FILT+. FILT+ 10 + 130 k 33 µF Figure 1. Recommended Resistor on FILT+ ! The MUTEC mute control pin goes active after only 512 LRCK periods of static zero data. ! Operation at +3.3 V is not offered for this revision. The Specified Operating Conditions are as follows Parameters DC Power Supply Specified Temperature Range -CZZ Symbol Min Nom Max Units VA TA 4.75 -10 5.0 - 5.25 +70 V °C ! The Popguard® ramp-down function will occur if either MCLK is removed or RST is asserted. See Figure 5 for details. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to http://www.cirrus.com/corporate/contacts/sales.cfm http://www.cirrus.com Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) ER672A2 DECEMBER '05 1 kHz THD+N, 0 dBFS, VA = 5 V, 20°C 96 95 94 dB 93 92 91 90 89 88 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Figure 2. Typical Channel-to-channel Variance with Recommended Resistor on FILT+ 1 kHz THD+N, 0 dBFS, VA=5 V 94 93 92 dB 91 90 89 88 87 86 20 30 40 50 60 70 °C Figure 3. Typical Variance Over Temperature with Recommended Resistor on FILT+ 1 kHz THD+N, 0 dBFS, 25°C 95 94 dB 93 92 91 90 4.75 5 5.25 VA Figure 4. Typical Variance Over Voltage with Recommended Resistor on FILT+ 2 ER672A2 USER: Apply Power VQ and outputs ramp down Power-Down State VQ and outputs ramp down VQ and outputs low USER: Apply MCLK, release RST USER: Apply RST or remove MCLK USER: Apply RST or remove MCLK VQ and outputs ramp up USER: Remove LRCK USER: Remove LRCK Wait State USER: Apply LRCK and MCLK USER: change MCLK/LRCK ratio MCLK/LRCK Ratio Detection USER: change MCLK/LRCK ratio USER: No SCLK USER: Applied SCLK SCLK mode = internal SCLK mode = external Normal Operation De-emphasis available Normal Operation De-emphasis not available Analog Output is Generated Analog Output is Generated Figure 5. CS4361 Rev A0 Initialization and Power-Down Sequence ER672A2 3