APW7190 5V or 12V Single Output PWM Controller with PFM Features General Description • The APW7190 is a single-phase, constant-on-time, synchronous PWM controller, which drives N-channel MOS- Operating with Single 5~12V Supply Voltage or Two Supply Voltages • FETs. The APW7190 allows wide input voltage that is either a single 5~12V or two supply voltage(s) for various ±0.6% 0.5V Reference - Over Line, Load Regulation, and Operating Temp. • applications. An internal 0.5V temperature-compensated reference voltage with high accuracy is designed to meet Drive Dual Low Cost N-Channel MOSFETs the requirement of low output voltage applications. The PWM controller operates fixed 300kHz pseudo-con- - Adaptive Shoot-Through Protection • Power-On-Reset Monitoring on VCC Pin • High Efficiency at Light Load • Constant-On-Time Control Scheme stant frequency PWM with an adaptive constant-on-time control. The device provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode. In Pulse Frequency Mode (PFM), the APW7190 provides very high efficiency over light to heavy loads with loading-modulated switching frequencies. The device - Switching Frequency Compensation for PWM Operation • 300kHz Constant Switching Frequency • Integrated MOSFET Drivers and Bootstrap Diode • Internal Integrated Soft-Start • Built-In Ultrasonic Mode Control Scheme with PFM • Adaptive Dead-Time Control • Power Good Monitoring • 70% Under-Voltage Protection • 125% Pre-Over-Voltage and Over-Voltage works in ultrasonic mode with PFM at no load. The unique ultrasonic mode maintains the switching frequency above 20kHz, which eliminates noise in audio applications. The APW7190 is equipped with accurate current-limit, output under-voltage, and output over-voltage protections. A Power-On-Reset function monitors the voltage on VCC to prevent wrong operation during power-on. The APW7190 has a 4ms digital soft-start to ramp up the output voltage with programmable slew rate to reduce the start-up current. A soft-stop function actively discharges the output capacitors with controlled reverse inductor current. Protection • The APW7190 is available in TDFN3x3-10 package. Adjustable Current-Limit Protection - Using Low-Side MOSFET’s RDS(ON) • Over-Temperature Protection Applications • 3mmx3mm TDFN-10 (TDFN3x3-10) Package • Mother Board • Lead Free and Green Devices Available • Low Cost PC (RoHS Compliant) • 5V or 12V-Input DC/DC Regulators ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 1 www.anpec.com.tw APW7190 Simplified Application Circuit VCC=5Vor 12V VIN EN/EXTREF Q1 UGATE LOUT VOUT PHASE POK LGATE/OCSET Q2 COUT ROCSET APW7190 Pin Configuration BOOT 1 UGATE 2 PHASE 3 GND 4 LGATE/OCSET 5 10 9 8 7 6 EN/EXTREF POK VOUT FB VCC TDFN3x3-10 Top View = Thermal Pad (connected to the GND plane for better heat dissipation) Ordering and Marking Information Package Code QB : TDFN3x3-10 Temperature Range I : -40 to 85 °C Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7190 Assembly Material Handling Code Temperature Range Package Code APW7190 QB : APW 7190 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 2 www.anpec.com.tw APW7190 Absolute Maximum Ratings Symbol VCC VBOOT-GND VBOOT (Note 1) Parameter Rating VCC Supply Voltage (VCC to GND) -0.3 ~ 16 V BOOT Supply Voltage (BOOT to GND ) -0.3 ~ 30 V BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 16 V FB, EN/EXTREF and VOUT to GND -0.3 ~ 7 V -0.3 ~ VCC+0.3 V UGATE Voltage (UGATE to PHASE) <400ns pulse width >400ns pulse width -5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 V LGATE/OCSET Voltage (LGATE to GND) <400ns pulse width >400ns pulse width -5 ~ VCC+0.3 -0.3 ~ VCC+0.3 V PHASE Voltage (PHASE to GND) <400ns pulse width >400ns pulse width -10 ~ 30 -0.3 ~ 16 V POK to GND VPHASE TJ Unit Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds 150 o -65 ~ 150 o 260 o C C C Note 1 : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Thermal Resistance -Junction to Ambient TDFN3x3-10 Thermal Resistance -Junction to Case Typical Value Unit 55 °C/W 5 °C/W (Note 2) (Note 3) TDFN3x3-10 Note 2 : θJA is measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Note 3 : The case temperature is measured at the center of the exposed pad on the underside of the TDFN3x3-10 package. Recommended Operating Conditions (Note 4) Symbol Parameter Range Unit VIN Converter Input Voltage 2.2 ~ 13.2 V VCC VCC, PVCC Supply Voltage 4.5 ~ 13.2 V VOUT Converter Output Voltage 0.5 ~ 3.3 V IOUT Converter Output Current TA Ambient Temperature TJ 0 ~ 40 Junction Temperature A -40 ~ 85 o -40 ~ 125 o C C Note 4 : Refer to the typical application circuit. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 3 www.anpec.com.tw APW7190 Electrical Characteristics These specifications apply for TA = -40°C to +85°C, unless otherwise stated. All typical specifications TA= +25°C, VIN= 12V, VCC = 12V. Symbol Parameter APW7190 Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT IVCC-PWM VCC Input Bias Current at PWM Mode UGATE and LGATE Open - 1.7 2.5 mA IVCC-PFM VCC Input Bias Current at PFM Mode UGATE and LGATE Open - 350 550 µA IVCC_SHDN VCC Shutdown Current - - 70 µA FEEDBACK VOLTAGE VREF Reference Voltage IFB - 0.5 - V Regulation Accuracy o TA = -40 C ~ 85 C -0.6 - +0.6 % Line and Load Regulation 0A < IOUT < 40A; 4V < VCC < 13.2V -0.2 - +0.2 % FB Input Bias Current VFB=0.5V -0.5 - +0.5 µA o PWM CONTROLLERS TON(MIN) Minimum on Time of UGATE Over Temperature and VCC - 100 - ns TOFF(MIN) Minimum off Time of UGATE Over Temperature and VCC - 350 - ns Internal Soft-Start Time From VFB=0V to POK Rises Up TSS 3 4 5 ms Zero Crossing Voltage Threshold -3 0 +3 mV PWM to PFM Debounce Time - 20 - µs PFM to PWM Debounce Time - 20 - µs PFM On Time / PWM On Time - 1.2 - UGATE Source Resistance VBOOT=12V, ISOURCE=100mA - 1.8 2.7 Ω UGATE Sink Resistance VBOOT=12V, ISINK=100mA - 2.2 3.3 Ω LGATE Source Resistance VCC=12V, ISOURCE=100mA - 1.2 1.8 Ω LGATE Sink Resistance VCC=12V, ISINK=100mA - 1.4 2.1 Ω UGATE Source Resistance VBOOT=5V, ISOURCE=100mA - 2.4 3.75 Ω UGATE Sink Resistance VBOOT=5V, ISINK=100mA - 3 4.5 Ω LGATE Source Resistance VCC=5V, ISOURCE=100mA - 1.8 2.7 Ω LGATE Sink Resistance VCC=5V, ISINK=100mA Dead Time (Note 5) PFM/PWM On Time Ratio GATE DRIVER - 1.8 2.7 Ω 20 25 60 ns Rising VCC POR Threshold Voltage 3.9 4.1 4.3 V VCC POR Hysteresis 0.1 0.2 0.3 V VCC POWER-ON-RESET (POR) THRESHOLD VVCC_THR OSCILLATOR FSW Switching Frequency in PWM Mode DC Output Current, VCC=4.5V~13.2V 270 300 330 kHz Minimum Ultrasonic Operating Frequency VCC=4.5V ~ 13.2V 20 25 - kHz Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 4 www.anpec.com.tw APW7190 Electrical Characteristics (Cont.) These specifications apply for TA = -40°C to +85°C, unless otherwise stated. All typical specifications TA= +25°C, VIN= 12V, VCC = 12V. Symbol Parameter APW7190 Test Conditions Unit Min. Typ. Max. - - 0.4 V External Reference, VOUT=VEN/EXTREF 0.5 - 3.3 V PWM on Logic High Threshold, EN/EXTREF Rising 3.5 - - V -0.1 - 0.1 µA VFB is from low to target value (POK Goes High) 93 95 97 % ~3µs noise filter, VFB Falling (POK Goes Low) 65 70 75 % ~3µs noise filter, VFB Rising (POK Goes Low) 120 125 130 % CONTROL INPUTS Shutdown Threshold, EN/EXTREF Falling EN/EXTREF Input Voltage EN/EXTREF Leakage Current VEN/EXTREF=0V POWER OK INDICATOR (POK) VPOK POK Threshold IPOK POK Leakage Current VPOK=5V - 0.1 1.0 µA VPOK POK Output Low Voltage IPOK=-4mA - 0.5 1 V IOCSET Source Current IOCSET Sourcing 9 10 11 µA Built-in Maximum Current-Limit Threshold Voltage 230 250 270 mV Under-Voltage Protection Threshold 65 70 75 % Under-Voltage Protection Debounce Interval - 2 - µs Over-Voltage Protection Rising Threshold 120 125 130 % Over-Voltage Protection Falling Threshold 100 105 110 % Over-Voltage Protection Debounce Interval - 2 - µs Over-Temperature Protection Rising Threshold (Note 5) - 150 - o Over-Temperature Protection Hysteresis (Note 5) - 20 PROTECTION IOCSET VOCSET_MAX VUV VOVR TOTR - C o C Note 5 : Guaranteed by design. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 5 www.anpec.com.tw APW7190 Typical Operating Characteristics Referece Voltage vs. Output Current Efficiency vs. Output Current 100 VIN=12V, VCC=12V, L=1µH,VOUT=1.1V 90 0.502 80 0.501 Efficiency (%) Reference Voltage,VREF (V) 0.503 0.5 0.499 70 60 50 H-Side:IPD090N03LGx1, L-Side:IPD060N03LGx2 H-Side:IPD090N03LGx2, L-Side:IPD060N03LGx2 H-Side:BSC090N03LSGx1, L-Side:NTMFS4839NH-Dx2 H-Side:BSC090N03LSGx2, 1 1 L-Side:NTMFS4839NH-Dx2 0 40 30 20 0.498 10 0.497 -40 -20 0 20 40 60 Junction Temperature,T J 80 (oC 0 100 0.1 100 Switching Frequnecy vs. Output Current Switching Frequnecy vs. Input Voltage 350 Switching Frequency, FSW (kHz) Switching Frequency, FSW (kHz) 10 Output Current,I OUT (A) ) 330 320 310 300 290 280 270 1 2 4 6 8 10 300 250 200 150 100 50 0 12 Input Voltage,VIN (V) 0 5 10 15 20 25 30 Outupt Current,I OUT (A) 35 40 Switching Frequency Over Temperature Switching Frequency, FSW (kHz) 330 320 310 300 290 280 270 -40 -20 0 20 40 60 Junction Temperature,T J Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 80 100 (oC) 6 www.anpec.com.tw APW7190 Operating Waveforms Enable at Zero Initial Voltage of VOUT Enable before End of Soft-Stop VEN/EXTREF VEN/EXTREF 1 1 VOUT VOUT 2 2 VPHASE VPHASE 3 3 VPOK 4 4 CH1: VEN/EXTREF (5V/div) CH2: VOUT (1V/div) CH3: VPHASE (10V/div) CH4: VPOK (10V/div) Time: 5ms/div CH1: VEN/EXTREF (5V/div) CH2: VOUT (1V/div) CH3: VPHASE (10V/div) CH4: VPOK (10V/div) Time: 10ms/div Shutdown at IOUT=20A Shutdown with Soft-Stop at No Load VEN/EXTREF 1 VPOK VEN/EXTREF 1 VOUT VPHASE 2 2 VOUT VPHASE 3 3 VPOK VPOK 4 4 CH1: VEN/EXTREF (5V/div) CH2: VOUT (1V/div) CH3: VPHASE (10V/div) CH4: VPOK (10V/div) Time: 20µs/div Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 CH1: VEN/EXTREF (5V/div) CH2: VOUT (1V/div) CH3: VPHASE (10V/div) CH4: VPOK (10V/div) Time: 50ms/div 7 www.anpec.com.tw APW7190 Operating Waveforms (Cont.) Mode Change (External Mode <=> Internal Mode) Mode Transient of PWM to PFM VEN/EXTREF VEN/EXTREF 1 VOUT 1 2 VOUT 2 CH1: VEN/EXTREF (1V/div) CH2: VOUT (1V/div) Time: 10ms/div CH1: VEN/EXTREF (1V/div) CH2: VOUT (1V/div) Time: 20ms/div Load Transient Load Transient 0A->10A 10A->0A VPHASE VPHASE 1 1 2 3 VLGATE VLGATE 2 VOUT VOUT 3 IL IL 4 4 CH1: VPHASE (10V/div) CH2: VLGATE (10V/div) CH3: VOUT (AC, 50mV/div) CH4: IL (10A/div) Time: 10µs/div Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 CH1: VPHASE (10V/div) CH2: VLGATE (10V/div) CH3: VOUT (AC, 50mV/div) CH4: IL (10A/div) Time: 10µs/div 8 www.anpec.com.tw APW7190 Operating Waveforms (Cont.) Current-Limit and UV Protections Short Circuit Test VPHASE VPHASE 1 1 VLGATE VLGATE 2 2 VOUT VOUT 3 3 IL IL 4 4 CH1: VPHASE (20V/div) CH2: VLGATE (20V/div) CH3: VOUT (500mV/div) CH4: IL (10A/div) Time: 200µs/div CH1: VPHASE (20V/div) CH2: VLGATE (20V/div) CH3: VOUT (500mV/div) CH4: IL (10A/div) Time: 10µs/div Operating at UTRASONIC Mode Operating at PFM Mode VPHASE VPHASE 1 1 VLGATE 2 VLGATE 2 VOUT 3 VOUT 3 IL IL 4 4 CH1: VPHASE (10V/div) CH2: VLGATE (10V/div) CH3: VOUT (AC,50mV/div) CH4: IL (5A/div) Time: 10µs/div Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 CH1: VPHASE (10V/div) CH2: VLGATE (10V/div) CH3: VOUT (AC,50mV/div) CH4: IL (5A/div) Time: 2µs/div 9 www.anpec.com.tw APW7190 Operating Waveforms (Cont.) Operating at PWM Mode VPHASE 1 VLGATE 2 3 VOUT IL 4 CH1: VPHASE (10V/div) CH2: VLGATE (10V/div) CH3: VOUT (AC,50mV/div) CH4: IL (5A/div) Time: 2µs/div Pin Description PIN FUNCTION NO. NAME 1 BOOT This pin provides ground referenced bias voltage to the high-side MOSFET driver. A bootstrap circuit with a diode connected to 5~12V is used to create a voltage suitable to drive a logic-level N-channel MOSFET. 2 UGATE Connect this pin to the high-side N-channel MOSFET’s gate. This pin provides gate drive for the high-side MOSFET. 3 PHASE The pin provides return path for the high-side MOSFET driver’s pull-low current. Connect this pin to the high-side MOSFET’s source. 4 GND The GND terminal provides return path for the IC’s bias current and the low-side MOSFET driver’s pull-low current. Connect the pin to the system ground via very low impedance layout on PCBs. 5 Low-side Gate Driver Output and Over-Current Setting Input. This pin is the gate driver for LGATE/OCSET low-side MOSFET. It also used to set the maximum inductor current. Refer to the section in “Function Description” for detail. 6 VCC 7 FB 8 VOUT 9 POK 10 EN/EXTREF Connect this pin to a 5~12V supply voltage. This pin provides bias supply for the control circuitry and the low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset (POR) purpose. Output Voltage Feedback pin. This pin is connected to the resistive divider that set the desired output voltage. The PGOOD, UVP, and OVP circuits detect this signal to report output voltage status. The VOUT pin makes a direct measurement of the converter output voltage. The VOUT pin should be connected to the top feedback resistor at the converter output. POK is an open drain output used to indicate the status of the output voltage. Connect the POK pin to +5V or +12V through a pull-high resistor. Enable/Shutdown Pin or External Reference Selection of The PWM Controller. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 10 www.anpec.com.tw APW7190 Block Diagram POK VOUT GND VOUT VREF x 125% Sense Low-Side Debounce Time VOCSET Current-Limit VREF x 95% /70% 125% VREF OV 300kHz Ocillator Fault Latch Logic BOOT UV UGATE 70% VREF PWM Signal Controller Thermal Shutdown FB On-Time Generator ZC Error Comparator VCC Digital Soft-Start VCC LGATE/OCSET VREF VCC VOUT POR EN/EXTREF PHASE Sample and Hold VOCSET Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 PHASE 10µA To LGATE/OCSET 11 www.anpec.com.tw APW7190 Typical Application Circuit APW7190 VPOK POK CIN Q1 APM4350 UGATE 5VBUS 12V RPOK 10K VIN 2.2V ~ 13.2V 820µF x 2 BOOT CBOOT 0.1µF LOUT 1µH VOUT PHASE COUT 820µF x 3 RVCC 2.2 LGATE/OCSET ROCSET 15K, 1% VCC CVCC Q2 APM4354 RTOP 1µF CFB-VOUT 1.1K,1% GND 10nF VOUT FB 5V EN/EXTREF RGND 1K, 1% Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 12 www.anpec.com.tw APW7190 Function Description This design provides a hysteresis of converter output current to prevent wrong or repeatedly PFM/PWM handoff Constant-On-Time PWM Controller with Input FeedForward with constant output current. The load current at handoff The constant-on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This ar- from PFM to PWM mode is given by: chitecture relies on the output filter capacitor’s effective series resistance (ESR) to act as a current-sense resistor, 1 VIN - VOUT x xTON - PFM 2 L VIN - VOUT 1.2 VOUT = x x 2L FSW VIN ILOAD(PFM to PWM) = so the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time controlled by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input The load current at handoff from PWM to PFM mode is given by: voltage and directly proportional to output voltage. In PWM operation, the high-side switch on-time is determined by ILOAD(PWM to PFM) = a switching frequency control circuit in the on-time generator block. The switching frequency control circuit = 1 x VIN - VOUT 2 L VIN - VOUT 2L x xTON - PWM 1 FSW x VOUT VIN senses the switching frequency of the high-side switch and keeps regulating it at a constant frequency in PWM Therefore, the ILOAD(PFM to PWM) is 1.2 time of the ILOAD(PWM to PFM). mode. The design improves the frequency variation and is more outstanding than a conventional constant-on- In this case, APW7190 operates in ultrasonic mode with PFM when the load is zero. The ultrasonic mode is time controller, which has large switching frequency variation over input voltage, output current, and temperature. illustrated as below description. Both in PFM and PWM, the on-time generator, which Ultrasonic Mode senses input voltage on PHASE pin, provides a very fast on-time response to input line transients. The ultrasonic mode activates an unique PFM mode with a minimum switching frequency of 20kHz. The minimum frequency 20kHz of ultrasonic mode eliminates audio- Another one-shot sets a minimum off-time (typical: 350ns). The on-time one-shot is triggered if the error com- frequency interference in light load condition. It will transit to an unique PFM mode when output loading makes the parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time one- frequency bigger than ultrasonic frequency. shot has timed out. In ultrasonic mode, the controller automatically transits Pulse-Frequency Modulation (PFM) to fixed-frequency PWM operation when the load reaches the same critical conduction point (ILOAD(PFM to PWM)). In PFM mode, an automatic switchover to pulse-frequency modulation (PFM) takes place at light loads. This When the controller detects that no switching has occurred within about 40µs (Typical), an ultrasonic pulse switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero will be occurred. The ultrasonic controller turns on the low-side MOSFET firstly to reduce the output voltage. Af- crossing. This mechanism causes the threshold between PFM and PWM operation to coincide with the boundary ter feedback voltage drops below the internal reference voltage, the controller turns off the low-side MOSFET and between continuous and discontinuous inductor-current operation (also known as the critical conduction point). triggers a constant-on-time. When the constant-on-time has expired, the controller turns on the low-side MOSFET The on-time of PFM mode is designed at 1.2 time of the nominal on-time of PWM mode. The on-time of PFM is given by: TON−PFM = again until the inductor current is below the zero-crossing threshold. The behavior is the same as PFM mode. 1.2 VOUT x FSW VIN Where FSW is the nominal switching frequency of the converter in PWM mode. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 13 www.anpec.com.tw APW7190 Function Description (Cont.) V Power-On-Reset (POR) TSS = t2-t1 = 4ms A Power-On-Reset (POR) function is designed to prevent wrong logic controls when the VCC voltage is low. The VCC VPOK POR function continually monitors the bias supply voltage on the VCC pin if at least one of the enable pins is set VOUT 95% x VREF EN high. When the rising VCC voltage reaches the rising POR voltage threshold (4.1V, typical), the POR signal goes high and the chip initiates soft-start operations. When this voltage drop lower than 3.9V (typical), the POR disables the chip. t0 EN/EXTREF Pin Control t1 t2 t Figure 1. Soft-Start Sequence The voltage (V EN/EXTREF) applied to EN/EXTREF pin selects either enable-shutdown or adjustable external During soft-start stage before the POK pin is ready, the under-voltage protection is prohibited. The over-voltage reference. When VEN/EXTREF is above the EN high threshold (3.5V, typical), the PWM is enabled. When VEN/EXTREF is and over-current protection functions are enabled. If the output capacitor has residue voltage before startup, both from 0.5V to 3.3V, the output voltage can be programmed as same as VEN/EXTREF voltage. When VEN/EXTREF is below low-side and high-side MOSFETs are in off-state until the internal digital soft start voltage equal the VFB voltage. the EN low threshold (0.4V, typical), the chip is in the shutdown and only low leakage current is taken from This will ensure the output voltage starts from its existing voltage level. VCC. In the event of under-voltage, over-voltage, over-temperature or shutdown, the chip enables the soft-stop function. Digital Soft-Start The soft-stop function discharges the output voltage to GND through an internal 20Ω switch. Cycling the EN/ The APW7190 integrates digital soft-start circuits to ramp up the output voltage of the converter to the programmed EXTREF enable signal or VCC power-on-reset signal can reset the latch. regulation setpoint at a predictable slew rate. The slew rate of output voltage is internally controlled to limit the Power OK Indicator inrush current through the output capacitors during softstart process. The figure 1 shows soft-start sequence. The APW7190 features an open-drain POK pin to indicate output regulation status. In normal operation,when When the EN/EXTREF pin is pulled above the rising EN threshold voltage, the VOCSET voltage is equal to 10µA x the output voltage rises 95% of its target value, the POK goes high. When the output voltage outruns 70% or 125% ROCSET. When VCC rising POR threshold is triggered, the device starts to sample and hold the current-limit setting of the target voltage, POK signal will be pulled low immediately. threshold. The sample time is as below: Since the FB pin is used for both feedback and monitoring purposes, the output voltage deviation can be coupled IOCSET(µA) x ROCSET(kΩ) x 5 x 10-3 sec. When current-limit setting action has finished, the device initiates a soft-start process to ramp up the output voltage. directly to the FB pin by the capacitor in parallel with the voltage divider as shown in the typical applications. In The soft-start interval, TSS, is about 4ms (typical value). order to prevent false POK drop, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient and the POK comparator has a built-in 3µs noise filter. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 14 www.anpec.com.tw APW7190 Function Description (Cont.) Under-Voltage Protection (UVP) IPEAK INDUCTOR CURRENT In the process of operation, if a short-circuit occurs, the output voltage will drop quickly. When the load current is bigger than current-limit threshold value, the output voltage will fall out of the required regulation range. The under-voltage protection circuit continually monitors the VFB after soft-start is completed. If a load step is strong enough to pull the output voltage lower than the under-voltage IOUT ΔI ILIMIT 0 Time threshold, the device starts to soft-stop process to shut down the output gradually. The under-voltage threshold Figure 2. Current-Limit Algorithm is 70% of the normal output voltage. The under-voltage comparator has a built-in 2µs noise filter to prevent the A resistor (ROCSET), connected from the LGATE/OCSET to GND, programs the current-limit threshold. Before the IC chip from wrong UVP shutdown caused by noise. Cycling the EN/EXTREF enable signal or VCC power-on- initiates a soft-start process, an internal current source, IOCSET (10µA typical), flowing through the ROCSET develops reset signal can reset the latch. a voltage (VOCSET) across the ROCSET. The device holds VOCSET and stops the current source, IOCSET, during normal Over-Voltage Protection (OVP) operation. The relationship between the sampled voltage VOCSET and the current-limit threshold ILIMIT is given by: The over-voltage function monitors the output voltage by FB pin. When the FB voltage increases over 125% of the reference voltage due to the high-side MOSFET failure or for other reasons, the over-voltage protection compara- 10µA x ROCSET = ILIMIT x RDS(ON) ILIMIT can be expressed as IOUT minus half of peak-to-peak tor designed with a 2µs noise filter will force the low-side MOSFET gate driver fully turn on. This action actively pulls inductor current. The APW7190 has an internal current-limit voltage down the output voltage. When the FB voltage decreases below 105%, the OVP comparator is disengaged and (VOCSET_MAX), and the value is 0.25V typical. When the R OCSET x IOCSET exceeds 0.25V or the ROCSET is floating or not both high-side and low-side drivers turn off. This OVP scheme only clamps the voltage overshoot and connected, the over current threshold will be the internal default value 0.25V. does not invert the output voltage when otherwise activated with a continuously high output from low-side The PCB layout guidelines should ensure that noise and DC errors do not corrupt the current-sense signals at MOSFET driver. It’s a common problem for OVP schemes with a latch. Once an over-voltage fault condition is set, it PHASE. Place the hottest power MOSEFTs as close to the IC as possible for best thermal coupling. When com- can only be reset by toggling EN/EXTREF enable signal or VCC power-on-reset signal. bined with the under-voltage protection circuit, this current-limit method is effective in almost every circumstance. Current-Limit Over-Temperature Protection (OTP) The current-limit circuit employs a “valley” current-sensing algorithm (See Figure 2). The APW7190 uses the When the junction temperature increases above the rising threshold temperature TOTR , the IC will enter the over- low-side MOSFET RDS(ON) of the synchronous rectifier as a current-sensing element. If the magnitude of the cur- temperature protection state that suspends the PWM, which forces the UGATE and LGATE gate drivers output rent-sense signal at PHASE pin is above the current-limit threshold, the PWM is not allowed to initiate a new cycle. low. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple after the junction temperature cools by 20oC. The OTP is designed with a 20oC hysteresis to lower the average TJ current. Therefore, the exact current-limit characteristic and maximum load capability are the functions of the during continuous thermal overload conditions, which increases lifetime of the APW7190. sense resistance, inductor value, and input voltage. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 15 www.anpec.com.tw APW7190 Application Information Output Voltage Setting choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has The output voltage is adjustable from 0.5V to 3.3V with a resistor-divider connected with FB, GND, and converter’s been chosen, selecting an inductor which is capable of carrying the required peak current without going into output or the voltage (VEN/EXTREF) applied to EN/EXTREF pin selects adjustable external reference. Using 1% or saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase better resistors for the resistor-divider is recommended. The output voltage is determined by: R VOUT = 0.5 × 1 + TOP R GND abruptly when it saturates. This results in a larger output ripple voltage. Besides, the inductor needs to have low DCR to reduce the loss of efficiency. Output Capacitor Selection Where 0.5 is the reference voltage, RTOP is the resistor connected from converter’s output to FB, and RGND is the Output voltage ripple, the transient voltage deviation and resistor connected from FB to GND. Suggested RGND is in the range from 1K to 20kΩ. To prevent stray pickup, lo- the stability issue are factors which have to be taken into consideration when selecting an output capacitor. Higher cate resistors RTOP and RGND close to APW7190. Similarly, when VEN/EXTREF is from 0.5V to 3.3V, the output voltage capacitor value and lower ESR reduce the output ripple and the load transient drop. Generally, selecting high per- can be programmed as same as VEN/EXTREF voltage. formance low ESR capacitors is recommended for switching regulator applications. In addition to high fre- Output Inductor Selection quency noise related to MOSFET turn-on and turn-off, the output voltage ripple includes the capacitance voltage The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output voltage drop ∆VCOUT and ESR voltage drop ∆VESR caused by the AC peak-to-peak inductor’s current. These two voltages can is fixed, it can be written as: D= be represented by: VOUT VIN IRIPPLE 8COUTFSW = IRIPPLE × RESR ∆VCOUT = The inductor value (L) determines the inductor ripple ∆VESR current, IRIPPLE, and affects the load transient response. Higher inductor value reduces the inductor’s ripple cur- These two components constitute a large portion of the rent and induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: total output voltage ripple. In some applications, multiple capacitors have to be paralleled to achieve the desired IRIPPLE = ESR value. If the output of the converter has to support another load with high pulsating current, more capaci- VIN - VOUT VOUT × FSW × L VIN tors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff Nevertheless, the constant-on-time (COT) control architecture relies on the output capacitor’s ESR to act as a exists between the inductor’s ripple current and the regulator load transient response time. current-sense resistor, so the output ripple voltage provides the PWM ramp signal. For stability issue, the output A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. ripple also need to be considered. By stability experimentation result, suggesting the feedback ripple is about Increasing the switching frequency (F SW ) also reduces the ripple current and voltage, but it will increase the 25mV to 50mV. To support a load transient that is faster than the switch- switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs ing frequency, more capacitors are needed for reducing the voltage excursion during load step change. Another at the maximum input voltage. A good starting point is to Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 16 www.anpec.com.tw APW7190 Application Information Output Capacitor Selection (Cont.) Layout Consideration aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at higher rated RMS current specified on the capacitors in order to prevent the capacitor from over-heating. frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and Input Capacitor Selection parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select- condition, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and ing the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum is freewheeling by the low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power-up, the input large voltage spike during the switching interval. In general, using short and wide printed circuit traces should capacitors have to handle great amount of surge current. For low-duty notebook appliactions, ceramic capacitor is minimize interconnecting impedances and the magnitude of voltage spike. Besides, signal and power grounds recommended. The capacitors must be connected between the drain of high-side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout. are to be kept separating and finally combined using ground plane construction or single point grounding. Fig- MOSFET Selection ure 3 illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: The selection of the N-channel power MOSFETs are determined by the R DS(ON), reversing transfer capacitance (CRSS) and maximum output current requirement. = Keep the switching nodes (UGATE, LGATE/OCSET, BOOT, and PHASE) away from sensitive small signal The losses in the MOSFETs have two components: conduction loss and transition loss. For the high-side nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as pos- and low-side MOSFETs, the losses are approximately given by the following equations: sible and there should be no other weak signal traces in parallel with theses traces on any layer. Phigh-side = IOUT 2(1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW = The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and Plow-side = IOUT 2(1+ TC)(RDS(ON))(1-D) discharging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE/OCSET) should Where IOUT is the load current be short and wide. = Place the source of the high-side MOSFET and the TC is the temperature dependency of RDS(ON) FSW is the switching frequency drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane be- tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition tween the two pads reduces the voltage bounce of the node. In addition, the large layout plane between loss. The switching interval, tSW , is the function of the reverse transfer capacitance CRSS. The (1+TC) term is a the drain of the MOSFETs (VIN and PHASE nodes) can get better heat sinking. factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs. Temperature” curve = Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example, place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible.) of the power MOSFET. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 17 www.anpec.com.tw APW7190 Application Information (Cont.) Layout Consideration (Cont.) = The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capacitors should be close to the loads. The input capacitor’s ground should be close to the grounds of the output capacitors and low-side MOSFET. = Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces can’t be close to the switching signal traces (UGATE, LGATE/OCSET, BOOT, and PHASE). = The ROCSET resistance should be placed near the IC as close as possible. APW7190 VIN VCC BOOT L O A D UGATE PHASE VOUT LGATE/OCSET ROCSET Close to IC Figure 3. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 18 www.anpec.com.tw APW7190 Package Information TDFN3x3-10 A b E D Pin 1 A1 D2 A3 L E2 Pin 1 Corner e S Y M B O L TDFN3x3-10 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.30 0.007 0.012 0.122 0.106 A3 b 0.20 REF 0.18 0.008 REF D 2.90 3.10 0.114 D2 2.20 2.70 0.087 E 2.90 3.10 0.114 0.122 E2 1.40 1.75 0.055 0.069 0.50 0.012 e 0.50 BSC L 0.30 K 0.20 0.020 BSC 0.020 0.008 Note : 1. Followed from JEDEC MO-229 VEED-5. Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 19 www.anpec.com.tw APW7190 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 178.0±2.00 50 MIN. TDFN3x3-10 P0 4.0±0.10 T1 P1 4.0±0.10 C d D W E1 8.4+2.00 13.0+0.50 -0.00 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.20 1.75±0.10 P2 D0 2.0±0.05 1.5+0.10 -0.00 D1 T 1.5 MIN. A0 B0 F 3.5±0.05 K0 0.6+0.00 -0.40 3.35±0.20 3.35±0.20 1.30±0.20 (mm) Devices Per Unit Package Type TDFN3x3-10 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 Quantity 3000 20 www.anpec.com.tw APW7190 Taping Direction Information TDFN3x3-10 t USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 21 www.anpec.com.tw APW7190 Classification Reflow Profiles (Cont.) Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak (Tp)* package body Temperature Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT ESD Latch-Up Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD 78 22 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV, VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7190 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 23 www.anpec.com.tw