APW8823

APW8823
System Power PWM Controller with Economy Standby Mode
Features
Simplified Application Circuit
•
•
VIN
5.5V~25V
Wide Input voltage Range from 5.5V to 25V
Provide 5 Independent Outputs with ±1.0% Accu-
VLDO5
racy Over-Temperature
VOUT1
put
- PWM2 Controller with Adjustable (2V to 5.5V) Out-
•
•
•
•
•
•
VOUT2
PWM2
Q4
Charge Pump
C1
- 100mA Low Dropout Regulator (LDO3) with Fixed
3.3V Output
•
•
L2
Q2
- 100mA Low Dropout Regulator (LDO5) with Fixed
5V Output
•
•
•
•
•
Q3
L1
PWM1
put
•
VLDO3
LDO3
LDO5
Q1
- PWM1 Controller with Adjustable (2V to 5.5V) Out-
EN2
EN1
D1
D2
D3 C3
C2
VCP
D4
C4
- 250kHz Clock Signal for 15V Charge Pump (Used
General Description
PWM1 as Its Power Supply)
Excellent Line/Load Regulations about ±1.5% over
The APW8823 integrates dual step-down, constant-ontime, synchronous PWM controllers (that drives dual N-
temperature range at PWM Channels
Low Consumption in Standby Mode
channel MOSFETs for each channel) and two low dropout regulators as well as various protections into a chip.
2Cells Input Battery Support
Built in POR Control Scheme Implemented
The PWM controllers step down high voltage of a battery
to generate low-voltage for NB applications. The output
Constant On-Time Control Scheme
Built in Soft Start for PWM Outputs and Soft Stop
of PWM1 and PWM2 can be adjusted from 2V to 5.5V by
setting a resistive voltage-divider from VOUTx to GND.
for PWM Outputs and LDO Outputs
Integrated Bootstrap Forward P-CH MOSFET
The linear regulators provide 5V and 3.3V output for
standby power supply. The linear regulators provide up
High Efficiency over Light to Full Load Range
(PWMs)
to 100mA output current. When the PWMx output voltage
is higher than LDOx bypass threshold, the related LDOx
Built in Power Good Indicators (PWMs)
60% Under-Voltage and 115% Over-Voltage Protec-
regulator is shut off and its output is connected to VOUTx
by internal switchover MOSFET. It can save power
tions (PWM)
Adjustable Current-Limit Protection (PWMs)
dissipation. The charge pump circuit with 250kHz clock
driver uses VOUT1 as its power supply to generate ap-
- Using Sense Low-Side MOSFET’s RDS(ON)
Over-Temperature Protection
proximately 15V DC voltage.
The APW8823 provides excellent transient response and
3mmx3mm Thin QFN-20 (TQFN3x3-20) package
Lead Free and Green Device Available (RoHS
accurate DC output voltage in either PFM or PWM Mode.
In Pulse-Frequency Mode (PFM), the APW8823 provides
Compliant)
very high efficiency over light to heavy loads with loadingmodulated switching frequencies. The Forced-PWM
Mode works nearly at constant frequency for low-noise
requirements. The unique ultrasonic mode maintains the
switching frequency above 25kHz, which eliminates noise
in audio application.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
1
www.anpec.com.tw
APW8823
General Description (Cont.)
Applications
The APW8823 has individual enable controls for each
•
•
•
•
•
•
•
PWM channels. Pulling both EN1/2 pin of APW8823A/
C/G low shuts down the all of outputs unless LDO3 output.
The LDO3 and LDO5 of APW8823B/D/E/F/H are always
on standby power.The APW 8823 is available in a
TQFN3x3-20 package.
Notebook and Sub-Notebook Computers
Portable Devices
DDR1, DDR2, and DDR3 Power Supplies
3-Cell and 4-Cell Li+ Battery-Powered Devices
Graphic Cards
Game Consoles
Telecommunications
Ordering and Marking Information
APW8823A
APW8823B
APW8823C
APW8823D
APW8823E
APW8823F
APW8823G
APW8823H
Package Code
QB: TQFN3x3-20
Operating Ambient Temperature Range
I : -40 to 85 ° C
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
APW
8823A
XXXXX
XXXXX - Date Code
APW
8823B
XXXXX
XXXXX - Date Code
APW8823C QB :
APW
8823C
XXXXX
XXXXX - Date Code
APW8823D QB :
APW
8823D
XXXXX
XXXXX - Date Code
APW8823E QB :
APW
8823E
XXXXX
XXXXX - Date Code
APW8823F QB :
APW
8823F
XXXXX
XXXXX - Date Code
APW8823G QB :
APW
8823G
XXXXX
XXXXX - Date Code
APW8823H QB :
APW
8823H
XXXXX
XXXXX - Date Code
APW8823A QB :
APW8823B QB :
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
2
www.anpec.com.tw
APW8823
Device
Number
VCLK
Function
Swi tchin g Fr eque ncy
SKIP Mod e
A lwa ys ONL DO
Soft- Start
Time
Curr ent
L imit (I LIM)
APW882 3A
Enab le by EN1
400K Hz / 4 75KHz
Auto - Skip
LDO3
0.9ms
50u A
APW882 3B
Enab le by EN1
400K Hz / 4 75KHz
Auto - Skip
LDO3 & LDO5
0.9ms
50u A
APW 8823 C
Withou t VCLK
Re place SKIPSEL Pin
400K Hz / 4 75KHz
Ultra-son ic / A uto Skip
mo de se lectio n
LDO3
0.9ms
50u A
APW 8823 D
Enab le by EN1
400K Hz / 4 75KHz
Auto - Skip
LDO3 & LDO5
3.0ms
10u A
APW882 3E
Enab le by EN1
300K Hz / 3 50KHz
Ultra-son ic mod e
LDO3 & LDO5
3.0ms
10u A
APW88 23F
Enab le by EN1
300K Hz / 3 50KHz
Auto - Skip
LDO3 & LDO5
0.9ms
10u A
APW88 23G
Enab le by EN1
300K Hz / 3 50KHz
Auto - Skip
LDO3
0.9ms
10u A
APW 8823 H
Enab le by EN1
300K Hz / 3 50KHz
Ultra-son ic mod e
LDO3 & LDO5
0.9ms
10u A
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
VCLK
PHASE1
BOOT1
UGATE1
EN1
SKIPSEL
PHASE1
BOOT1
UGATE1
16
APW8823A
APW8823B
APW8823D
Bottom
APW8823E
View
APW8823F
APW8823G
APW8823H
6
7
8
9
10
15
LGATE1
14
BYP
13
LDO5
12
VIN
11
LGATE2
ILIM1
1
15
LGATE1
FB1
2
14
BYP
LDO3
3
13
LDO5
FB2
4
12
VIN
ILIM2
5
11
LGATE2
Bottom
APW8823C
View
6
7
8
9
10
UGATE2
5
17
BOOT2
ILIM2
18
PHASE2
4
19
POK
FB2
20
EN2
3
16
UGATE2
LDO3
17
BOOT2
2
18
PHASE2
FB1
19
POK
1
20
EN2
ILIM1
EN1
Pin Configuration
TQFN 3X3-20
Top View
= GND and Thermal Pad (connected to GND plane for better heat dissipation)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
3
www.anpec.com.tw
APW8823
Absolute Maximum Ratings
Symbol
VIN
V BOOT
VBOOT-GND
V UG-PHASE
V LG-GN D
(Note 1)
Param eter
Inp ut Po we r Vol tag e (VIN to GND)
B OOT Supp ly Voltage (B OOT to PHASE)
B OOT Supp ly Voltage (B OOT to GND)
UGATE Voltage (UGATE to PHASE)
<20 ns pu lse
>20 ns pu lse
L GATE Voltage ( LGATE to GND)
<20 ns pu lse
>20 ns pu lse
P HASE Voltage (PHA SE to G ND)
VPHASE
width
width
width
width
<20 ns pu lse width
>20 ns pu lse width
A ll Oth er Pins (FBx, BY P, LDO5, LDO3, VCLK, ENx, IL IMx to
GND)
TJ
Maximum Junction Temp erature
T STG
T SDR
Storag e Temp erature
Maximum Lea d Sold ering Tempera tu re, 1 0 S econds
Ra ting
Unit
- 0.3 ~ 28
V
-0.3 ~ 7
V
- 0.3 ~ 35
V
-5 ~ VBOOT +5
-0.3 ~ VBOOT +0.3
V
-5 ~ V LDO5 +5
-0.3 ~ V LDO5 +0.3
V
- 5 ~ 35
- 0.3 ~ 28
V
-0.3 ~ 6
V
1 50
o
-6 5 ~ 150
o
2 60
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics (Note 2)
Symbol
Parameter
Typical Value
θJA
Thermal Resistance -Junction to Ambient
65
θJC
Thermal Resistance -Junction to Case
10
Unit
o
C/W
Note 2: θJA and θJC are measured with the component mounted on a high effective the thermal conductivity test board in free air. The
thermal pad of package is soldered directly on the PCB.
Recommended Operating Conditions
S ymbol
Range
Unit
V IN
PWM1/2 Converter Input Vo ltag e
5.5 ~ 25
V
V OUT1
PWM1 Converter Ou tp ut Voltage
2 ~ 5 .5
V
V OUT2
PWM2 Converter Ou tp ut Voltage
2 ~ 5 .5
V
VLIMx
I LIMx A djustment Ran ge (VILIMx-GN D)
0.2~2
V
PWM1/2 Converter Input Ca pacito r ( ML CC)
10 ~
µF
LDO Ou tpu t Capacitor (MLCC)
1.0 ~
µF
C IN
C LDO
TA
TJ
Pa ram ete r
Ambi ent Temper atu re
Junction Tem perature
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
4
-4 0 ~ 85
o
-40 ~ 1 25
o
C
C
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APW8823
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V and TA= -40 ~ 85oC, unless otherwise
specified. Typical values are at TA=25oC.
S ymbol
P arame ter
APW882 3
Test Conditions
Unit
Min
Typ
Max
-
280
4 00
-
10
-
-
20
-
-
40
-
4.2
4.3
4.4
V
-
0.1
-
V
2.9
3.0
3.1
V
-
0.1
-
V
-
3.8
-
V
-
3.8
-
V
-
3.7
-
V
1.9 8
2.0
2.02
V
-20
-
20
nA
-
0.9
-
ms
-
3.0
-
ms
-
3.0
-
ms
INPUT SUPPLY POWER
I VIN
VIN Sup ply Curr ent
S uppl y curren t1, BYP=0V,
E N1 =E N2 =5V, VFB1 = VFB2 = 2.05V
S uppl y curren t2, BYP=5V,
E N1 =E N2 =5V, VFB1 = VFB2 = 2.05V
Stand by curre nt1 , BYP=0 V,
E N1 =E N2 =0V (For APW88 23A /C/G )
Stand by curre nt2 , BYP=0 V,
E N1 =E N2 =0V (For APW88 23B /D/E /F/H)
µA
µA
UNDER VOLTAGE LOCK OUT PROTECTION (UV LO)
L DO5 UV LO thresho ld
Rising Edge, PWM1/2 e nabl e
Hyste resis
L DO3 UV LO thresho ld
Rising Edge
Hyste resis
VIN POR th reshol d
Rising thresh old1, LDO3 ena ble
(For APW8 823A /C/G)
Rising thresh old2, LDO3 & LDO5 en able
(For APW8 823B /D/E/F/H)
Fall ing th reshold , LDOx sh utd own with
soft stop
P WM CONTROLLERS
V FB
I FB
T SS
F SW1
F SW2
FBx Re fe rence Voltage
o
o
T A = -40 C to 8 5 C
o
FBx inpu t curren t
V FBX=2.0V, T A=25 C
Soft-Start Tim e
E Nx Hi gh to V OU T 95% Regu lation,
L DO 5=5 V (For APW 8823 A/B/C/F/G /H)
V OUT 0% to 9 5% Regul ati on,
L DO 5=5 V(For A PW88 23D/E )
Soft-Stop Time
E Nx low to VFBX<0 .1 V
PW M1 S witchin g Fre quency
(For APW8 823A/B/C/D)
V IN =20 V, PW M1 =5V
320
4 00
480
V IN =20 V, PW M2 =3.33 V
380
4 75
570
PW M2 S witchin g Fre quency
(For APW8 823A/B/C/D)
kHz
F SW1
PW M1 S witchin g Fre quency
(For APW8 823E/F/G/H)
V IN =20 V, PW M1 =5V
240
3 00
360
F SW2
PW M2 S witchin g Fre quency
(For APW8 823E/F/G/H)
V IN =20 V, PW M2 =3.33 V
280
3 50
420
200
3 00
400
kHz
UGATEx Min imum O ff-Time
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
5
ns
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APW8823
Electrical Characteristics(Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V and TA= -40 ~ 85oC, unless otherwise
specified. Typical values are at TA=25oC.
S ymbol
Parame ter
APW882 3
Test Conditions
Unit
Min
Typ
Max
4.9
5.0
5.1
V
3 .26 7
3.300
3 .3 33
V
4.55
4.7
4.85
V
Hys.
-
150
-
mV
VOUT1 =5V, 50 mA
-
1.5
3
Ω
-
1.5
3
Ω
15 0
200
2 50
mA
-
50
1 00
Ω
LOW DRO UPUT LINE AR RE GULATO RS (LDO 5/LDO 3)
VTHBYP5
L DO5 Output Vo lta ge
BYP=GND, 7V<VIN<25V,
I LDO5<100mA
L DO3 Output Vo lta ge
7V <V IN <25V, I LDO3<100mA
L DO5 Bypass Thresho ld for
VOUT1-to-LDO5 S witch On
VOUT1 Reg ulation Voltage Rising
VOUT1-to-LDO5 S witch On
Resista nce
VIN or BYP-to -LDO3 Input Switch
VIN=5 V or BYP=5V, 50mA
On Re sistance
L DOx Curre nt Limi t
VOUTx=G ND, LDOx = GND
L DOx Disch arge O n Re sistance
I LDOX=5 mA
CHARGE P UMP CLOCK
o
V CLKH
High l eve l vol tag e
I VCLK=-10mA, LDO5 =5V, T A=25 C
-
4 .9 2
-
VCL KL
L ow level voltage
I VCLK=10mA, LDO5=5V, TA=25 oC
-
0 .0 6
-
FC LK
Clock fre quen cy
T A=2 5 C
-
250
-
kHz
110
115
1 20
%
-
3
-
µs
-
50
-
µA
-
10
-
µA
-
45 00
-
ppm/ C
20 5
250
-
mV
o
V
P WM1/2 P ROTECTIONS
Ove r Vol tag e P rotecti on Thr eshold
VFBX Risin g
Ove r Vol tag e Fa ult Pr opaga tio n
Dela y
Delta vo lta ge=10mV
o
I LIM
Curr ent L imit Curre nt So urce
VILIMx=1 V, T A = 25 C
(For APW88 23A/B/C)
o
VILIMx=1 V, T A = 25 C
(For APW88 23D/E/F/G/H)
o
On the ba sis of 2 5 C
o
Maximum settin g voltage
VILIMx =5V, Setting Curren t Limit
Thresh pld
Curr ent l imit compara tor
o ffse t
(V IL IMx-GND-V PGND -PHASEx ), VILIMx=9 20mV
-8
0
8
mV
Zero -Crossing Th reshold
VPGND – PHASE
-5
0
5
mV
Und er-Voltage Protectio n Thre sh old
55
60
65
%
Und er-Voltage Protectio n De bounce
Interval
-
25
-
µs
-
1.4
-
-
4.7
-
T J Rising
-
160
-
Hystere sis
-
25
-
Und er-Voltage Protectio n E nabl e
Blanking Tim e
Ove r-Temper atu re Protection
Thre shold
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
From EN sig nal go hig h to PO K goes
hig h (For APW 8823A /B /C/F/G /H)
From EN sig nal go hig h to PO K goes
hig h (For APW 8823 D/E)
ms
o
C
6
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APW8823
Electrical Characteristics(Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V and TA= -40 ~ 85oC, unless otherwise
specified. Typical values are at TA=25oC.
S ymbol
Parame ter
APW882 3
Test Conditions
Unit
Min
Typ
Max
87
90
93
-
10
-
110
115
1 20
-
1.4
-
-
4.7
-
2.5
7.5
-
mA
µA
POWER G OOD
POK in fro m L owe r ( POK g oes h igh)
POK Thresho ld
POK En able Delay
POK hyster esis
POK Upper Thresho ld (POK g oes
low)
From EN sig nal go hig h to PO K goes
hig h (For APW 8823A /B /C/F/G /H)
From EN sig nal go hig h to PO K goes
hig h (For APW 8823 D/E)
%
ms
POK Sin k curren t
VPOK = 500mV
POK Lea ka ge Curren t
VPOK = 5V
-
0.1
1
En able
-
-
1.5
0.4
-
-
-
0.1
1
µA
-
-
1.5
V
2.7
-
-
V
LOGIC LEVE LS
ENx In put Vo ltag e Thre shold
V
shutdown
ENx In put l eakage curre nt
VEN =5V
SKIPSEL Input Volta ge
(For APW8 823C)
Au to Skip with Ultraso nic
Au tom atic PFM/PW M Mode
G ATE DRIVERS
UG Pull -Up Resistance
VBOOTx – V UGATEx=250mV
-
3
5
Ω
UG Sink Resistance
VUGATEx – V PHASEx=25 0mV
-
1.7
2.5
Ω
LG Pull-Up Resistance
VLD O5 – V LGATEx=250m V
-
3
5
Ω
LG Sink Resista nce
VLGATEx – V PGN D=2 50mV
-
1.0
2
Ω
UG fall ing to LG r isi ng
-
20
-
ns
L G fa lling to UG r isi ng
-
20
-
ns
Dea d Time
BO OTSTRAP S WITCH
VF
Forwar d Vo lta ge
VL DO5 – V BOOTx-GND, IF = 10mA
-
0 .1 5
0.25
V
IR
Reverse Le akage
VBOOTx-GND = 30V, V PH ASEx = 25 V, V LDO5
= 5V
-
-
0.5
µA
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
7
www.anpec.com.tw
APW8823
Pin Description
PIN
FUNCTION
NO .
NAME
1
ILIM1
2
FB1
3
LDO3
4
FB2
5
ILIM2
6
E N2
7
P OK
Cu rrent L imit Adju stment. Ther e is a n in ter nal 10µA curre nt source from LDO5 to ILIM1 a nd co nnected a
resistor from IL IM1 to G ND to set th e cu rrent l imit threshol d. The PGND-PHASE1 curre nt- limit thresho ld
is 1/8th th e vol ta ge set at ILIM1 ove r a 0 .2 to 2V ran ge. The lo gic curre nt limit th reshold is default to
250mV valu e if IL IM1 is 5 V.
Ou tpu t voltage feedb ack pin (PWM1) . It can use a resistive divider from VOUT1 to G ND to a djust the
outpu t fr om 2 V to 5.5V .
3.3V Li near Regu lato r Output. LDO3 can p rovide a to tal of 100mA , 3.3V exte rnal loa ds. Bypass to
GND with a minimum of 1 .0u F ceramic capacitor fo r stabili ty.
Ou tpu t voltage feedb ack pin (PWM2) . It can use a resistive divider from VOUT2 to G ND to a djust the
outpu t fr om 2 V to 5.5V .
Curren t Limit Adjustment. There is an interna l 10 µA curren t source fro m L DO 5 to ILIM2 an d con necte d
a resistor from ILIM2 to GND to set the curren t limit thresh old. The PG ND- PHASE 2 cu rrent-limit
th
threshol d is 1/8 th e voltag e set at ILIM2 o ve r a 0.2 to 2V rang e. The logi c curren t limit thresh old is
defau lt to 250mV value if ILIM2 is 5V .
PWM2 En able. PWM2 is ena bled when E N2 =1. When EN2=0, PWM2 is in shutdown.
Po wer -Good O utput Pin of Both P WMs (Log ic A ND). POK is an open -drain o utp ut use d to ind ica te the
sta tus of the PWMx o utput voltag e. Conn ect th e POK in to +5V thro ugh a pull -high resistor.
8
PHASE2
Juncti on Poin t of The High -Side MOS FE T Sou rce, Ou tpu t Filter In ducto r a nd Th e Low-Sid e MO SFET
Dra in fo r PWM2. Conn ect this pin to the Sour ce of th e h igh-sid e MOSFET. PHAS E2 serves as th e
l ower su pply rail for the UGATE2 high -side gate driver. P HA SE2 is the curr ent-sense input fo r the
P WM2.
9
B OOT2
Sup ply Inp ut for Th e UGATE2 Ga te Driver and a n internal level- sh ift circu it. Co nnect to an exte rnal
ca pacito r to create a boosted volta ge suita ble to d rive a lo gic-level N-channe l MO SFET.
10
UG ATE2
Ou tpu t of The High -Sid e MOS FET Driver for PWM2. Conn ect this pin to Gate of the h igh-side
MOSFET.
11
L GATE2
Outpu t of The Lo w-Side MOSFET Dr ive r for PWM2. Connect this pin to G ate of the low-side MOSFET.
S wings fro m PGND to LDO5.
12
VIN
Ba ttery vo lta ge input pin. VIN powers line ar regu lators a nd is also used for th e co nstant on-time PWM
on-time on e-shot circuits. Conne ct VIN to the b attery inpu t and b ypass with a 1µF capacitor fo r n oise
interferen ce.
5V Li near Regu lator Output. L DO 5 ca n p rovide a tota l of 100mA, 5V exte rnal loa ds. Whe n L DO5 is at
5V an d P WM1 output voltag e is over bypass thre shold and POK is in hi gh state and PW M1 is not in
curren t limit con dition , the interna l L DO will shut down, a nd LDO5 ou tpu t pin con nects to VO UT1
throug h a 1.5 Ω switch . Bypass to GND with a minimum of 1.0u F ceramic capacitor fo r stability.
BYP is the input pin of switchover vo lta ge for the L DO5. This pin makes a di rect measureme nt of th e
PWM1 outpu t vo ltage.
13
LDO5
14
BYP
15
L GATE1
Outpu t of The Lo w-Side MOSFET Dr ive r for PWM1. Connect this pin to G ate of the low-side MOSFET.
S wings fro m PGND to LDO5.
16
UG ATE1
Ou tpu t of The High -Sid e MOS FET Driver for PWM1. Conn ect this pin to Gate of the h igh-side
MOSFET.
17
BOOT1
Sup ply Inp ut for Th e UGATE1 Ga te Driver and a n internal level- sh ift circu it. Co nnect to an exte rnal
ca pacito r to create a boosted volta ge suita ble to d rive a lo gic-level N-channe l MO SFET.
PHASE1
Juncti on Poin t of The High -Side MOS FE T Sou rce, Ou tpu t Filter In ducto r a nd Th e Low-Sid e MO SFET
Dra in fo r PWM1. Conn ect this pin to the Sour ce of th e h igh-sid e MOSFET. PHAS E1 serves as th e
l ower su pply rail for the UGATE1 high -side gate driver. P HA SE1 is the curr ent-sense input fo r the
P WM1.
18
VCLK
19
250 kHz Cl ock Outpu t for 15V Charge Pump. ( Fo r APW8 823A/B/D/E/F/G/H)
PWM1 and 2 Controlle r Opera tio n Mod e Co ntrol. Con nect SKIP SEL to GND for auto skip mo de with
SKIPSEL
Ultra- so nic, an d to LDO3 or LDO5 for au to skip mo de with out u ltra -sonic. (For APW 8823 C)
20
EN1
PWM1 En able. PWM1 is ena bled when E N1 =1. When EN1=0, PWM1 is in shutdown.
Therma l Pad
GND
Sig nal Gro und for Th e IC.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
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APW8823
Typical Operating Characteristics
Efficiency vs. Output Current
Efficiency vs. Output Current
100
100
VOUT1=5V
VOUT2=3.3V
98
95
96
Efficiency (%)
Efficiency (%)
94
92
90
88
86
90
85
80
VIN=7.4V
VIN=7.4V
84
75
VIN=12V
82
VIN=20V
VIN=20V
70
80
0.001
0.01
0.1
1
VIN=12V
0.001
10
0.01
0.1
1
10
Output Current (A)
Output Current (A)
Load Reguretion
Load Reguretion
5.15
3.40
VOUT1=5V
VOUT2=3.3V
Output Voltage (V)
Output Voltage (V)
5.10
5.05
5.00
4.95
VIN=7.4V
4.90
3.35
3.30
3.25
VIN=7.4V
VIN=12V
VIN=12V
VIN=20V
VIN=20V
3.20
4.85
0.001
0.01
0.1
1
0.001
10
0.01
Output Current (A)
0.1
1
10
Output Current (A)
Line Regulation
Line Regulation
5.15
3.40
VOUT2=3.3V
VOUT1=5V
Output 2 Voltage (V)
Output 1 Voltage (V)
5.10
5.05
5.00
4.95
4.90
3.35
3.30
3.25
IOUT1=0A
4.85
IOUT2=0A
IOUT1=6A
IOUT2=7A
4.80
3.20
5
10
15
20
5
25
Input Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
10
15
20
25
Input Voltage (V)
9
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APW8823
Typical Operating Characteristics
Switching Frequency vs. Output
Current
Switching Frequency vs. Output
Current
600
600
VIN=7.4V
VIN=12V
500
Switching Frequency (kHz)
Switching Frequency (kHz)
VIN=7.4V
VIN=20V
400
300
200
100
VOUT1=5V
0
0.001
0.01
0.1
1
VIN=12V
500
VIN=20V
400
300
200
100
VOUT2=3.3V
0
0.001
10
Output Current (A)
Switching Frequency vs. Input
Voltage
Switching Frequency (kHz)
Switching Frequency (kHz)
500
400
300
200
100
VOUT1=5V
IOUT1=6A
20
500
400
300
200
100
0
25
5
Input Voltage (V)
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Rev. A.2 - Jan., 2016
10
VOUT2=3.3V
IOUT2=7A
0
15
1
Switching Frequency vs. Input
Voltage
600
10
0.1
Output Current (A)
600
5
0.01
10
15
20
25
Input Voltage (V)
10
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APW8823
Operating Waveforms
Enable
Shutdown
VEN1=VEN2
VEN1=VEN2
1
1
VOUT1
VOUT1
2
2
VOUT2
VOUT2
3
4
3
VPOK
VPOK
4
CH1: VEN1=VEN2, 5V/Div
CH2: VOUT1, 2V/Div
CH3: VOUT2, 2V/Div
CH4: VPOK, 5V/Div
Time: 200us/Div
CH1: VEN1=VEN2, 5V/Div
CH2: VOUT1, 2V/Div
CH3: VOUT2, 2V/Div
CH4: VPOK, 5V/Div
Time: 1ms/Div
Output 1 Ripple Voltage
Output 2 Ripple Voltage
VOUT1
VOUT2
1
1
VPHASE2
VPHASE1
2
2
IL1
IL2
3
3
CH1: VOUT2, 50mV/Div, AC
CH2: VPHASE2, 5V/Div
CH3: IL2, 5A/Div
Time: 1us/Div
CH1: VOUT1, 50mV/Div, AC
CH2: VPHASE1, 5V/Div
CH3: IL1, 5A/Div
Time: 1us/Div
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APW8823
Operating Waveforms
Current Limit, R ILIM=15kΩ
Line Transient
VIN
VEN1
1
1
VOUT1
VOUT1
2
2
VOUT2
3
3
IL1
VPHASE 1
I L1
4
4
CH1: VEN1 , 5V/Div
CH2: VOUT1, 50mV/Div
CH3: VPHASE1, 5V/Div
CH4: IL1 , 10A/Div
Time: 200us/Div
CH1: VIN, 5V/Div
CH2: VOUT1, 100mV/Div, AC
CH3: VOUT2, 50mV/Div, AC
CH4: IL1, 2A/Div
Time: 1ms/Div
Load Transient
Load Transient
VIN=7.4V
VIN=7.4V
VOUT1
VOUT2
1
1
2
2
IOUT1=0.6A~5.4A
CH1: VOUT1, 100mV/Div, AC
CH2: IOUT1, 2A/Div
Time: 100us/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
IOUT2=0.7A~6.3A
CH1: VOUT1, 100mV/Div, AC
CH2: IOUT2, 2A/Div
Time: 100us/Div
12
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APW8823
Operating Waveforms
Over Voltage Protection
Under Voltage Protection
VPOK
VPOK
1
1
VOUT1
VPHASE1
4
VOUT1
2
2
VPHASE1
3
IL1
3
IL1
4
CH1: VPOK, 5V/Div
CH2: VOUT1, 2V/Div
CH3: VPHASE1, 10V/Div
CH4: IL1, 10A/Div
Time: 20us/Div
CH1: VPOK, 5V/Div
CH2: VOUT1, 2V/Div
CH3: VPHASE1, 10V/Div
CH4: IL1, 10A/Div
Time: 100us/Div
Copyright  ANPEC Electronics Corp.
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APW8823
Block Diagram
BOOT2
ADAPTIVE
DEAD-TIME
DIODE
EMULATION
PWM/PFM
TRANSITION
UGATE2
PWM FREQUENCY
CONTROL
PHASE2
TON
Generator
PHASE1
BOOT1
ADAPTIVE
DEAD-TIME
DIODE
EMULATION
PWM/PFM
TRANSITION
UGATE1
PHASE2
PHASE1
ZC2
LGATE2
ZC1
SMPS1
PWM2
CONTROLLER
SMPS2
PWM2
CONTROLLER
LDO5
LDO5
LGATE1
PGND
VIN
LDO UVLO
LDO3
LDO3
LDO5
THERMAL
SHUTDOWN
BYP
LDO5
VIN
EN ENABLE
POWER ON SEQUENCE
CLEAR FAULT LATCH
EN2
EN1
PHASE1
ILIM2
ILIM1
PHASE2
VTHBYP5
CURRENT LIMIT
CONTROLLER
CHARGE PUMP
OSCILLATOR
SOFT START
POK
BYP
VCLK
POK2
POK1
90% VFB2
90% VFB1
125% VFB2
125% VFB1
OV2
OV1
FAULT
LATCH
LOGIC
FB2
FB1
UV1
UV2
70% VFB2
LGATE2
70% VFB1
SOFT
STOP
EN2
EN1
SOFT
STOP
LGATE1
GND
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APW8823
Typical Application Circuit
For APW8823A/B/D/E/F/G/H
VIN : 5.5V to 25V
LDO5
CLDO5
1µF
LDO3
VIN
CLDO3
1µF
POK
CIN1
10µF
VOUT1
5V/7A
COUT1
RPOK
200k
Q1
APM4810
LOUT1
4.7µH
BOOT1
BOOT2
RBOOT1
0
CBOOT1
0.1µF
Q3
APM4810
RBOOT2
0
UGATE1
UGATE2
PHASE1
PHASE2
LGATE1
LGATE2
GND
GND
RTOP1
30k
VOUT2
3.3V/11A
LOUT2
2.2µH
CBOOT2
0.22µF
Q2
APM4810
330µF/10V
9m ohm
CIN2
10µF
COUT2
330µF/6.3Vx2
4m ohm
Q4
APM4810
RTOP2
13k
BYP
FB1
FB2
ILIM2
ILIM1
RILIM2
40k
RILIM1
40k
RGND1
20k
ON
ON
RGND2
20k
EN2
EN1
OFF
OFF
GND
GND
VCLK
CCP1
100nF
CCP2
100nF
D1
VCP
15V
CCP3
100nF
D2
D3
D4
CCP4
1µF
For APW8823A/B/D/E/F/G/H(COUT used pure MLCC)
VIN : 5.5V to 25V
LDO3
LDO5 VIN
CLDO5
1µF
CLDO3
1µF
POK
CIN1
10µF
VOUT1
5V/7A
COUT1
22µF/25V*4
MLCC
RPOK
200k
Q1
APM4810
LOUT1
4.7µH
BOOT1
BOOT2
RBOOT1
0
CBOOT1
0.1µF
Q3
APM4810
RBOOT2
0
UGATE1
UGATE2
PHASE1
PHASE2
CBOOT2
0.22µF
Q2
APM4810
LGATE1
GND
RTOP1
30k
LGATE2
GND
CIN2
10µF
LOUT2
2.2µH
VOUT2
3.3V/11A
Q4
APM4810
COUT2
22µF/25Vx4
MLCC
RTOP2
13k
BYP
CFB1
100p
FB1
FB2
ILIM2
ILIM1
RILIM2
40k
RILIM1
40k
RGND1
20k
ON
OFF
CFB2
100p
ON
RGND2
20k
EN2
EN1
OFF
GND
GND
VCLK
CCP1
100nF
D1
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CCP3
100nF
D2
CCP2
100nF
D3
D4
VCP
15V
CCP4
1µF
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APW8823
Typical Application Circuit
For APW8823C
VIN : 5.5V to 25V
LDO5 VIN
CLDO5
1µF
LDO3
CLDO3
1µF
POK
CIN1
10µF
VOUT1
5V/7A
COUT1
RPOK
200k
Q1
APM4810
LOUT1
4.7µH
BOOT1
BOOT2
RBOOT1
0
Q3
APM4810
RBOOT2
0
UGATE1 UGATE2
CBOOT1
0.1µF
PHASE1
CBOOT2
0.22µF
PHASE2
Q2
APM4810
330µF/10V
9m ohm
LGATE1
LGATE2
GND
GND
RTOP1
30k
CIN2
10µF
LOUT2
2.2µH
VOUT2
3.3V/11A
Q4
APM4810
COUT2
330µF/6.3Vx2
4m ohm
RTOP2
13k
BYP
FB2
FB1
ILIM2
ILIM1
RILIM2
40k
RILIM1
40k
RGND1
20k
ON
ON
RGND2
20k
EN2
EN1
OFF
OFF
GND
GND
SKIPSEL
PFM
Ultrasonic
For APW8823C (COUT used pure MLCC)
VIN : 5.5V to 25V
LDO5
CLDO5
1µF
VIN
LDO3
CLDO3
1µF
POK
CIN1
10µF
VOUT1
5V/7A
COUT1
RPOK
200k
Q1
APM4810
LOUT1
4.7µH
BOOT1
BOOT2
RBOOT1
0
CBOOT1
0.1µF
Q3
APM4810
RBOOT2
0
UGATE1
UGATE2
PHASE1
PHASE2
CBOOT2
0.22µF
Q2
APM4810
22µF/25V*4
MLCC
LGATE1
RTOP1
30k
VOUT2
3.3V/11A
LOUT2
2.2µH
COUT2
22µF/25Vx4
MLCC
Q4
APM4810
LGATE2
GND
GND
CIN2
10µF
RTOP2
13k
BYP
CFB1
100p
FB1
FB2
ILIM2
ILIM1
RILIM2
40k
RILIM1
40k
RGND1
20k
ON
OFF
CFB2
100p
ON
EN2
EN1
OFF
GND
RGND2
20k
GND
SKIPSEL
PFM
Ultrasonic
Copyright  ANPEC Electronics Corp.
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APW8823
Function Description
Where FSW is the nominal switching frequency of the converter in PWM mode. Similarly, the on-time of ultrasonic
Constant-On-Time PWM Controller with Input Feed-Forward
The constant-on-time control architecture is a pseudo-
mode is the same with PFM mode.
The load current at handoff from PFM to PWM mode is
fixed frequency with input voltage feed-forward. This architecture relies on the output filter capacitor’s effective
given by:
series resistance (ESR) to act as a current-sense resistor,
so the output ripple voltage provides the PWM ramp signal.
ILOAD(PFM to PWM) =
In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined solely by a one-
=
shot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
a switching frequency control circuit in the on-time gen-
1 VIN − VOUT
×
× TON −PFM
2
L
VIN − VOUT
V
1
×
× OUT
2L
F SW
VIN
Linear Regulator (LDO3 and LDO5)
The LDO3 and LDO5 regulators can supply up to 100mA
erator block. The switching frequency control circuit
senses the switching frequency of the high-side switch
for external loads. Bypass to GND with a minimum of 1uF
ceramic capacitor for stability. For APW8823A/C, When
and keeps regulating it at a constant frequency in PWM
mode. The design improves the frequency variation and
VIN reaches POR rising threshold, only the VLDO3 is fixed
3.33V in standby mode. For APW8823B/D/E, When VIN
is more outstanding than a conventional constant-ontime controller, which has large switching frequency varia-
reaches POR rising threshold, the VLDO3 is fixed 3.33V
and the VLDO5 is fixed 5V in standby mode. Let’s see the
tion over input voltage, output current and temperature.
Both in PFM and PWM, the on-time generator, which
table2 “Power-Up Control Logics” for the detail description about standby mode. For all of APW8823 series, When
senses input voltage on VIN pin, provides very fast ontime response to input line transients.
PWM1 output voltage is over whose bypass threshold,
and POK is in high state and PWM1 is not in current limit
Another one-shot sets a minimum off-time (typ.300ns).
The on-time one-shot is triggered if the error comparator
condition , the internal LDO5 to VOUT1 switchover is
active. These actions change the current path to power
is high, the low-side switch current is below the currentlimit threshold, and the minimum off-time one-shot has
the loads from the PWM regulator voltage, rather than
from the internal linear regulator.
timed out.
Power -On-Reset
Pulse-Frequency Modulation (PFM) Mode
In PFM mode, an automatic switchover to pulse-frequency
A Power-On-Reset (POR) function is designed to prevent
wrong logic controls. The POR function continually moni-
modulation (PFM) takes place at light loads. This
switchover is affected by a comparator that truncates the
tors the supply voltage on the LDO5 pins. LDO5 POR
circuitry inhibits wrong switching. When the rising VLDO5
low-side switch on-time at the inductor current zero
crossing. This mechanism causes the threshold between
voltage reaches the rising POR threshold (4.3V typical),
the PWM output voltages begin to ramp up. When the
PFM and PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current
LDO5 voltage is lower than 4.2V(typ.) or LDO3 voltage is
lower than 2.9V(typ.), both switch power supplies are shut
operation (also known as the critical conduction point).
The on-time of PFM is given by:
off. This is non-latch protection. LDO5 POR threshold
could reset the under-voltage, over-voltage.
TON - PFM =
V
1
× OUT
FSW
VIN
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APW8823
Function Description (Cont.)
Soft Start
Soft-Stop (PWMs)
The APW8823 integrates soft-start circuit to ramp up the
PWMx output voltage of the converter to the programmed
In the event of PWM under-voltage or shutdown, the chip
enables the soft-stop function. The soft-stop function discharges the PWM output voltages to low voltage by the
regulation set point at a predictable slew rate. The slew
rate of PWMx output voltage is internally controlled to limit
soft stop method. The reference remains active to provide an accurate threshold and to provide over-voltage
the inrush current through the output capacitors during
soft start process. When the ENx pin is pulled above the
protection.
rising threshold voltage, the related PWM initiates a softstart process to ramp up the output voltage. The soft-start
Power Good Indicator (PWMs)
interval is 0.9ms(typical)(APW8823A/B/C/F/G/H) and independent of the UGATE switching frequency.
When the junction temperature increases above the rising threshold temperature 160oC, the IC will enter the
Enable Controls
over temperature protection (OTP). When the OTP occurs,
LDO and PWM controllers circuitry shuts down. It is non-
The APW8823 has two independent enable controls for
PWM part. When the ENx pin is high at standby mode, the
PWMx initiates a soft-start process to ramp up the output
latch protection.
voltage. The PWM1 and PWM2 are controlled individually
by EN1 and EN2. When EN1 and EN2 are both low, the
Current Limit (PWMs)
chip is in its low-power standby state. The APW8823A/C/
G only consumes 20µA of current while in standby mode.
The current limit circuit employs a "valley" current-sensing algorithm (See Figure 1). The APW8823A/B/C/D/E
When the EN1 is high, the clock signal becomes available from VCLK pin. Both PWM outputs are discharged to
uses the low-side MOSFET’s RDS(ON) of the synchronous
rectifier as a current-sensing element. If the magnitude
of the current-sense signal at PHASE pin is above the
low voltage by the soft stop method and both LDO outputs are discharged to 0V through a 50Ω switch in soft
current-limit threshold, the PWM is not allowed to initiate
a new cycle. The actual peak current is greater than the
stop state. Driving EN1 and EN2 (logic AND) below low
threshold clears the over-voltage, and under-voltage fault
current-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit charac-
latches.
teristic and maximum load capability are a function of the
sense resistance, inductor value, and input voltage.
Charge Pump(For APW8823A/B/D/E/F/G/H)
IPEAK
INDUCTOR CURRENT
The condition of the 250kHz clock signal can be used is
that the EN1 is high. When VOUT1 regulates at 5V and the
clock signal uses VOUT1 as its power supply, the charge
pump circuit can generate 15V DC voltage approximately.
The example of charge pump circuit is shown in typical
application circuit.
IOUT
ΔI
ILIMIT
0
Time
Figure 1. Current Limit algorithm
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APW8823
Function Description (Cont.)
Current Limit (PWMs)(cont.)
Both PWM controllers use the low-side MOSFETs onresistance RDS(ON) to monitor the current for protection
Where VILIMX is the voltage at the ILIMx pin. RDS(ON) is the
low side MOSFETs conducive resistance. ILIMIT is the set-
against shorted outputs. The MOSFET’s RDS(ON) is varied
by temperature and gate to source voltage, the user
ting current limit threshold. ILIMIT can be expressed as IOUT
minus half of peak-to-peak inductor current.
should determine the maximum RDS(ON) in manufacture’s
datasheet.
The PCB layout guidelines should ensure that noise and
DC errors do not corrupt the current-sense signals at
The current Limit threshold of APW8823A/B/C/D/E is adjusted with an external resistor. The current-limit thresh-
PHASE. Place the hottest power MOSEFTs as close to
the IC as possible for best thermal coupling. When com-
old voltage is 1/8th the voltage at ILIMx pin. As shown in
Figure 2, The ILIMx pin can source 50µA(APW8823/A/B/
bined with the under-voltage protection circuit, this current-limit method is effective in almost every circumstance.
C). The voltage at ILIMx pin is equal to 50µA x RILIM. The
logic current limit threshold is default to 250mV value if
ILIM
voltage at ILIMx pin is above 2V. The relationship between
the sampled voltage VILIM and the current limit threshold
VILIM
ILIMIT is given by:
RILIM
50uA
1
× VILIMX = ILIMIT × RDS( ON)
8
7R
TO CURRENT
LIMIT LOGIC
R
Figure 2. Current-Limit Setting Block Diagram
Table 1. Operating Mode Truth Table
MO DE
Run
Stan dby
&
S oft Sto p
UVP
OVP
OTP
CONDITION
COMMENT
ENx = 1
PWM is in no rmal opera tio n.
PWMx is i n shutdown with soft stop, and th en LDO5 is also in
shutdown with discharge function a fter soft sto p function in
PWMx is completed. LDO3 is a ctive.
PWMx is in shutdown with so ft sto p function. L DO 3 a nd L DO 5
APW8 823B /D/E/F/H
E Nx=0
are active.
The soft stop function wi ll enable to pul l lo w outpu t voltage.
Either VOUT1, or VOUT2 < 60% of nomina l o utput LDOx is active. Reset by tog gling E N1 and EN2 (log ic AND).
vo lta ge
This acti on will re-start LDO5 a t the same time. (For
APW8 823A/C/G).
LGATE of th e PWM ch anne l, which occurs OVP e ven t is fo rced
high , the othe r PW M cha nnel is in shutdown with soft stop.
Either VOUT1 a nd V OU T2>115% of no rmal output
LDOx is active. Reset by tog gling E N1 and EN2 (log ic AND).
vo lta ge
This acti on will re-start LDO5 a t the same time. (For
APW8 823A/C/G).
All circuitry off. It is non-l atch pr ote ctio n after the juncti on
o
T J > +160 C
o
tempera tur e coo ls by 25 C.
APW8 823A /C/G
E Nx = 0
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Rev. A.2 - Jan., 2016
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APW8823
Function Description (Cont.)
Table 2. Power-Up Control Logics
For APW8823A/G
VEN1
VEN2
LDO5
LDO3
PWM1
PWM2
VCLK*
OFF
OFF
OFF
ON
ON
ON
Low
Low
OFF
ON
High
High
ON
ON
ON
ON
ON
OFF
ON
ON
ON
OFF
ON
OFF
High
Low
Low
High
For APW8823C
VEN1
VEN2
LDO5
LDO3
PWM1
PWM2
Low
Low
OFF
ON
OFF
OFF
High
High
ON
ON
ON
ON
High
Low
ON
ON
ON
OFF
ON
ON
OFF
ON
Low
High
For APW8823B/D/E/F/H
VEN1
Low
VEN2
Low
LDO5
LDO3
PWM1
ON
ON
PWM2
VCLK*
OFF
OFF
OFF
ON
ON
ON
High
High
ON
ON
High
Low
ON
ON
ON
OFF
ON
Low
High
ON
ON
OFF
ON
OFF
*. Need connected the correct charge pump circuit on VCLK pin.
Copyright  ANPEC Electronics Corp.
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APW8823
Application Information
Output Voltage Selection
ripple current occurs at the maximum input voltage. A
The output voltage of PWM1 can be adjusted from 2V to
5.5V with a resistor-driver at FB1 between VOUT1 and
good starting point is to choose the ripple current to be
approximately 30% of the maximum output current.
GND. Using 1% or better resistors for the resistive divider is recommended. The FB1 pin is the inverter input
Once the inductance value has been chosen, selecting
an inductor is capable of carrying the required peak cur-
of the error amplifier, and the reference voltage is 2V.
Take the example, the output voltage of PWM1 is deter-
rent without going into saturation. In some types of
inductors, especially core that is made of ferrite, the ripple
mined by:
current will increase abruptly when it saturates. This will
be result in a larger output ripple voltage.
VOUTI

R
= 2 ×  1 + TOP1
R
GND1

Output Capacitor Selection




Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting an output capacitor. Higher
Where RTOP1 is the resistor connected from VOUTI to VFB1
and RGND1 is the resistor connected from FB1 to GND.
capacitor value and lower ESR reduce the output ripple
and the load transient drop. Therefore, selecting high
Similarly, the output voltage of PWM2 can be alsoadjusted
from 2V to 5.5V.
performance low ESR capacitors is intended for switching regulator applications. In addition to high frequency
Output Inductor Selection
noise related MOSFET turn-on and turn-off, the output
voltage ripple includes the capacitance voltage drop and
The duty cycle of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
ESR voltage drop caused by the AC peak-to-peak current.
These two voltages can be represented by:
is fixed, it can be written as:
D=
VOUT
VIN
∆VESR
The inductor value determines the inductor ripple current
and affects the load transient reponse. Higher inductor
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
value reduces the inductor’s ripple current and induces
lower output ripple voltage. The ripple current can be
capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
approxminated by:
IRIPPLE =
IRIPPLE
8COUTFSW
= IRIPPLE × RESR
∆VCOUT =
VIN - VOUT VOUT
×
VIN
FSW × L
another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR
Where FSW is the switching frequency of the regulator.
Increasing the inductor value and frequency will re-
and suppress the voltage ripple to a tolerable level. A
small decoupling capacitor in parallel for bypassing
duce the ripple current and voltage. However, there is a
tradeoff between the inductor’s ripple current and the
the noise is also recommended, and the voltage rating
of the output capacitors must also be considered.
regulator load transient response time.
To support a load transient that is faster than the
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple
switching frequency, more capacitors have to be used
to reduce the voltage excursion during load step change.
current. Increasing the switching frequency (FSW ) also
reduces the ripple current and voltage, but it will
Another aspect of the capacitor selection is that the
total AC current going through the capacitors has to be
increase the switching loss of the MOSFETs and the
power dissipation of the converter. The maximum
less than the rated RMS current specified on the capacitors to prevent the capacitor from over-heating.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
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APW8823
Application Information (Cont.)
(CRSS) and maximum output current requirement. The
Input Capacitor Selection
losses in the MOSFETs have two components: conduction loss and transition loss. For the high-side and low-
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select
side MOSFETs, the losses are approximately given by
the following equations:
the capacitor voltage rating to be at least 1.3 times higher
than the maximum input voltage. The maximum RMS
2
Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
current rating requirement is approximately IOUT/2, where
IOUT is the load current. During power up, the input capaci-
2
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)
tors have to handle large amount of surge current. In lowduty notebook appliactions, ceramic capacitors are
Where
I
is the load current
OUT
remmended. The capacitors must be connected between
the drain of high-side MOSFET and the source of low-
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
side MOSFET with very low-impeadance PCB layout.
tSW is the switching interval
D is the duty cycle
MOSFET Selection
The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should
Note that both MOSFETs have conduction losses while
the high-side MOSFET includes an additional transi-
be used. The design has to trade off the gate charge with
the RDS(ON) of the MOSFET:
tion loss. The switching internal, t SW , is the function
of the reverse transfer capacitance CRSS. The (1+TC) term
•
•
is to factor in the temperature dependency of the R DS(ON)
and can be extracted from the “RDS(ON) vs Temperature”
For the low-side MOSFET, before it is turned on, the
body diode has been conducted. The low-side MOSFET
driver will not charge the miller capacitor of this
curve of the power MOSFET.
MOSFET.
Layout Consideration
In the turning off process of the low-side MOSFET,
In any high switching frequency converter, a correct layout
is important to ensure proper operation of the regulator.
the load current will shift to the body diode first. The
high dv/dt of the phase node voltage will charge the
With power devices switching at higher frequency, the
resulting current transient will cause voltage spike across
miller capacitor through the low-side MOSFET driver
sinking current path. This results in much less
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
switching loss of the low-side MOSFETs. The duty
cycle is often very small in high battery voltage
of the PWM MOSFET. Before turn-off condition, the
MOSFET is carrying the full load current. During turn-off,
applications, and the low-side MOSFET will conduct most of the switching cycle; therefore, the less
current stops flowing in the MOSFET and is freewheeling
by the lower MOSFET and parasitic diode. Any parasitic
the RDS(ON) of the low-side MOSFET, the less the power
loss. The gate charge for this MOSFET is usually a
inductance of the circuit generates a large voltage spike
during the switching interval. In general, using short and
secondary consideration. The high-side MOSFET
does not have this zero voltage switching
wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. And
condition, and because it conducts for less time
compared to the low-side MOSFET, the switching
signal and power grounds are to be kept separating and
finally combined to use the ground plane construction or
loss tends to be dominant. Priority should be given
to the MOSFETs with less gate charge, so that both
single point grounding. The best tie-point between the
signal ground and the power ground is at the negative
the gate driver loss and switching loss will be
minimized.
The selection of the N-channel power MOSFETs are de-
side of the output capacitor on each channel, where there
is less noise. Noisy traces beneath the IC are not
termined by the RDS(ON), reversing transfer capacitance
recommended. Below is a checklist for your layout:
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
22
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APW8823
Application Information (Cont.)
Layout Consideration (Cont.)
•
3mm
Keep the switching nodes (UGATEx, LGATEx, BOOTx,
and PHASEx) away from sensitive small signal nodes
(ILIMx, and FBx) since these nodes are fast moving
signals. Therefore, keep traces to these nodes as
short as possible and there should be no other weak
signal traces in parallel with theses traces on any layer.
The signals going through theses traces have both
1.66 mm
•
0.5mm *
0.2mm
high dv/dt and high di/dt, with high peak charging and
discharging current. The traces from the gate drivers
•
to the MOSFETs (UGATEx and LGATEx) should be short
and wide.
1.66 mm
0.17mm
0.5mm
Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of
•
3mm
0.4mm
TQFN3x3-20
* Just Recommend
the node.
Decoupling capacitor, the resistor dividers, boot
capacitors, and current-limit stetting resistor should
be close to their pins. (For example, place the
decoupling ceramic capacitor near the drain of the
high-side MOSFET as close as possible. The bulk
•
capacitors are also placednear the drain).
The input capacitor should be near the drain of the
upper MOSFET; the high quality ceramic decoupling
capacitor can be put close to the VCC and GND pins;
the output capacitor should be near the loads. The
input capacitor GND should be close to the output ca-
•
pacitor GND and the lower MOSFET GND.
The drain of the MOSFETs (VIN and PHASEx nodes)
should be a large plane for heat sinking. And PHASEx
pin traces are also the return path for UGATEx. Con-
•
nect these pins to the respective converter’s upper
MOSFET source.
The controller used ripple mode control. Build the resistor divider close to the FB1 pin so that the high
impedance trace is shorter when the output voltage is
in ad justable mode. And the FB1 pin traces can’t be
•
close to the switching signal traces (UGATEx, LGATEx,
BOOTx, and PHASEx).
The PGND trace should be a separate trace, and independently go to the source of the low-side MOSFETs
for current-limit accuracy.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
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APW8823
Package Information
TQFN3x3-20
D
E
b
A
Pin 1
A1
A3
D2
NX
aaa C
L K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
TQFN3x3-20
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.031
A1
0.00
0.05
0.000
0.002
A3
0.20 REF
0.008 REF
b
0.15
0.25
0.006
0.010
D
2.90
3.10
0.114
0.122
0.071
D2
1.50
1.80
0.059
E
2.90
3.10
0.114
0.122
1.80
0.059
0.071
0.50
0.012
E2
1.50
e
0.40 BSC
L
0.30
K
0.20
0.016 BSC
0.008
0.08
aaa
0.020
0.003
Note : 1. Followed from JEDEC MO-220 WEEE
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
24
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APW8823
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN3x3 -20
A
H
T1
C
d
D
330±2.00
50 MIN.
12.4+2.00
-0.00
1 3.0+0 .50
-0 .20
1.5 MIN.
20 .2 MIN.
P0
P1
P2
D0
D1
2.0±0.05
1.5+0.10
-0.00
4.0±0.10
8 .0 ±0 .1 0
1.5 MIN.
T
0.6+0.00
-0.40
W
E1
1 2.0 ±0 .3 0 1 .7 5±0.10
F
5.5±0.05
A0
B0
K0
3 .30 ±0 .2 0
3.30±0.20
1 .0 0±0.2 0
(mm)
Devices Per Unit
Package Type
TQFN3x3-20
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
Unit
Tape & Reel
Quantity
3000
25
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APW8823
Taping Direction Information
TQFN3x3-20
USER DIRECTION OF FEED
Classification Profile
Supplier Tp≧Tc
User Tp≦Tc
TC
TC -5oC
User tp
Supplier tp
Tp
tp
Temperature
Max. Ramp Up Rate = 3oC/s
Max. Ramp Down Rate = 6oC/s
TL
Tsmax
TC -5oC
t
Preheat Area
Tsmin
tS
25
Time 25oC to Peak
Time
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APW8823
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Jan., 2016
27
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APW8823
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
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