HFA1113 Data Sheet February 1999 850MHz, Low Distortion, Output Limiting, Programmable Gain, Buffer Amplifier The HFA1113 is a high speed Buffer featuring user programmable gain and output limiting coupled with ultra high speed performance. This buffer is the ideal choice for high frequency applications requiring output limiting, especially those needing ultra fast overload recovery times. The output limiting function allows the designer to set the maximum positive and negative output levels, thereby protecting later stages from damage or input saturation. The sub-nanosecond overdrive recovery time quickly returns the amplifier to linear operation following an overdrive condition. A unique feature of the pinout allows the user to select a voltage gain of +1, -1, or +2, without the use of any external components, as described in the “Application Information” section. Compatibility with existing op amp pinouts provides flexibility to upgrade low gain amplifiers, while decreasing component count. Unlike most buffers, the standard pinout provides an upgrade path should a higher closed loop gain be needed at a future date. File Number 1342.5 Features • User Programmable Output Voltage Limiting • User Programmable For Closed-Loop Gains of +1, -1 or +2 Without Use of External Resistors • Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 850MHz • Excellent Gain Flatness (to 100MHz). . . . . . . . . . ±0.07dB • Low Differential Gain and Phase . . . 0.02%/0.04 Degrees • Low Distortion (HD3, 30MHz). . . . . . . . . . . . . . . . . -73dBc • Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . 2400V/µs • Fast Settling Time (0.1%) . . . . . . . . . . . . . . . . . . . . . 13ns • High Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 60mA • Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V • Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . <1ns • Standard Operational Amplifier Pinout Applications Component and composite video systems will also benefit from this buffer’s performance, as indicated by the excellent gain flatness, and 0.02%/0.04 Degree Differential Gain/Phase specifications (RL = 150Ω). • RF/IF Processors For Military product, refer to the HFA1113/883 data sheet. • Impedance Transformation • Driving Flash A/D Converters • High-Speed Communications • Line Driving Ordering Information • Video Switching and Routing PART NUMBER (BRAND) TEMP. RANGE (oC) HFA1113IB (H1113I) -40 to 85 HFA11XXEVAL PACKAGE 8 Ld SOIC PKG. NO. M8.15 DIP Evaluation Board For High Speed Op Amps Pinout HFA1113 (SOIC) TOP VIEW NC 300 1 • Radar Systems • Medical Imaging Systems Pin Descriptions NAME PIN NUMBER NC 1 No Connection -IN 2 Inverting Input DESCRIPTION +IN 3 Non-Inverting Input 8 VH V- 4 Negative Supply 7 V+ VL 5 Lower Output Limit OUT 6 Output V+ 7 Positive Supply VH 8 Upper Output Limit 300 -IN 2 - + +IN 3 6 OUT V- 4 5 VL 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HFA1113 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Voltage at VH or VL Terminal . . . . . . . . . . . . . . (V+) + 2V to (V-) - 2V Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . 60mA Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified Electrical Specifications TEMP. (oC) MIN TYP MAX UNITS 25 - 8 25 mV Full - - 35 mV Output Offset Voltage Drift Full - 10 - µV/oC PSRR 25 39 45 - dB Full 35 - - dB PARAMETER TEST CONDITIONS INPUT CHARACTERISTICS Output Offset Voltage Input Noise Voltage (Note 3) 100kHz 25 - 9 - nV/√Hz +Input Noise Current (Note 3) 100kHz 25 - 37 - pA/√Hz 25 - 25 40 µA Full - - 65 µA Non-Inverting Input Resistance 25 25 50 - kΩ Inverting Input Resistance (Note 2) 25 240 300 360 Ω Input Capacitance 25 - 2 - pF Input Common Mode Range Full ±2.5 ±2.8 - V 25 0.980 0.990 1.020 V/V Full 0.975 - 1.025 V/V 25 1.96 1.98 2.04 V/V Full 1.95 - 2.05 V/V AV = +2, ±2V Full Scale 25 - 0.02 - % AV = -1 25 ±3.0 ±3.3 - V Full ±2.5 ±3.0 - V 25, 85 50 60 - mA -40 35 50 - mA 25 - 0.3 - Ω Supply Voltage Range Full ±4.5 - ±5.5 V Supply Current (Note 3) 25 - 21 26 mA Full - - 33 mA Non-Inverting Input Bias Current TRANSFER CHARACTERISTICS AV = +1, VIN = +2V Gain AV = +2, VIN = +1V DC Non-Linearity (Note 3) OUTPUT CHARACTERISTICS Output Voltage (Note 3) RL = 50Ω Output Current (Note 3) Closed Loop Output Impedance DC, AV = +2 POWER SUPPLY CHARACTERISTICS 2 HFA1113 VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER TEMP. (oC) MIN TYP MAX UNITS AV = -1 25 450 800 - MHz AV = +1 25 500 850 - MHz AV = +2 25 350 550 - MHz TEST CONDITIONS AC CHARACTERISTICS -3dB Bandwidth (VOUT = 0.2VP-P, Notes 2, 3) AV = -1 25 1500 2400 - V/µs AV = +1 25 800 1500 - V/µs AV = +2 25 1100 1900 - V/µs AV = -1 25 - 300 - MHz AV = +1 25 - 150 - MHz AV = +2 25 - 220 - MHz AV = -1 25 - ±0.02 - dB AV = +1 25 - ±0.1 - dB AV = +2 25 - ±0.015 ±0.04 dB AV = -1 25 - ±0.05 - dB AV = +1 25 - ±0.2 - dB AV = +2 25 - ±0.036 ±0.08 dB Gain Flatness (to 100MHz, Notes 2, 3) AV = -1 25 - ±0.10 - dB AV = +2 25 - ±0.07 ±0.22 dB Linear Phase Deviation (to 100MHz, Note 3) AV = -1 25 - ±0.13 - Degrees AV = +1 25 - ±0.83 - Degrees AV = +2 25 - ±0.05 - Degrees 2nd Harmonic Distortion (30MHz, VOUT = 2VP-P, Notes 2, 3) AV = -1 25 - -52 - dBc AV = +1 25 - -57 - dBc AV = +2 25 - -52 -45 dBc AV = -1 25 - -71 - dBc AV = +1 25 - -73 - dBc AV = +2 25 - -72 -65 dBc AV = -1 25 - -47 - dBc AV = +1 25 - -53 - dBc AV = +2 25 - -47 -40 dBc AV = -1 25 - -63 - dBc AV = +1 25 - -68 - dBc AV = +2 25 - -65 -55 dBc AV = -1 25 - -41 - dBc AV = +1 25 - -50 - dBc AV = +2 25 - -42 -35 dBc Slew Rate (VOUT = 5VP-P, Note 2) Full Power Bandwidth (VOUT = 5VP-P, Note 3) Gain Flatness (to 30MHz, Notes 2, 3) Gain Flatness (to 50MHz, Notes 2, 3) 3rd Harmonic Distortion (30MHz, VOUT = 2VP-P, Notes 2, 3) 2nd Harmonic Distortion (50MHz, VOUT = 2VP-P, Notes 2, 3) 3rd Harmonic Distortion (50MHz, VOUT = 2VP-P, Notes 2, 3) 2nd Harmonic Distortion (100MHz, VOUT = 2VP-P, Notes 2, 3) 3rd Harmonic Distortion (100MHz, VOUT = 2VP-P , Notes 2, 3) 3 AV = -1 25 - -55 - dBc AV = +1 25 - -49 - dBc AV = +2 25 - -62 -45 dBc HFA1113 VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER TEST CONDITIONS TEMP. (oC) MIN TYP MAX UNITS 3rd Order Intercept (AV = +2, Note 3) 100MHz 25 - 28 - dBm 300MHz 25 - 13 - dBm 1dB Compression (AV = +2, Note 3) 100MHz 25 - 19 - dBm 300MHz 25 - 12 - dBm Reverse Isolation (S12, Note 3) 40MHz 25 - -70 - dB 100MHz 25 - -60 - dB 600MHz 25 - -32 - dB AV = -1 25 - 500 800 ps AV = +1 25 - 480 750 ps AV = +2 25 - 700 1000 ps AV = -1 25 - 0.82 - ns AV = +1 25 - 1.06 - ns AV = +2 25 - 1.00 - ns AV = -1 25 - 12 30 % AV = +1 25 - 45 65 % AV = +2 25 - 6 20 % 0.1% Settling Time (Note 3) VOUT = 2V to 0V 25 - 13 20 ns 0.05% Settling Time VOUT = 2V to 0V 25 - 20 33 ns Differential Gain AV = +1, 3.58MHz, RL = 150Ω 25 - 0.03 - % AV = +2, 3.58MHz, RL = 150Ω 25 - 0.02 - % AV = +1, 3.58MHz, RL = 150Ω 25 - 0.05 - Degrees AV = +2, 3.58MHz, RL = 150Ω 25 - 0.04 - Degrees TRANSIENT CHARACTERISTICS Rise Time (VOUT = 0.5V Step, Note 2) Rise Time (VOUT = 2V Step) Overshoot (VOUT = 0.5V Step, Input tR/tF = 200ps, Notes 2, 3, 4) Differential Phase OUTPUT LIMITING CHARACTERISTICS AV = +2, VH = +1V, VL = -1V, Unless Otherwise Specified VIN = ±1.6V, AV = -1 Clamp Accuracy (Note 3) 25 - ±100 ±150 mV Full - - ±200 mV Clamp Overshoot VIN = ±1V, Input tR/tF = 500ps 25 - 7 - % Overdrive Recovery Time (Note 3) VIN = ±1V 25 - 0.75 1.5 ns Negative Clamp Range 25 - -5.0 to +2.0 - V Positive Clamp Range 25 - -2.0 to +5.0 - V Clamp Input Bias Current (Note 3) 25 - 50 200 µA Full - - 300 µA 25 - 500 - MHz VH or VL = 100mVP-P Clamp Input Bandwidth (Note 3) NOTES: 2. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-lot variation. 3. See Typical Performance Curves for more information. 4. Overshoot decreases as input transition times increase, especially for AV = +1. Please refer to Typical Performance Curves. 4 HFA1113 Application Information avoided by placing a resistor (RS) in series with the output prior to the capacitance. Closed Loop Gain Selection The HFA1113 features a novel design which allows the user to select from three closed loop gains, without any external components. The result is a more flexible product, fewer part types in inventory, and more efficient use of board space. This “buffer” operates in closed loop gains of -1, +1, or +2, and gain selection is accomplished via connections to the ±Inputs. Applying the input signal to +IN and floating -IN selects a gain of +1, while grounding -IN selects a gain of +2. A gain of -1 is obtained by applying the input signal to -IN with +IN grounded. The table below summarizes these connections: CONNECTIONS Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 850MHz. By decreasing RS as CLincreases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. Even so, bandwidth does decrease as you move to the right along the curve. For example, at AV = +1, RS = 50Ω, CL = 30pF, the overall bandwidth is limited to 300MHz, and bandwidth drops to 100MHz at AV = +1, RS = 5Ω, CL = 340pF. GAIN (ACL) +INPUT (PIN 3) -INPUT (PIN 2) -1 GND Input +1 Input NC (Floating) 50 +2 Input GND 45 AV = +1 40 35 The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! 30 Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value chip (0.1µF) capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. For unity gain applications, care must also be taken to minimize the capacitance to ground seen by the amplifier’s inverting input. At higher frequencies this capacitance will tend to short the -INPUT to GND, resulting in a closed loop gain which increases with frequency. This will cause excessive high frequency peaking and potentially other problems as well. An example of a good high frequency layout is the Evaluation Board shown in Figure 3. Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be 5 RS (Ω) PC Board Layout 25 20 15 10 5 AV = +2 0 0 40 80 120 160 200 240 280 320 360 400 LOAD CAPACITANCE (pF) FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD CAPACITANCE Evaluation Board The performance of the HFA1113 may be evaluated using the HFA11XX Evaluation Board, slightly modified as follows: 1. Remove the 500Ω feedback resistor (R2), and leave the connection open. 2. a. For AV = +1 evaluation, remove the 500Ω gain setting resistor (R1), and leave pin 2 floating. b. For AV = +2, replace the 500Ω gain setting resistor with a 0Ω resistor to GND. The modified schematic and layout of the board are shown in Figures 2 and 3. To order evaluation boards (part number HFA11XXEVAL), please contact your local sales office. NOTE: The SOIC version may be evaluated in the DIP board by using a SOIC-to-DIP adapter such as Aries Electronics Part Number 08-350000-10. HFA1113 ∞ (AV = +1) . between the positive and negative inputs. This buffer forces -IN to track +IN, and sets up a slewing current of: OR 0Ω (AV = +2) VH R1 50Ω 1 8 2 7 3 6 4 5 (V-IN - VOUT)/RF + V-IN/RG 0.1µF 10µF +5V 50Ω IN 0µF 0.1µF OUT VL GND GND -5V FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC TOP LAYOUT This current is mirrored onto the high impedance node (Z) by QX3-QX4, where it is converted to a voltage and fed to the output via another unity gain buffer. If no clamping is utilized, the high impedance node may swing within the limits defined by QP4 and QN4. Note that when the output reaches its quiescent value, the current flowing through -IN is reduced to only that small current (-IBIAS) required to keep the output at the final voltage. Tracing the path from VH to Z illustrates the effect of the clamp voltage on the high impedance node. VH decreases by 2VBE (QN6 and QP6) to set up the base voltage on QP5. V+ VH QP3 50K (30K FOR VL ) QP4 1 +IN QN2 OUT V+ VL VGND QP1 +IN R1 Z ICLAMP +1 VV+ 200Ω QN1 QN5 BOTTOM LAYOUT QP2 QP6 QN3 QN4 V300Ω VH QN6 QP5 V-IN RG (INTERNAL) RF = 300Ω (INTERNAL) -IN VOUT FIGURE 4. HFA1113 SIMPLIFIED VH CLAMP CIRCUITRY FIGURE 3. EVALUATION BOARD LAYOUT Limiting Operation General The HFA1113 features user programmable output clamps to limit output voltage excursions. Clamping action is obtained by applying voltages to the VH and VL terminals (pins 8 and 5) of the amplifier. VH sets the upper output limit, while VL sets the lower clamp level. If the amplifier tries to drive the output above VH, or below VL, the clamp circuitry limits the output voltage at VH or VL (± the clamp accuracy), respectively. The low input bias currents of the clamp pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or DACs. Clamp Circuitry Figure 4 shows a simplified schematic of the HFA1113 input stage, and the high clamp (VH) circuitry. As with all current feedback amplifiers, there is a unity gain buffer (QX1 - QX2) 6 QP5 begins to conduct whenever the high impedance node reaches a voltage equal to QP5’s base voltage + 2VBE (QP5 and QN5). Thus, QP5 clamps node Z whenever Z reaches VH. R1 provides a pull-up network to ensure functionality with the clamp inputs floating. A similar description applies to the symmetrical low clamp circuitry controlled by VL. When the output is clamped, the negative input continues to source a slewing current (ICLAMP) in an attempt to force the output to the quiescent voltage defined by the input. QP5 must sink this current while clamping, because the -IN current is always mirrored onto the high impedance node. The clamping current is calculated as: ICLAMP = (V-IN - VOUT CLAMPED)/300Ω + V-IN/RG. As an example, a unity gain circuit with VIN = 2V, and VH = 1V, would have ICLAMP = (2V - 1V)/300Ω + 2V/∞ = 3.33mA (RG = ∞ because -IN is floated for unity gain applications). Note that ICC will increase by ICLAMP when the output is clamp limited. HFA1113 Clamp Accuracy The clamped output voltage will not be exactly equal to the voltage applied to VH or VL. Offset errors, mostly due to VBE mismatches, necessitate a clamp accuracy parameter which is found in the device specifications. Clamp accuracy is a function of the clamping conditions. Referring again to Figure 4, it can be seen that one component of clamp accuracy is the VBE mismatch between the QX6 transistors, and the QX5 transistors. If the transistors always ran at the same current level there would be no VBE mismatch, and no contribution to the inaccuracy. The QX6 transistors are biased at a constant current, but as described earlier, the current through QX5 is equivalent to ICLAMP. VBE increases as ICLAMP increases, causing the clamped output voltage to increase as well. ICLAMP is a function of the overdrive level (AVCL x VIN - VOUT CLAMPED), so clamp accuracy degrades as the overdrive increases. As an example, the specified accuracy of ±100mV (AV = -1, VH = 1V) for a 1.6X overdrive degrades to ±240mV for a 3X (200%) overdrive, as shown in Figure 43. Consideration must also be given to the fact that the clamp voltages have an affect on amplifier linearity. The “Nonlinearity Near Clamp Voltage” curve, Figure 48, illustrates the impact of several clamp levels on linearity. Clamp Range Unlike some competitor devices, both VH and VL have usable ranges that cross 0V. While VH must be more positive than VL , both may be positive or negative, within the range Typical Performance Curves restrictions indicated in the specifications. For example, the HFA1113 could be limited to ECL output levels by setting VH = -0.8V and VL = -1.8V. VH and VL may be connected to the same voltage (GND for instance) but the result won’t be in a DC output voltage from an AC input signal. A 150mV - 200mV AC signal will still be present at the output. Recovery from Overdrive The output voltage remains at the clamp level as long as the overdrive condition remains. When the input voltage drops below the overdrive level (VCLAMP/AVCL) the amplifier will return to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear operation. The plots of “Unclamped Performance” and “Clamped Performance” (Figures 41 and 42) highlight the HFA1113’s subnanosecond recovery time. The difference between the unclamped and clamped propagation delays is the overdrive recovery time. The appropriate propagation delays are 8.0ns for the unclamped pulse, and 8.8ns for the clamped (2X overdrive) pulse yielding an overdrive recovery time of 800ps. The measurement uses the 90% point of the output transition to ensure that linear operation has resumed. Note: The propagation delay illustrated is dominated by the fixturing. The delta shown is accurate, but the true HFA1113 propagation delay is 500ps. Overdrive recovery time is also a function of the overdrive level. Figure 47 details the overdrive recovery time for various clamp and overdrive levels. VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified 200 2.0 AV = +2 150 1.5 100 1.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) AV = +2 50 0 -50 -100 -150 0.5 0 -0.5 -1.0 -1.5 -200 -2.0 TIME (5ns/DIV.) FIGURE 5. SMALL SIGNAL PULSE RESPONSE 7 TIME (5ns/DIV.) FIGURE 6. LARGE SIGNAL PULSE RESPONSE HFA1113 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 2.0 200 AV = +1 AV = +1 1.5 100 OUTPUT VOLTAGE (V) 50 0 -50 -100 -150 1.0 0.5 0 -0.5 -1.0 -1.5 -200 -2.0 TIME (5ns/DIV.) TIME (5ns/DIV.) FIGURE 7. SMALL SIGNAL PULSE RESPONSE FIGURE 8. LARGE SIGNAL PULSE RESPONSE 200 2.0 AV = -1 AV = -1 1.5 100 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) 150 50 0 -50 -100 1.0 0.5 0 -0.5 -1.0 -150 -1.5 -200 -2.0 TIME (5ns/DIV.) TIME (5ns/DIV.) FIGURE 10. LARGE SIGNAL PULSE RESPONSE 6 VOUT = 200mVP-P AV = +2, VOUT = 200mVP-P AV = +1 GAIN 9 0 AV = -1 AV = +2 -3 PHASE -6 0 -9 AV = +2 AV = -1 AV = +1 -90 -180 -270 -360 0.3 1 10 100 FREQUENCY (MHz) FIGURE 11. FREQUENCY RESPONSE 8 1000 GAIN (dB) 3 NORMALIZED PHASE (DEGREES) NORMALIZED GAIN (dB) FIGURE 9. SMALL SIGNAL PULSE RESPONSE GAIN 6 3 RL = 50Ω RL = 100Ω RL = 1kΩ 0 PHASE 0 RL = 100Ω RL = 50Ω RL = 1kΩ 0.3 1 10 100 FREQUENCY (MHz) -90 -180 -270 -360 1000 FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS PHASE (DEGREES) OUTPUT VOLTAGE (mV) 150 HFA1113 Typical Performance Curves GAIN 0 RL = 1kΩ -3 RL = 100Ω -6 RL = 50Ω -90 RL = 100Ω -180 RL = 50Ω -270 RL = 1kΩ 1 -360 1000 10 100 FREQUENCY (MHz) 0 -90 4.0VP-P 2.5VP-P 1VP-P -180 -270 -360 10 100 FREQUENCY (MHz) GAIN (dB) 0 VOUT = 4VP-P -3 VOUT = 2.5VP-P -90 VOUT = 4VP-P 90 0 -90 -180 10 100 FREQUENCY (MHz) PHASE (DEGREES) 180 1 1000 FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES 9 -270 VOUT = 1VP-P -360 1 10 100 FREQUENCY (MHz) 1000 FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES VOUT = 5VP-P 12 PHASE VOUT = 1VP-P -180 VOUT = 2.5VP-P VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P 0 0.3 -6 0.3 GAIN 0 VOUT = 2.5VP-P VOUT = 4VP-P -180 1000 AV = +1 3 1000 VOUT = 1VP-P -3 0 FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS 15 GAIN 10 100 FREQUENCY (MHz) PHASE FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES AV = -1 1 PHASE (DEGREES) PHASE 180 -90 RL = 1kΩ -6 0 3 RL = 50Ω GAIN (dB) 4.0VP-P 2.5VP-P 3 RL = 100Ω 90 NORMALIZED GAIN (dB) GAIN (dB) 1VP-P GAIN 1 PHASE 6 AV = +2 6 6 RL = 50Ω -6 0.3 FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS 0.3 RL = 100Ω PHASE (DEGREES) 0 9 0 -3 PHASE (DEGREES) PHASE 12 RL = 1kΩ GAIN -9 -9 0.3 AV = -1, VOUT = 200mVP-P 3 PHASE (DEGREES) 3 GAIN (dB) 6 AV = +1, VOUT = 200mVP-P GAIN (dB) 6 VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 9 6 3 0 AV = -1 -3 AV = +2 -6 AV = +1 -9 -12 -15 0.3 1 10 FREQUENCY (MHz) 100 FIGURE 18. FULL POWER BANDWIDTH 1000 HFA1113 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 900 0.35 AV = +1 850 AV = -1 NORMALIZED GAIN (dB) BANDWIDTH (MHz) 800 0.30 750 700 650 600 AV = +2 550 0.25 0.20 AV = -1 AV = +1 0.15 0.10 0.05 0 -0.05 AV = +2 -0.10 500 -50 -25 0 25 50 75 100 -0.15 125 1 10 FREQUENCY (MHz) TEMPERATURE (oC) FIGURE 19. -3dB BANDWIDTH vs TEMPERATURE 100 FIGURE 20. GAIN FLATNESS 4 AV = +2, VOUT = 2V 3 0.6 1 AV = -1 0 -1 AV = +2 -2 AV = +1 -3 SETTLING ERROR (%) DEVIATION (DEGREES) 2 0.4 0.2 0.1 0 -0.1 -0.2 -0.4 -0.6 -4 -5 -6 15 30 45 60 75 90 105 120 135 -2 150 3 8 13 FREQUENCY (MHz) 18 23 28 33 38 FIGURE 21. DEVIATION FROM LINEAR PHASE 48 FIGURE 22. SETTLING RESPONSE 235 -24 -30 180 AV = +1 PHASE -36 AV = +1 -42 -24 -54 -30 AV = +2 AV = -1 AV = -1 -60 -66 AV = +2 -72 -78 90 45 AV = -1 -48 GAIN (dB) GAIN (dB) 43 TIME (ns) AV = +2 GAIN AV = +2 0 PHASE (DEGREES) 0 -36 -42 -48 AV = -1 AV = -1 -54 -84 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (MHz) FIGURE 23. LOW FREQUENCY REVERSE ISOLATION (S12) 10 -60 100 190 280 370 460 550 640 730 FREQUENCY (MHz) 820 910 1000 FIGURE 24. HIGH FREQUENCY REVERSE ISOLATION (S12) HFA1113 VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 30 20 2 - TONE 18 AV = -1 16 INTERCEPT POINT (dBm) OUTPUT POWER AT 1dB COMPRESSION (dBm) Typical Performance Curves 14 AV = +2 12 10 8 AV = +1 6 AV = +2 AV = +1 10 4 2 0 100 0 100 200 300 FREQUENCY (MHz) 400 500 FIGURE 25. 1dB GAIN COMPRESSION vs FREQUENCY -30 -40 -40 DISTORTION (dBc) -30 -50 100MHz 30MHz 50MHz -70 -50 -60 -70 -80 -80 -90 -90 30MHz 50MHz 100MHz -100 -100 -6 -3 0 3 6 9 12 15 -6 -3 0 3 OUTPUT POWER (dBm) 6 9 12 15 18 OUTPUT POWER (dBm) FIGURE 27. SECOND HARMONIC DISTORTION vs POUT FIGURE 28. THIRD HARMONIC DISTORTION vs POUT -20 -20 AV = +1 AV = +1 -30 -30 -40 DISTORTION (dBc) -40 DISTORTION (dBc) 400 AV = +2 AV = +2 -60 200 300 FREQUENCY (MHz) FIGURE 26. THIRD ORDER INTERMODULATION INTERCEPT vs FREQUENCY -20 -20 DISTORTION (dBc) AV = -1 20 -50 -60 -70 100MHz 50MHz 30MHz -50 -60 -70 100MHz -80 -80 -90 -90 50MHz 30MHz -100 -100 -6 -3 0 3 6 9 OUTPUT POWER (dBm) 12 FIGURE 29. SECOND HARMONIC DISTORTION vs POUT 11 15 -6 -3 0 3 6 9 OUTPUT POWER (dBm) 12 FIGURE 30. THIRD HARMONIC DISTORTION vs POUT 15 HFA1113 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) -20 -20 AV = -1 -30 -30 -40 -40 DISTORTION (dBc) DISTORTION (dBc) AV = -1 -50 -60 -70 50MHz 100MHz 30MHz -50 -60 -70 -80 -80 -90 -90 30MHz 50MHz 100MHz -100 -100 -6 -3 0 3 6 9 OUTPUT POWER (dBm) 12 -6 15 -3 0 3 6 9 12 15 OUTPUT POWER (dBm) FIGURE 31. SECOND HARMONIC DISTORTION vs POUT FIGURE 32. THIRD HARMONIC DISTORTION vs POUT 60 0.04 VOUT = 0.5V 0.02 OVERSHOOT (%) PERCENT ERROR (%) 50 0 AV = +1 40 30 20 -0.02 AV = -1 10 AV = +2 0 -0.04 -3.0 -2.0 -1.0 0 1.0 INPUT VOLTAGE (V) 2.0 100 3.0 500 700 900 1100 1300 INPUT RISE TIME (ps) FIGURE 33. INTEGRAL LINEARITY ERROR FIGURE 34. OVERSHOOT vs INPUT RISE TIME 60 60 VOUT = 1V VOUT = 2V 50 50 OVERSHOOT (%) OVERSHOOT (%) 300 40 AV = +1 30 20 40 30 AV = -1 20 AV = -1 10 AV = +1 AV = +2 10 AV = +2 0 100 300 500 700 900 INPUT RISE TIME (ps) 1100 FIGURE 35. OVERSHOOT vs INPUT RISE TIME 12 1300 0 100 300 500 700 900 INPUT RISE TIME (ps) 1100 FIGURE 36. OVERSHOOT vs INPUT RISE TIME 1300 HFA1113 VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 25 24 SUPPLY CURRENT (mA) 23 22 21 20 19 18 17 16 5 6 7 8 9 TOTAL SUPPLY VOLTAGE (V+ - V-, V) 15 10 -50 FIGURE 37. SUPPLY CURRENT vs SUPPLY VOLTAGE AV = -1 OUTPUT VOLTAGE (V) 3.3 3.2 NOISE VOLTAGE (nV/√Hz) +VOUT (RL= 50Ω) 3.4 +VOUT (RL= 100Ω) |-VOUT| (RL= 100Ω) 3.1 3.0 2.9 2.8 |-VOUT| (RL= 50Ω) 0 25 50 75 TEMPERATURE (oC) 100 125 FIGURE 38. SUPPLY CURRENT vs TEMPERATURE 3.6 3.5 -25 50 130 40 110 30 90 20 70 ENI 50 10 INI 2.7 2.6 0 -50 -25 0 25 50 75 TEMPERATURE (oC) 100 125 0.1 FIGURE 39. OUTPUT VOLTAGE vs TEMPERATURE 1 10 FREQUENCY (kHz) FIGURE 40. INPUT NOISE CHARACTERISTICS AV = +2 IN 0V TO 0.5V IN 0V TO 1V OUT 0V TO 1V OUT 0V TO 1V TIME (20ns/DIV.) FIGURE 41. UNCLAMPED PERFORMANCE 13 30 100 AV = +2 TIME (20ns/DIV.) FIGURE 42. CLAMPED PERFORMANCE NOISE CURRENT (pA/√Hz) SUPPLY CURRENT (mA) Typical Performance Curves HFA1113 Typical Performance Curves 350 VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 250 AV = ±1 AV = ±1 VL = -500mV VH = 500mV CLAMP ACCURACY (mV) CLAMP ACCURACY (mV) 300 250 VH = 1V 200 150 VH = 2V 100 VH = 100mV 200 VL = -1V 150 100 VL = -2V 50 50 VL = -100mV 0 0 0 100 200 300 400 100 0 500 OVERDRIVE (% OF VH) FIGURE 43. VH CLAMP ACCURACY vs OVERDRIVE 400 500 250 AV = ±2 AV = +2 VH = 1V 300 CLAMP ACCURACY (mV) CLAMP ACCURACY (mV) 300 FIGURE 44. VL CLAMP ACCURACY vs OVERDRIVE 400 VH = 2V 200 VH = 500mV 100 VH = 100mV VL = -1V 200 VL = -500mV 150 VL = -2V 100 50 VL = -100mV 0 0 100 200 300 400 0 500 0 100 OVERDRIVE (% OF VH) FIGURE 45. VH CLAMP ACCURACY vs OVERDRIVE 3500 20 3000 15 V H = 2V 2000 1500 V H = 1V 1000 V H = 0.5V 500 0 100 400 500 AV = -1 VL = -3V 2500 200 300 OVERDRIVE (% OF VL) FIGURE 46. VL CLAMP ACCURACY vs OVERDRIVE VOUT - (AV x VIN) (mV) OVERDRIVE RECOVERY TIME (ps) 200 OVERDRIVE (% OF VL) VL = -2V VL = -1V 10 5 0 -5 VH = 1V -10 VH = 2V VH = 3V -15 V H = 0.1V -20 200 300 400 OVERDRIVE LEVEL (% OF CLAMP LEVEL) FIGURE 47. OVERDRIVE RECOVERY vs OVERDRIVE 14 500 -3 -2 -1 0 AV x VIN (V) 1 2 FIGURE 48. NON-LINEARITY NEAR CLAMP VOLTAGE 3 HFA1113 Typical Performance Curves 140 130 AV = -1, VIN = ±1.6V VH = 1V, VL = -1V VH = 1V, VL = -1V 120 CLAMP BIAS CURRENT (µA) 130 CLAMP ACCURACY (mV) VSUPPLY = ±5V, TA = 25oC, RL = 100Ω, Unless Otherwise Specified (Continued) 120 VH 110 100 90 VL 80 70 110 100 90 VL 80 70 60 VH 50 40 30 60 -75 -50 -25 0 25 50 75 100 125 20 -75 150 -50 -25 75 25 0 50 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 49. CLAMP ACCURACY vs TEMPERATURE 125 6 VH = 300mVP-P 0 -3 -6 0 -3 -6 VL = 600mVP-P VH = 600mVP-P VH = 1.2VP-P -9 VL = 300mVP-P 3 GAIN (dB) 3 -9 VL = 1.2VP-P -12 -12 1 10 100 FREQUENCY (MHz) 1000 FIGURE 51. VH CLAMP INPUT BANDWIDTH 15 150 FIGURE 50. CLAMP BIAS CURRENT vs TEMPERATURE 6 GAIN (dB) 100 1 10 100 FREQUENCY (MHz) 1000 FIGURE 52. VL CLAMP INPUT BANDWIDTH HFA1113 Die Characteristics DIE DIMENSIONS: PASSIVATION: 63 mils x 44 mils x 19 mils 1600µm x 1130µm x 483µm Type: Nitride Thickness: 4kÅ ±0.5kÅ TRANSISTOR COUNT: METALLIZATION: 52 Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ SUBSTRATE POTENTIAL (POWERED UP): Floating (Recommend Connection to V-) Metallization Mask Layout HFA1113 NC +IN V- VL -IN VH NC V+ OUT 16 HFA1113 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- e α A1 B 0.25(0.010) M C A M MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e C 0.10(0.004) B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MILLIMETERS MIN 0.050 BSC 1.27 BSC 0.2284 0.2440 h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 5.80 - H 8 0o 6.20 - 8 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 17 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029