HFA1135 TM Data Sheet June 2000 360MHz, Low Power, Video Operational Amplifier with Output Limiting The HFA1135 is a high speed, low power current feedback amplifier build with Intersil’s proprietary complementary bipolar UHF-1 process. This amplifier features user programmable output limiting, via the VH and VL pins. The HFA1135 is the ideal choice for high speed, low power applications requiring output limiting (e.g. flash A/D drivers), especially those requiring fast overdrive recovery times. The limiting function allows the designer to set the maximum and minimum output levels to protect downstream stages from damage or input saturation. The sub-nanosecond overdrive recovery time ensures a quick return to linear operation following an overdrive condition. Component and composite video systems also benefit from this operational amplifier’s performance, as indicated by the gain flatness, and differential gain and phase specifications. File Number Features • User Programmable Output Voltage Limiting • Fast Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . <1ns • Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . 6.8mA • High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 2MΩ • Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . . 360MHz • Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . . 1200V/µs • Gain Flatness (to 50MHz) . . . . . . . . . . . . . . . . . . ±0.07dB • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02% • Differential Phase . . . . . . . . . . . . . . . . . . . . 0.04 Degrees • Pin Compatible Upgrade to CLC501 and CLC502 Applications • Flash A/D Drivers The HFA1135 is a low power, high performance upgrade for the CLC501 and CLC502. • High Resolution Monitors Ordering Information • Video Digitizing Boards/Systems PART NUMBER (BRAND) TEMP. RANGE (oC) PKG. NO. PACKAGE HFA1135IB (H1135I) -40 to 85 8 Ld SOIC M8.15 HFA1135IB96 (H1135I) -40 to 85 8 Ld SOIC Tape and Reel M8.15 HFA11XXEVAL DIP Evaluation Board for High Speed Op Amps 3653.5 • Professional Video Processing • Multimedia Systems • RGB Preamps • Medical Imaging • Hand Held and Miniaturized RF Equipment • Battery Powered Communications Pinout HFA1135 (SOIC) TOP VIEW 1 NC 1 -IN 2 +IN 3 V- 4 + 8 VH 7 V+ 6 OUT 5 VL CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HFA1135 Absolute Maximum Ratings TA = 25oC Thermal Information Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V Output Current (Note 1) . . . . . . . . . . . . . . . . .Short Circuit Protected 30mA Continuous 60mA ≤ 50% Duty Cycle ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >600V Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Maximum Junction Temperature (Die Only) . . . . . . . . . . . . . . . .175oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. VSUPPLY = ±5V, AV = +1, RF = 510Ω (Note 3), RL = 100Ω, Unless Otherwise Specified Electrical Specifications PARAMETER TEST CONDITIONS (NOTE 2) TEST LEVEL TEMP. (oC) MIN TYP MAX UNITS INPUT CHARACTERISTICS Input Offset Voltage A 25 - 2 5 mV A Full - 3 8 mV B Full - 1 10 µV/oC ∆VCM = ±1.8V A 25 47 50 - dB ∆VCM = ±1.8V A 85 45 48 - dB ∆VCM = ±1.2V A -40 45 48 - dB ∆VPS = ±1.8V A 25 50 54 - dB ∆VPS = ±1.8V A 85 47 50 - dB Average Input Offset Voltage Drift Input Offset Voltage Common-Mode Rejection Ratio Input Offset Voltage Power Supply Rejection Ratio ∆VPS = ±1.2V A -40 47 50 - dB Non-Inverting Input Bias Current A 25 - 6 15 µA A Full - 10 25 µA Non-Inverting Input Bias Current Drift B Full - 5 60 nA/oC ∆VPS = ±1.8V A 25 - 0.5 1 µA/V ∆VPS = ±1.8V A 85 - 0.8 3 µA/V ∆VPS = ±1.2V A -40 - 0.8 3 µA/V ∆VCM = ±1.8V A 25 0.8 2 - MΩ ∆VCM = ±1.8V A 85 0.5 1.3 - MΩ ∆VCM = ±1.2V A -40 0.5 1.3 - MΩ Non-Inverting Input Bias Current Power Supply Sensitivity Non-Inverting Input Resistance A 25 - 0.1 4 µA A Full - 3 8 µA B Full - 60 200 nA/oC ∆VCM = ±1.8V A 25 - 3 6 µA/V ∆VCM = ±1.8V A 85 - 4 8 µA/V ∆VCM = ±1.2V A -40 - 4 8 µA/V ∆VPS = ±1.8V A 25 - 2 5 µA/V ∆VPS = ±1.8V A 85 - 4 8 µA/V Inverting Input Bias Current Inverting Input Bias Current Drift Inverting Input Bias Current Common-Mode Sensitivity Inverting Input Bias Current Power Supply Sensitivity A -40 - 4 8 µA/V Inverting Input Resistance ∆VPS = ±1.2V C 25 - 40 - Ω Input Capacitance (Either Input) C 25 - 1.6 - pF 2 HFA1135 VSUPPLY = ±5V, AV = +1, RF = 510Ω (Note 3), RL = 100Ω, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER TEST CONDITIONS Input Voltage Common Mode Range (Implied by VIO CMRR, +RIN, and -IBIAS CMS tests) (NOTE 2) TEST LEVEL TEMP. (oC) MIN TYP MAX UNITS A 25, 85 ±1.8 ±2.4 - V A -40 ±1.2 ±1.7 - V Input Noise Voltage Density (Note 5) f = 100kHz B 25 - 3.5 - nV/√Hz Non-Inverting Input Noise Current Density (Note 5) f = 100kHz B 25 - 2.5 - pA/√Hz Inverting Input Noise Current Density (Note 5) f = 100kHz B 25 - 20 - pA/√Hz AV = -1 C 25 - 500 - kΩ AV = +1, RF = 1.5kΩ B 25 - 660 - MHz AV = +2, RF = 250Ω B 25 - 360 - MHz AV = +2, RF = 330Ω B 25 - 315 - MHz AV = -1, RF = 330Ω B 25 - 290 - MHz Full Power Bandwidth (VOUT = 5VP-P at AV = +2/-1, 4VP-P at AV = +1, Note 5) AV = +1, RF = 1.5kΩ B 25 - 90 - MHz AV = +2, RF = 250Ω B 25 - 130 - MHz AV = -1, RF = 330Ω B 25 - 170 - MHz Gain Flatness (to 25MHz, VOUT = 0.2VP-P, Note 5) AV = +1, RF = 1.5kΩ B 25 - ±0.10 - dB AV = +2, RF = 250Ω B 25 - ±0.02 - dB AV = +2, RF = 330Ω B 25 - ±0.02 - dB AV = +1, RF = 1.5kΩ B 25 - ±0.22 - dB AV = +2, RF = 250Ω B 25 - ±0.07 - dB AV = +2, RF = 330Ω B 25 - ±0.03 - dB A Full - 1 - V/V 25 ±3 ±3.4 - V TRANSFER CHARACTERISTICS Open Loop Transimpedance Gain (Note 5) AC CHARACTERISTICS AV = +2, RF = 250Ω, Unless Otherwise Specified -3dB Bandwidth (VOUT = 0.2VP-P, Note 5) Gain Flatness (to 50MHz, VOUT = 0.2VP-P, Note 5) Minimum Stable Gain OUTPUT CHARACTERISTICS RF = 510Ω, Unless Otherwise Specified Output Voltage Swing (Note 5) AV = -1, RL = 100Ω A A Full ±2.8 ±3 - V Output Current (Note 5) AV = -1, RL = 50Ω A 25, 85 50 60 - mA A -40 28 42 - mA B 25 - 90 - mA Output Short Circuit Current Closed Loop Output Resistance (Note 5) DC, AV = +2, RF = 250Ω B 25 - 0.07 - Ω Second Harmonic Distortion (AV = +2, RF = 250Ω, VOUT = 2VP-P, Note 5) 10MHz B 25 - -50 - dBc 20MHz B 25 - -45 - dBc Third Harmonic Distortion (AV = +2, RF = 250Ω, VOUT = 2VP-P, Note 5) 10MHz B 25 - -50 - dBc 20MHz B 25 - -45 - dBc TRANSIENT CHARACTERISTICS AV = +2, RF = 250Ω, Unless Otherwise Specified Rise and Fall Times (VOUT = 0.5VP-P, Note 5) Rise Time B 25 - 0.81 - ns Fall Time B 25 - 1.25 - ns Overshoot (Note 4) (VOUT = 0 to 0.5V, VIN tRISE = 2.5ns) +OS B 25 - 3 - % -OS B 25 - 5 - % Overshoot (Note 4) (VOUT = 0.5VP-P, VIN tRISE = 2.5ns) +OS B 25 - 2 - % -OS B 25 - 10 - % Slew Rate (VOUT = 4VP-P, AV = +1, RF = 1.5kΩ) +SR B 25 - 875 - V/µs -SR (Note 6) B 25 - 510 - V/µs Slew Rate (VOUT = 5VP-P, AV = +2, RF = 250Ω) 3 +SR B 25 - 1530 - V/µs -SR (Note 6) B 25 - 850 - V/µs HFA1135 VSUPPLY = ±5V, AV = +1, RF = 510Ω (Note 3), RL = 100Ω, Unless Otherwise Specified (Continued) Electrical Specifications PARAMETER TEST CONDITIONS (NOTE 2) TEST LEVEL TEMP. (oC) MIN TYP MAX UNITS Slew Rate (VOUT = 5VP-P, AV = -1, RF = 330Ω) +SR B 25 - 2300 - V/µs -SR (Note 6) B 25 - 1200 - V/µs Settling Time (VOUT = +2V to 0V step, Note 5) To 0.1% B 25 - 23 - ns To 0.05% B 25 - 33 - ns To 0.02% B 25 - 45 - ns RL = 150Ω B 25 - 0.02 - % RL = 75Ω B 25 - 0.03 - % RL = 150Ω B 25 - 0.04 - Degrees RL = 75Ω B 25 - 0.06 - Degrees VIDEO CHARACTERISTICS AV = +2, RF = 250Ω, Unless Otherwise Specified Differential Gain (f = 3.58MHz) Differential Phase (f = 3.58MHz) OUTPUT LIMITING CHARACTERISTICS AV = +2, RF = 250Ω, VH = +1V, VL = -1V, Unless Otherwise Specified Limit Accuracy (Note 5) VIN = ±2V, AV = -1, RF = 510Ω A Full -125 25 125 mV Overdrive Recovery Time (Note 5) VIN = ±1V B 25 - 0.8 - ns Negative Limit Range B 25 -5.0 to +2.5 V Positive Limit Range B 25 -2.5 to +5.0 V Limit Input Bias Current A 25 - 50 200 µA A Full - 80 200 µA Power Supply Range C 25 ±4.5 - ±5.5 V Power Supply Current (Note 5) A Full 6.4 6.9 7.3 mA POWER SUPPLY CHARACTERISTICS NOTES: 2. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 3. The optimum feedback resistor for the HFA1135 at AV = +1 is 1.5kΩ. The Production Tested parameters are tested with RF = 510Ω because the HFA1135 shares test hardware with the HFA1105 amplifier. 4. Undershoot dominates for output signal swings below GND (e.g., 0.5VP-P), yielding a higher overshoot limit compared to the VOUT = 0V to 0.5V condition. See the “Application Information” section for details. 5. See Typical Performance Curves for more information. 6. Slew rates are asymmetrical if the output swings below GND (e.g., a bipolar signal). Positive unipolar output signals have symmetric positive and negative slew rates comparable to the +SR specification. See the “Application Information” section, and the pulse response graphs for details. Application Information Relevant Application Notes The following Application Notes pertain to the HFA1135: • AN9653-Use and Application of Output Limiting Amplifiers • AN9752-Sync Stripper and Sync Inserter for Composite Video • AN9787-An Intuitive Approach to Understanding Current Feedback Amplifiers • AN9420-Current Feedback Amplifier Theory and Applications • AN9663-Converting from Voltage Feedback to Current Feedback Amplifiers 4 These publications may be obtained from Intersil’s web site (www.intersil.com) or via our AnswerFAX system. Optimum Feedback Resistor Although a current feedback amplifier’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF. The HFA1135 design is optimized for a 250Ω RF at a gain of +2. Decreasing RF decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same HFA1135 The table below lists recommended RF values, and the expected bandwidth, for various closed loop gains. TABLE 1. OPTIMUM FEEDBACK RESISTOR GAIN (AV) RF (Ω) BANDWIDTH (MHz) -1 330 290 +1 1.5k 660 +2 250 330 360 315 +5 180 200 +10 250 90 Non-inverting Input Source Impedance For best operation, the DC source impedance seen by the non-inverting input should be ≥50Ω. This is especially important in inverting gain configurations where the noninverting input would normally be connected directly to GND. Pulse Undershoot and Asymmetrical Slew Rates The HFA1135 utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (see Figures 9, 13, and 17). This undershoot isn’t present for small bipolar signals, or large positive signals. Another artifact of the composite device is asymmetrical slew rates for output signals with a negative voltage component. The slew rate degrades as the output signal crosses through 0V (see Figures 9, 13, and 17), resulting in a slower overall negative slew rate. Positive only signals have symmetrical slew rates as illustrated in the large signal positive pulse response graphs (see Figures 7, 11, and 15). PC Board Layout This amplifier’s frequency response depends greatly on the care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. 5 Care must also be taken to minimize the capacitance to ground at the amplifier’s inverting input (-IN), as this capacitance causes gain peaking, pulse overshoot, and if large enough, instability. To reduce this capacitance, the designer should remove the ground plane under traces connected to -IN, and keep connections to -IN as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 2. Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 660MHz (AV = +1). By decreasing RS as CL increases (as illustrated by the curves), the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth still decreases as the load capacitance increases. For example, at AV = +1, RS = 50Ω, CL = 20pF, the overall bandwidth is 170MHz, but the bandwidth drops to 45MHz at AV = +1, RS = 10Ω, CL = 330pF. 50 45 40 35 RS (Ω) problems due to the feedback impedance decrease at higher frequencies). At higher gains the amplifier is more stable, so RF can be decreased in a trade-off of stability for bandwidth. 30 25 20 15 AV = +1 AV = +1 10 AV = +2, RF = 250Ω 5 0 0 40 80 120 160 200 240 280 320 360 400 LOAD CAPACITANCE (pF) FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD CAPACITANCE HFA1135 Evaluation Board The performance of the HFA1135 may be evaluated using the HFA11XX evaluation board (part number HFA11XXEVAL). Please contact your local sales office for information. When evaluating this amplifier at a gain of +2, the two 510Ω gain setting resistors on the evaluation board should be changed to 250Ω. The layout and schematic of the board are shown in Figure 2. NOTE: The SOIC version may be evaluated in the DIP board by using a SOIC-to-DIP adapter such as Aries Electronics part number 08-350000-10. BOARD SCHEMATIC 510Ω of the amplifier. VH sets the upper output limit, while VL sets the lower limit level. If the amplifier tries to drive the output above VH, or below VL, the clamp circuitry limits the output voltage at VH or VL (± the limit accuracy), respectively. The low input bias currents of the limit pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or DACs. Limit Circuitry Figure 3 shows a simplified schematic of the HFA1135 input stage, and the high limit (VH) circuitry. As with all current feedback amplifiers, there is a unity gain buffer (QX1 - QX2) between the positive and negative inputs. This buffer forces -IN to track +IN, and sets up a slewing current of: ISLEW = (V-IN - VOUT)/RF + V-IN/RG 510Ω VH 50Ω 1 8 2 7 3 6 4 5 V+ 0.1µF 10µF +5V QP3 50Ω IN 10µF 0.1µF VL QN2 GND QP1 GND -5V QP4 OUT +IN TOP LAYOUT R1 Z ILIMIT +1 VV+ 200Ω QN1 QN5 QP2 VH 1 50kΩ VH QN6 QP6 QN3 QN4 QP5 +IN OUT V+ VL VGND VV-IN -IN RF (EXTERNAL) VOUT FIGURE 3. HFA1135 SIMPLIFIED VH LIMIT CIRCUITRY BOTTOM LAYOUT This current is mirrored onto the high impedance node (Z) by QX3-QX4, where it is converted to a voltage and fed to the output via another unity gain buffer. If no limiting is utilized, the high impedance node may swing within the limits defined by QP4 and QN4. Note that when the output reaches its quiescent value, the current flowing through -IN is reduced to only that small current (-IBIAS) required to keep the output at the final voltage. FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT Limiting Operation General The HFA1135 features user programmable output clamps to limit output voltage excursions. Limiting action is obtained by applying voltages to the VH and VL terminals (pins 8 and 5) 6 Tracing the path from VH to Z illustrates the effect of the limit voltage on the high impedance node. VH decreases by 2VBE (QN6 and QP6) to set up the base voltage on QP5 . QP5 begins to conduct whenever the high impedance node reaches a voltage equal to QP5’s base voltage + 2VBE (QP5 and QN5). Thus, QP5 limits node Z whenever Z reaches VH . R1 provides a pull-up network to ensure functionality with the limit inputs floating. A similar description applies to the symmetrical low limit circuitry controlled by VL. HFA1135 As an example, a unity gain circuit with VIN = 2V, and VH = 1V, would have ILIMIT = (2V - 1V)/1.5kΩ + 2V/∞ = 667µA (RG = ∞ for unity gain applications). Note that ICC increases by ILIMIT when the output is limited. Limit Accuracy The limited output voltage will not be exactly equal to the voltage applied to VH or VL. Offset errors, mostly due to VBE mismatches, necessitate a limit accuracy parameter which is found in the device specifications. Limit accuracy is a function of the limiting conditions. Referring again to Figure 3, it can be seen that one component of limit accuracy is the VBE mismatch between the QX6 transistors, and the QX5 transistors. If the transistors always ran at the same current level there would be no VBE mismatch, and no contribution to the inaccuracy. The QX6 transistors are biased at a constant current, but as described earlier, the current through QX5 is equivalent to ILIMIT. VBE increases as ILIMIT increases, causing the limited output voltage to increase as well. ILIMIT is a function of the overdrive level ((AV x VIN - VLIMIT) / VLIMIT), so limit accuracy degrades as the overdrive increases. For example, accuracy degrades from +15mV to +70mV when the overdrive increases from 100% to 200% (AV = +2, VH = 500mV, RF = 250Ω). Benefits of Output Limiting The plots of “Pulse Response Without Limiting” and “Pulse Response With Limiting” (Figures 4 and 5) highlight the advantages of output limiting. Besides the obvious benefit of constraining the output swing to a defined range, limiting the output excursions also keeps the output transistors from saturating, which prevents unwanted saturation artifacts from distorting the output signal. Output limiting also takes advantage of the HFA1135’s ultra-fast overdrive recovery time, reducing the recovery time from 2.3ns to 0.3ns, based on the amplifier’s normal propagation delay of 1.2ns. AV = +2, RF = 250Ω 4.0 2.0 IN 3.0 1.5 OUT 1.0 2.0 0.5 1.0 0 0 -0.5 -1.0 -1.0 -2.0 OUTPUT VOLTAGE (V) ILIMIT = (V-IN - VOUT LIMITED)/RF + V-IN/RG . limiting and the amplifier’s normal propagation delay, and it is a strong function of the overdrive level. Figure 36 details the overdrive recovery time for various limit and overdrive levels. INPUT VOLTAGE (V) When the output is limited, the negative input continues to source a slewing current (ILIMIT) in an attempt to force the output to the quiescent voltage defined by the input. QP5 must sink this current while limiting, because the -IN current is always mirrored onto the high impedance node. The limiting current is calculated as: TIME (5ns/DIV.) FIGURE 4. PULSE RESPONSE WITHOUT LIMITING Consideration must also be given to the fact that the limit voltages have an effect on amplifier linearity. The “Linearity Near Limit Voltage” curves, Figures 34 and 35, illustrate the impact of several limit levels on linearity. AV = +2, RF = 250Ω Limit Range 2.0 Unlike some competitor devices, both VH and VL have usable ranges that cross 0V. While VH must be more positive than VL , both may be positive or negative, within the range restrictions indicated in the specifications. For example, the HFA1135 could be limited to ECL output levels by setting VH = -0.8V and VL = -1.8V. VH and VL may be connected to the same voltage (GND for instance) but the result won’t be a DC output voltage from an AC input signal. A 150mV - 200mV AC signal will still be present at the output. 1.5 1.0 OUT 0.5 1.0 0 0 -0.5 -1.0 -1.0 Recovery from Overdrive VH = +2.0V, VL = 0V The output voltage remains at the limit level as long as the overdrive condition remains. When the input voltage drops below the overdrive level (VLIMIT/AV) the amplifier returns to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear operation. Overdrive recovery time is defined as the difference between the amplifier’s propagation delay exiting 7 2.0 TIME (5ns/DIV.) FIGURE 5. PULSE RESPONSE WITH LIMITING OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) IN HFA1135 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified 3.0 300 AV = +2, RF = 250Ω 250 2.5 200 2.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) AV = +2, RF = 250Ω 150 100 50 0 -50 1.5 1.0 0.5 0 -0.5 -100 -1.0 TIME (5ns/DIV.) TIME (5ns/DIV.) FIGURE 6. SMALL SIGNAL POSITIVE PULSE RESPONSE FIGURE 7. LARGE SIGNAL POSITIVE PULSE RESPONSE 200 2.0 AV = +2, RF = 250Ω 150 1.5 100 1.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) AV = +2, RF = 250Ω 50 0 -50 -100 -150 0.5 0 -0.5 -1.0 -1.5 -200 -2.0 TIME (5ns/DIV.) TIME (5ns/DIV.) FIGURE 8. SMALL SIGNAL BIPOLAR PULSE RESPONSE FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE 300 250 3.0 AV = +1 AV = +1 2.5 2.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) 200 150 100 50 0 -50 1.5 1.0 0.5 0 -0.5 -1.0 -100 TIME (5ns/DIV.) FIGURE 10. SMALL SIGNAL POSITIVE PULSE RESPONSE 8 TIME (5ns/DIV.) FIGURE 11. LARGE SIGNAL POSITIVE PULSE RESPONSE HFA1135 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) 200 AV = +1 1.5 1.0 100 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) 150 2.0 AV = +1 50 0 -50 -100 -150 0.5 0 -0.5 -1.0 -1.5 -200 -2.0 TIME (5ns/DIV.) FIGURE 12. SMALL SIGNAL BIPOLAR PULSE RESPONSE FIGURE 13. LARGE SIGNAL BIPOLAR PULSE RESPONSE 3.0 300 AV = -1 AV = -1 250 2.5 200 2.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) TIME (5ns/DIV.) 150 100 50 0 -50 1.5 1.0 0.5 0 -0.5 -100 -1.0 TIME (5ns/DIV.) FIGURE 14. SMALL SIGNAL POSITIVE PULSE RESPONSE TIME (5ns/DIV.) FIGURE 15. LARGE SIGNAL POSITIVE PULSE RESPONSE 200 2.0 AV = -1 150 1.5 100 1.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) AV = -1 50 0 -50 -100 -150 0.5 0 -0.5 -1.0 -1.5 -200 TIME (5ns/DIV.) FIGURE 16. SMALL SIGNAL BIPOLAR PULSE RESPONSE 9 -2.0 TIME (5ns/DIV.) FIGURE 17. LARGE SIGNAL BIPOLAR PULSE RESPONSE HFA1135 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, GAIN 0 AV = -1 -6 AV = +2, RF = 250Ω PHASE 0 AV = -1 AV = +2, RF = 250Ω AV = +1 90 180 270 360 1 10 100 0 GAIN -3 VOUT = 2.5VP-P -6 VOUT = 4VP-P 0 PHASE AV = +1 1000 1 GAIN (dB) GAIN -3 VOUT = 2.5VP-P -6 VOUT = 4VP-P 10 100 FREQUENCY (MHz) PHASE 0 VOUT = 1VP-P 90 180 270 360 1 10 100 1000 AV = -1 3 VOUT = 1VP-P GAIN 0 -3 VOUT = 2.5VP-P -6 VOUT = 4VP-P VOUT = 2.5VP-P 180 FIGURE 19. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES VOUT = 1VP-P 0 90 360 PHASE PHASE (DEGREES) GAIN (dB) 3 VOUT = 4VP-P VOUT = 2.5VP-P VOUT = 1VP-P 270 FREQUENCY (MHz) FIGURE 18. FREQUENCY RESPONSE VOUT = 1VP-P 0 VOUT = 4VP-P 90 VOUT = 2.5VP-P VOUT = 1VP-P 180 270 360 1000 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) FIGURE 20. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES VOUT = 4VP-P NORMALIZED PHASE (DEGREES) -3 AV = +2 3 R = 250Ω F PHASE (DEGREES) AV = +1 NORMALIZED GAIN (dB) VOUT = 200mVP-P 3 NORMALIZED PHASE (DEGREES) NORMALIZED GAIN (dB) Unless Otherwise Specified (Continued) 1000 FIGURE 21. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES 900 BANDWIDTH (MHz) NORMALIZED GAIN (dB) 1000 3 0 AV = +1, VOUT = 4VP-P -3 AV = +2, RF = 250Ω, VOUT = 5VP-P -6 800 700 600 500 AV = +2, RF = 250Ω 400 -9 AV = -1, VOUT = 5VP-P 300 AV = -1 1 10 100 FREQUENCY (MHz) FIGURE 22. FULL POWER BANDWIDTH 10 1000 200 -75 -50 -25 0 25 50 75 100 TEMPERATURE (oC) FIGURE 23. -3dB BANDWIDTH vs TEMPERATURE 125 HFA1135 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) VOUT = 200mVP-P AV = +2, RF = 250Ω 630 AV = +2, RF = 330Ω 0.1 200 GAIN 63 -0.1 -0.2 -0.3 -0.4 AV = +1 -0.5 20 PHASE 6.3 180 2.0 135 0.63 90 0.2 45 0 -0.6 1 10 FREQUENCY (MHz) 0.001 100 10 100 500 AV = +2, RF = 250Ω OUTPUT RESISTANCE (Ω) -30 -40 -50 -60 -70 -80 1K 100 10 1 0.1 0.01 -90 -100 0.3 1 10 100 FREQUENCY (MHz) 1000 1 10 100 FREQUENCY (MHz) 1000 FIGURE 27. OUTPUT RESISTANCE FIGURE 26. REVERSE ISOLATION 100 100 0.05 0.025 0 -0.025 -0.05 -0.1 3 13 23 33 43 53 63 73 83 TIME (ns) FIGURE 28. SETTLING TIME RESPONSE 11 93 103 INI- 10 10 ENI INI+ 1 0.1 1 1 10 FREQUENCY (kHz) 100 FIGURE 29. INPUT NOISE CHARACTERISTICS NOISE CURRENT (pA/√Hz) NOISE VOLTAGE (nV/√Hz) 0.1 SETTLING ERROR (%) GAIN (dB) 1 FIGURE 25. OPEN LOOP TRANSIMPEDANCE AV = +2, ±1 -20 0.1 FREQUENCY (MHz) FIGURE 24. GAIN FLATNESS -10 0.01 PHASE (DEGREES) 0 GAIN (kΩ) NORMALIZED GAIN (dB) 0.2 HFA1135 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) -45 -40 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) AV = +2, RF = 250Ω -45 -50 20MHz -55 -60 10MHz -65 -70 -5.0 -2.5 0 2.5 5.0 7.5 10.0 12.5 AV = +2, RF = 250Ω -50 20MHz -55 10MHz -60 -65 -70 -75 -5.0 15.0 -2.5 0 150 VH = +500mV, RF = 250Ω VH = +1.0V, RF = 250Ω 50 VH = +1.0V, RF = 510Ω 0 -50 VH = +2.0V, RF = 510Ω -100 10.0 12.5 15.0 VL = -500mV, RF = 250Ω AV = +2 VL = -1.0V, RF = 250Ω 100 V = -1.0V, R = 510Ω L F VH = +500mV, RF = 510Ω LIMIT ACCURACY (mV) LIMIT ACCURACY (mV) 100 7.5 FIGURE 31. 3rd HARMONIC DISTORTION vs POUT FIGURE 30. 2nd HARMONIC DISTORTION vs POUT AV = +2 5.0 OUTPUT POWER (dBm) OUTPUT POWER (dBm) 150 2.5 -150 50 VL = -500mV, RF = 510Ω VL = -2.0V, RF = 250Ω VL = -2.0V, RF = 510Ω 0 -50 -100 -150 VH = +2.0V, RF = 250Ω -200 -200 0 100 200 300 400 500 0 100 200 OVERDRIVE (% OF VH) FIGURE 32. VH LIMIT ACCURACY vs OVERDRIVE 2.0 AV = +2 RF = 250Ω AV = +1 500 VH = +2V 1.8 1.6 1.6 VL = -2V VH = +2V 1.4 LINEARITY ERROR (%) LINEARITY ERROR (%) 400 FIGURE 33. VL LIMIT ACCURACY vs OVERDRIVE 2.0 1.8 300 OVERDRIVE (% OF VL) 1.2 VL = -1V VH = +1V 1.0 0.8 0.6 VL = -500mV VH = +500mV 0.4 VL = -2V 1.4 VH = +1V 1.2 VL = -1V 1.0 0.8 VL = -500mV 0.6 VH = +500mV 0.4 0.2 0.2 0 -2.0 -1.5 -1.0 0 -0.5 0.5 AV x VIN (V) 1.0 1.5 FIGURE 34. LINEARITY NEAR LIMIT VOLTAGE 12 2.0 0 -2.0 -1.5 -1.0 -0.5 0 0.5 AV x VIN (V) 1.0 1.5 FIGURE 35. LINEARITY NEAR LIMIT VOLTAGE 2.0 HFA1135 Typical Performance Curves VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table, RL = 100Ω, Unless Otherwise Specified (Continued) 3.6 2.5 AV = -1 VH = +1V |-VOUT| (RL = 100Ω) 3.5 +VOUT (RL = 100Ω) 2.0 3.4 VH = +2V OUTPUT VOLTAGE (V) OVERDRIVE RECOVERY TIME (ns) AV = +2 RF = 250Ω 1.5 VH = +3V VL = -2V 1.0 VL = -1V VL = -3V 0.5 3.3 3.2 |-VOUT| (RL = 50Ω) 3.1 +VOUT (RL = 50Ω) 3.0 2.9 2.8 2.7 0 0 100 200 300 2.6 -50 400 -25 0 25 FIGURE 36. OVERDRIVE RECOVERY TIME vs OVERDRIVE 100 125 1.8 1.7 VOUT = 500mVP-P FALL TIMES 1.6 7.0 AV = -1 RISE/FALL TIMES (ns) 1.5 SUPPLY CURRENT (mA) 75 FIGURE 37. OUTPUT VOLTAGE vs TEMPERATURE 7.1 6.9 6.8 6.7 1.4 AV = +1 1.3 1.2 AV = +2, RF = 250Ω 1.1 RISE TIMES 1.0 AV = -1 0.9 AV = +1 0.8 AV = +2, RF = 250Ω 0.7 4.0 50 TEMPERATURE (oC) OVERDRIVE (% OF VH OR VL) 4.5 5.0 5.5 6.0 6.5 SUPPLY VOLTAGE ( ±V) FIGURE 38. SUPPLY CURRENT vs SUPPLY VOLTAGE 13 7.0 0.6 -75 -50 -25 0 25 50 75 100 TEMPERATURE (oC) FIGURE 39. RISE AND FALL TIMES vs TEMPERATURE 125 HFA1135 Die Characteristics DIE DIMENSIONS SUBSTRATE POTENTIAL (POWERED UP) 59 mils x 58.2 mils x 19 mils 1500µm x 1480µm x 483µm Floating (Recommend Connection to V-) PASSIVATION METALLIZATION Type: Nitride Thickness: 4kÅ ±0.5kÅ Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ TRANSISTOR COUNT 89 PROCESS Bipolar Dielectric Isolation Metallization Mask Layout HFA1135 -IN VH V+ OUT +IN V- 14 VL HFA1135 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- e α A1 B 0.25(0.010) M C A M MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e C 0.10(0.004) B S NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MILLIMETERS MIN 0.050 BSC 1.27 BSC 0.2284 0.2440 h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 5.80 - H 8 0o 6.20 - 8 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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