EL5000A ® Data Sheet July 28, 2005 High Voltage TFT-LCD Logic Driver Features The EL5000A is high voltage TFT-LCD logic driver with +40V and -30V output swing capability. Manufactured using the Intersil proprietary monolithic high voltage bipolar process, it is capable of delivering 100mA output peak current into 5nF of capacitive load. To simplify external circuitry, the EL5000A integrates additional logic circuits. • 3.3V logic supply The EL5000A can operate on 3.3V logic supply and high voltage -30V to +40V output supplies. The EL5000A is available in TSSOP-16 package. It is specified for operation over the -20°C to +85°C extended temperature range. Ordering Information PART NUMBER • 40V VON output high level • -30V VOFF output low level • 166kHz input logic frequency • 100mA output peak current • 10mA output continuous current • TTL-compatible logic input • Pb-free plus anneal available (RoHS compliant) Applications PACKAGE TAPE & REEL PKG. DWG. # EL5000AER 16-Pin TSSOP - MDP0044 EL5000AER-T7 16-Pin TSSOP 7” MDP0044 EL5000AER-T13 16-Pin TSSOP 13” MDP0044 EL5000AERZ (See Note) 16-Pin TSSOP (Pb-Free) - MDP0044 EL5000AERZ-T7 (See Note) 16-Pin TSSOP (Pb-Free) 7” MDP0044 EL5000AERZT13 (See Note) 16-Pin TSSOP (Pb-Free) 13” MDP0044 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 FN6167.0 • TFT-LCD panels Pinout EL5000A (16-PIN TSSOP) TOP VIEW VON1 1 16 VDD CKV 2 15 DISH CKVCS 3 14 OECON NC 4 13 GND CKVBCS 5 12 STV CKVB 6 11 OE STVP 7 10 CPV VOFF 8 9 GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5000A Absolute Maximum Ratings (TA = 25°C) VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V VON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44V VOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -33V VCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V VCKV, VCKVB, VSTVP, VCKVCS, VCKVBCS, VSTVP . . . . . . . . VON + 1 diode/VOFF - 1 diode VCPV, VOE, VSTV, VOECON . . . . . . . VDD + 1 diode/GND - 1 diode VDISH . . . . . . . . . . . . . . . . . . . . . . . GND + 1 diode/VOFF - 1 diode IOUT (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA IOUT (continuos), CKV, CKVB, or STVP . . . . . . . . . . . . . . . . . 30mA IOUT (continuous, total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA TAMBIENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20°C to +85°C TJUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20°C to +150°C TSTORAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C PDISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER IVDD VON = 20V, VOFF = -14V, VDD = 3.3V, 4.7nF Load on STV, CKV, CKVB, unless otherwise specified. DESCRIPTION VDD Supply Current CONDITION All inputs low CPV = 3.1V, other inputs low IVON VON Supply Current VOFF Supply Current ISTV ICPV IOE IOECON STV Input Current CPV Input Current OE Input Current OECON Input Current 0.7 MAX 1.5 0.2 0.45 UNIT mA 2.5 0.25 All inputs low CPV = 3.1V, other inputs low TYP 1.1 All inputs low CPV = 3.1V, other inputs low IVOFF MIN mA mA 0.9 0.25 mA mA -1.25 -0.7 -0.30 mA STV = 3.1V 25 130 180 µA STV = 0.2V -1 0 1 µA CPV = 3.1V 20 60 90 µA CPV = 0.2V -1 0 1 µA OE = 0.2V -1 0 1 µA OE = 3.1V, OECON = 0.2V 200 450 700 µA OE = 3.1V, OECON = 3.1V -1 0 1 µA OECON - 0.2V, OE = 3.1V -40 -25 -5 µA OECON - 0.2V, OE = 0.2V -1 0 1 µA VCKV+ CKV Positive Output Swing VON = +20V, 1mA output current 19.1 19.3 19.5 V VCKV CKV Negative Output Swing VOFF = -14V, 1mA output current -13.1 -13.3 -13.5 V VCKVB+ CKVB Positive Output Swing VON = +20V, 1mA output current 19.1 19.3 19.5 V VCKVB CKVB Negative Output Swing VOFF = -14V, 1mA output current -13.1 -13.3 -13.5 V VSTVP+ STVP Positive Output Swing VON = +20V, 1mA output current 19.0 19.2 19.4 V VSTVP STVP Negative Output Swing VOFF = -14V, 1mA output current -13.1 -13.3 -13.5 V RIN CPV, OE, STV Input Resistance 3 kΩ CIN CPV, OE, STV Input Capacitance 1.5 pF TR-CKV CKV Rise Time 0.3 0.5 0.7 µs TF-CKV CKV Fall Time 0.5 0.75 1 µs TR-CKVB CKVB Rise Time 0.3 0.5 0.7 µs TF-CKVB CKVB Fall Time 0.5 0.75 1 µs TR-STVP STVP Rise Time 1.2 1.6 2.4 µs TF-STVP STVP Fall Time 1.2 1.6 2.4 µs 2 FN6167.0 July 28, 2005 EL5000A Electrical Specifications PARAMETER VON = 20V, VOFF = -14V, VDD = 3.3V, 4.7nF Load on STV, CKV, CKVB, unless otherwise specified. (Continued) DESCRIPTION CONDITION MIN TYP MAX UNIT TD-CKV+ CKV Rising Edge Delay Time 0.5 0.9 1.3 µs TD-CKV- CKV Falling Edge Delay Time 0.7 1.1 1.5 µs TD-CKVB+ CKVB Rising Edge Delay Time 0.5 0.9 1.3 µs TD-CKVB- CKVB Falling Edge Delay Time 0.7 1.1 1.5 µs TD-STVP+ STVP Rising Edge Delay Time 1.3 1.75 2.2 µs TD-STVP- STVP Falling Edge Delay Time 1.2 1.7 2 µs TD-CKV_CS+ CKV_CS Rising Edge Delay Time 1.6 2.3 2.9 µs TD-CKV_CS- CKV_CS Falling Edge Delay Time 3.4 4.1 4.8 µs TD-CKVB_CS+ CKVB_CS Rising Edge Delay Time 1.6 2.3 2.9 µs TD-CKVB_CS- CKVB_CS Falling Edge Delay Time 3.4 4.1 4.8 µs Typical Performance Curves 1.5 500 VON=20V VOFF=-14V 1.25 VCC=3.3V VOFF=-14V 400 CPV INPUT HIGH IVON (µA) IVCC (mA) 1 0.75 300 200 ALL INPUTS LOW 0.5 100 0.25 0 0 1 2 3 4 0 5 0 10 20 VCC (V) 50 FIGURE 2. VON DC SUPPLY CURRENT vs VON 800 1.5 VON=20V VOFF=-14V 1.25 CPV INPUT HIGH FALL DELAY (µs) IVOFF (µA) 40 VON (V) FIGURE 1. VSS SUPPLY CURRENT vs VCC 600 30 400 1 RISE 0.75 0.5 ALL INPUTS LOW 200 0.25 VCC=3.3V VON=20V 0 -35 -30 -25 -20 -15 -10 -5 0 VOFF (V) FIGURE 3. VOFF DC SUPPLY CURRENT vs VOFF 3 0 DELAY FROM CPV INPUT TO CKV OR CKVB REACHING 50% OF FINAL VALUE 0 1K 2K 3K 4K 5K LOAD CAPACITANCE (pF) FIGURE 4. CLOCK DELAY vs LOAD CAPACITOR FN6167.0 July 28, 2005 EL5000A Typical Performance Curves (Continued) 1.5 1.5 VON=40V VOFF=-20V 1.25 1.25 VON=20V VOFF=-14V FALL 1 0.75 DELAY (µs) DELAY (µs) FALL RISE 0.5 0.25 0 1K 2K 3K 4K RISE 0.75 0.5 0.25 DELAY FROM CPV INPUT TO CKV OR CKVB REACHING 50% OF FINAL VALUE 0 1 4.7nF LOAD CAPACITORS 0 -25 25 5K LOAD CAPACITANCE (pF) FIGURE 5. CLOCK DELAY vs LOAD CAPACITOR VCC=3.3V VON=20V VOFF=-14V IVCC (mA) 1.2 1 0.8 0.6 -25 25 75 1K IVO 800 600 IVO 200 IVON, INPUTS LOW OE INPUT, 75 125 3.3V HEADROOM (mV) INPUT CURRENT (µA) 25 750 300 STV INP UT, 3.3V 100 500 250 CPV INPUT, 3.3V CKV, CKVB, AND STVP OUTPUTS 5mA LOAD OECON INPUT, 0.2V -100 -25 IGH FIGURE 8. DC SUPPLY CURRENTS vs TEMPERATURE 500 0 N , CP V H AMBIENT TEMPERATURE (°C) FIGURE 7. VCC SUPPLY CURRENT vs TEMPERATURE 200 FF , CPV HIGH IVOFF, INPUTS LOW 0 -25 125 VCC=3.3V VON=20V VOFF=-14V 400 AMBIENT TEMPERATURE (°C) 400 125 FIGURE 6. CLOCK DELAY vs TEMPERATURE SUPPLY CURRENT (µA) 1.4 75 AMBIENT TEMPERATURE (°C) 25 75 125 AMBIENT TEMPERATURE (°C) FIGURE 9. INPUT BIAS CURRENTS vs TEMPERATURE 4 0 -25 25 75 125 AMBIENT TEMPERATURE (°C) FIGURE 10. OUTPUT SWING HEADROOM vs TEMPERATURE FN6167.0 July 28, 2005 EL5000A Typical Performance Curves (Continued) 800 VON=40V 1200 VOFF=-20V RCS=500Ω POWER DISSIPATION (mW) POWER DISSIPATION (mW) 1400 1000 800 4700pF 1000pF 600 400 220pF 200 0 0 0 100 150 600 400 4700pF 1000pF 200 220pF 0 200 VON=20V VOFF=-14V RCS=500Ω 0 0 INPUT FREQUENCY (kHz) FIGURE 11. POWER CONSUMPTION vs FREQUENCY AND LOAD JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.8 200 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.6 1 845mW 0.8 θ TS JA = 0.6 SO 14 8° P1 C/ 6 W 0.4 0.2 0 150 FIGURE 12. POWER CONSUMPTION vs FREQUENCY AND LOAD POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 100 INPUT FREQUENCY (kHz) 1.4 1.289W 1.2 θ TS SO P 97 16 °C /W JA = 1 0.8 0.6 0.4 0.2 0 25 75 85 100 50 125 150 AMBIENT TEMPERATURE (°C) FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 5 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN6167.0 July 28, 2005 EL5000A Pin Descriptions PIN NUMBER PIN NAME 1 VON Positive supply 2 CKV High voltage output, scan clock out 3 CKVCS 4 NC 5 CKVBCS 6 CKVB High voltage output, scan clock even 7 STVP High voltage output, scan start pulse 8 VOFF Negative supply 9 GND Ground 10 CPV H sync timing, H sync clock 1 11 OE Writing timing, H sync clock 2 12 VTS V sync timing, V sync 13 GND Ground, logic return 14 OECON 15 DISH Discharge function input, VOFF discharge 16 VDD Logic power supply 6 PIN FUNCTION Discharge switch input, CKV charge share No connect Discharge switch input, CKVB charge share OE disable input, OE blank FN6167.0 July 28, 2005 EL5000A EL5000A FIGURE 15. EL5000A SYSTEM BLOCK DIAGRAM Application Information General Description The EL5000A is a high performance 70V TFT-LCD row driver. It level shifts TTL level timing signals from the video source into 70V peak to peak output voltage. Its output is capable of delivering 100mA peak current into 1nF of capacitive load. It also incorporates logic to control the output timings. The logic timing control circuit is powered from 3.3V supply. Figure 15 shows the system block diagram. CL capacitors model the capacitive loading appeared at the inputs of the TFT-LCD panel for the CKV and the CKVB signals. The CL is typically between 1nF and 5nF. In addition to switches SW1, SW2, SW3, and SW4, a fifth switch is added to reduce the power dissipation and shape the output waveform. Figure 17 shows the location of the additional SW5 switch. Input Signals The device performs beside of level transformation also logic operation between the input signals: • STV - Vertical Sync Timing signal, frequency range around 60Hz SW1 SW2 CKV CKVB r SW5 Rd r CL • CPV - Horizontal Sync Timing signal, frequency range up to 166kHz CL SW3 SW4 • OE - Output Enable Write Signal, frequency range up to 166kHz FIGURE 17. SW5 SWITCH LOCATION Output Signals The output signals, CKV and CKVB are generated by EL5000A internal switches. Figure 16 depicts the simplified schematic of the output stage and interface. In reality, each switch consists of two such switches, one for the positive discharge and one for the negative discharge, see Figure 18. FIGURE 18. BI-DIRECTIONAL SWITCHES FIGURE 16. SIMPLIFIED SCHEMATIC OF OUTPUT STAGE 7 Due to the actual solid-state construction of the switches, the capacitors CL does not get discharged entirely. The amount of left over charges depends on the value of the voltages of VON and VOFF on the capacitors. FN6167.0 July 28, 2005 EL5000A Internal Logic Block Diagram Figures 19 and 20 show the internal block diagram. In order to reduce power dissipation, most of the logic circuitry is powered from 3.3V logic supply. The output of the 3.3V logic is level-shifted to drive the output switches. FIGURE 19. INTERNAL LOGIC BLOCK DIAGRAM FIGURE 20. INTERNAL LOGIC BLOCK DIAGRAM AND OUTPUT SWITCHES 8 FN6167.0 July 28, 2005 EL5000A Output Waveforms Figure 21 shows a typical CKV and CKVB output waveforms. The output droop rate depends on the external discharge resistor value and the output capacitor load. Figure 22 shows the delay time between the incoming horizontal sync timing pulse CPV and the generated output pulses. ∆t is dependent mainly on the value of CL. Figure 23 shows the effect of STV. CKV CKV CKVB STV CKVB FIGURE 21. CKV AND CKVB OUTPUT WAVEFORMS CPV FIGURE 23. EFFECT OF STV CKV Auxiliary Functions CKVB DISH: It discharges VOFF when the logic power voltage level drops out, when 'DISH' is < -0.6V (VCC system power turns off), VOFF is connected to ground level by 1kΩ. OECON: It provides continuos polarity changes to the TFT-LCD panel during the vertical blanking. CPV FIGURE 22. CPV TO CKV/CKVB DELAY FIGURE 24. TYPICAL APPLICATION CIRCUIT 9 FN6167.0 July 28, 2005 EL5000A Power Dissipation +40V The dissipated power in R3 and R6 could calculated as follows: 23V We assume that: +17 V • VON = 40V +3.3 V • VOFF = -20V 0V • H sync timing frequency = 60kHz • CL = 5nF 23V -20V The value of VL, the left over voltage in the capacitors in that case is 23V for the positive discharge and 3.3V for the negative discharge. FIGURE 25. The voltage change across the capacitor is therefore 23V, see Figure 25. The stored energy in the capacitor is: 2 2 -9 1/2 × V C = 1/2 × 23 × 5 × 10 = 132µW The energy which is stored in the capacitor will be dissipated on the resistor see Figure 26. The switch will close 2 x 60,000 in every second. Since the process will be repeated 2 times, for the CKV and the CKVB. In 0,000 cycles per second the power dissipation in R3 and R6 becomes: 2 × 1.32 × 10 -6 3 × 60 = 160mW FIGURE 26. For different values of VON, VOFF, CL and H sync timing frequency, the worst case dissipation can be calculated in a similar matter. The value of the R3 and R6 must be selected such that the capacitor CL is discharged via R3 or R6 resistor in one half period of the H sync timing. Figures 11 and 12 show the total power dissipation over a range of possible voltages, operating frequencies and loads. Care should be taken to prevent the power from exceeding the maximum rating of the package, as shown in Figure 13. 10 FN6167.0 July 28, 2005 EL5000A Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6167.0 July 28, 2005