EL5000A ® Data Sheet February 20, 2008 High Voltage TFT-LCD Logic Driver Features The EL5000A is high voltage TFT-LCD logic driver with +40V and -30V output swing capability. Manufactured using the Intersil proprietary monolithic high voltage bipolar process, it is capable of delivering 100mA output peak current into 5nF of capacitive load. To simplify external circuitry, the EL5000A integrates additional logic circuits. • 3.3V logic supply FN6167.2 • 40V VON output high level • -30V VOFF output low level • 166kHz input logic frequency • 100mA output peak current The EL5000A can operate on 3.3V logic supply and high voltage -30V to +40V output supplies. The EL5000A is available in a 16 Ld TSSOP. It is specified for operation over the -20°C to +85°C extended temperature range. Ordering Information PART NUMBER (Note) PART MARKING • 10mA output continuous current • TTL-compatible logic input • Pb-free (RoHS compliant) Applications PACKAGE (Pb-free) PKG. DWG. # EL5000AERZ 5000AER Z 16 Ld TSSOP MDP0044 EL5000AERZ-T7* 5000AER Z 16 Ld TSSOP MDP0044 EL5000AERZ-T13* 5000AER Z 16 Ld TSSOP MDP0044 • TFT-LCD panels Pinout EL5000A (16 LD TSSOP) TOP VIEW *Please refer to TB347 for details on reel specifications. VON 1 16 VDD NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CKV 2 15 DISH 1 CKVCS 3 14 OECON NC 4 13 GND CKVBCS 5 12 STV CKVB 6 11 OE STVP 7 10 CPV VOFF 8 9 GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5000A Absolute Maximum Ratings (TA = +25°C) Thermal Information VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V VON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44V VOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -33V VCKV, VCKVB, VSTVP, VCKVCS, VCKVBCS . . . . . . . . . . . . . . . . . .VON + 0.3V /VOFF - 0.3V VCPV, VOE, VSTV, VOECON . . . . . . . . . . . VDD + 0.3V /GND - 0.3V VDISH . . . . . . . . . . . . . . . . . . . . . . . . . . . GND + 0.3V /VOFF - 0.3V IOUT (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA IOUT (continuous), CKV, CKVB, or STVP . . . . . . . . . . . . . . . . 30mA IOUT (continuous, total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA TAMBIENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20°C to +85°C TJUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-20°C to +150°C TSTORAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C PDISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER IVDD VON = 20V, VOFF = -14V, VDD = 3.3V, 4.7nF load on STV, CKV, CKVB, unless otherwise specified. DESCRIPTION VDD Supply Current CONDITION All inputs low CPV = 3.1V, other inputs low IVON VON Supply Current VOFF Supply Current ISTV ICPV IOE IOECON STV Input Current CPV Input Current OE Input Current OECON Input Current 0.7 MAX (Note 1) 1.5 0.2 0.45 UNIT mA 2.5 0.25 All inputs low CPV = 3.1V, other inputs low TYP 1.1 All inputs low CPV = 3.1V, other inputs low IVOFF MIN (Note 1) mA mA 0.9 0.25 mA mA -1.25 -0.7 -0.30 mA STV = 3.1V 25 130 180 µA STV = 0.2V -1 0 1 µA CPV = 3.1V 20 60 90 µA CPV = 0.2V -1 0 1 µA OE = 0.2V -1 0 1 µA OE = 3.1V, OECON = 0.2V 200 450 700 µA OE = 3.1V, OECON = 3.1V -1 0 1 µA OECON - 0.2V, OE = 3.1V -40 -25 -5 µA OECON - 0.2V, OE = 0.2V -1 0 1 µA VCKV+ CKV Positive Output Swing VON = +20V, 1mA output current 19.1 19.3 19.5 V VCKV CKV Negative Output Swing VOFF = -14V, 1mA output current -13.1 -13.3 -13.5 V VCKVB+ CKVB Positive Output Swing VON = +20V, 1mA output current 19.1 19.3 19.5 V VCKVB CKVB Negative Output Swing VOFF = -14V, 1mA output current -13.1 -13.3 -13.5 V VSTVP+ STVP Positive Output Swing VON = +20V, 1mA output current 19.0 19.2 19.4 V VSTVP STVP Negative Output Swing VOFF = -14V, 1mA output current -13.1 -13.3 -13.5 V RIN CPV, OE, STV Input Resistance CIN CPV, OE, STV Input Capacitance tR-CKV CKV Rise Time 0.3 0.5 0.7 µs tF-CKV CKV Fall Time 0.5 0.75 1 µs tR-CKVB CKVB Rise Time 0.3 0.5 0.7 µs tF-CKVB CKVB Fall Time 0.5 0.75 1 µs tR-STVP STVP Rise Time 1.2 1.6 2.4 µs 2 3 kΩ 1.5 pF FN6167.2 February 20, 2008 EL5000A Electrical Specifications PARAMETER VON = 20V, VOFF = -14V, VDD = 3.3V, 4.7nF load on STV, CKV, CKVB, unless otherwise specified. (Continued) DESCRIPTION CONDITION MIN (Note 1) TYP MAX (Note 1) UNIT tF-STVP STVP Fall Time 1.2 1.6 2.4 µs tD-CKV+ CKV Rising Edge Delay Time 0.5 0.9 1.3 µs tD-CKV- CKV Falling Edge Delay Time 0.7 1.1 1.5 µs tD-CKVB+ CKVB Rising Edge Delay Time 0.5 0.9 1.3 µs tD-CKVB- CKVB Falling Edge Delay Time 0.7 1.1 1.5 µs tD-STVP+ STVP Rising Edge Delay Time 1.3 1.75 2.2 µs tD-STVP- STVP Falling Edge Delay Time 1.2 1.7 2 µs tD-CKV_CS+ CKV_CS Rising Edge Delay Time 1.6 2.3 2.9 µs tD-CKV_CS- CKV_CS Falling Edge Delay Time 3.4 4.1 4.8 µs tD-CKVB_CS+ CKVB_CS Rising Edge Delay Time 1.6 2.3 2.9 µs tD-CKVB_CS- CKVB_CS Falling Edge Delay Time 3.4 4.1 4.8 µs NOTE: 1. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. 3 FN6167.2 February 20, 2008 EL5000A Timing Diagram TD-CKV_CS- TD-CKV+ TD-CKV- +20V +17V TD-CKV_CS+ +10V CKV -4V -11V -14V -14V CPV 50% OF VDD +20V +20V +17V +10V CKVB TD-CKVB_CS- -4V -14V TD-CKVB- 4 -11V TD-CKVB+ TD-CKVB_CS+ FN6167.2 February 20, 2008 EL5000A Typical Performance Curves 500 1.50 VCC = 3.3V VOFF = -14V VON = 20V VOFF = -14V 1.25 400 CPV INPUT HIGH IVON (µA) IVCC (mA) 1.00 0.75 300 200 ALL INPUTS LOW 0.50 100 0.25 0 0 0 1 2 3 4 0 5 10 20 40 50 FIGURE 2. VON DC SUPPLY CURRENT vs VON FIGURE 1. VSS SUPPLY CURRENT vs VCC 800 1.50 VON = 20V VOFF = -14V 1.25 CPV INPUT HIGH 600 FALL DELAY (µs) IVOFF (µA) 30 VON (V) VCC (V) 400 1.00 RISE 0.75 0.50 ALL INPUTS LOW 200 0.25 VCC = 3.3V VON = 20V 0 -35 -30 -25 -20 -15 -5 -10 DELAY FROM CPV INPUT TO CKV OR CKVB REACHING 50% OF FINAL VALUE 0 0 0 VOFF (V) 1k 2k 3k 4k 5k LOAD CAPACITANCE (pF) FIGURE 3. VOFF DC SUPPLY CURRENT vs VOFF FIGURE 4. CLOCK DELAY vs LOAD CAPACITOR 1.50 1.50 VON = 40V VOFF = -20V 1.25 1.25 VON = 20V VOFF = -14V FALL 1.00 0.75 DELAY (µs) DELAY (µs) FALL RISE 0.50 1.00 RISE 0.75 0.50 0.25 0.25 DELAY FROM CPV INPUT TO CKV OR CKVB REACHING 50% OF FINAL VALUE 0 0 1k 2k 3k 4k 5k LOAD CAPACITANCE (pF) FIGURE 5. CLOCK DELAY vs LOAD CAPACITOR 5 4.7nF LOAD CAPACITORS 0 -25 25 75 125 AMBIENT TEMPERATURE (°C) FIGURE 6. CLOCK DELAY vs TEMPERATURE FN6167.2 February 20, 2008 EL5000A Typical Performance Curves (Continued) 1.4 1k SUPPLY CURRENT (µA) VCC = 3.3V VON = 20V VOFF = -14V IVCC (mA) 1.2 1.0 0.8 0.6 -25 25 75 IVO 800 600 IVO HIGH IVOFF, INPUTS LOW 200 IVON, INPUTS LOW 25 75 125 AMBIENT TEMPERATURE (°C) FIGURE 7. VCC SUPPLY CURRENT vs TEMPERATURE FIGURE 8. DC SUPPLY CURRENTS vs TEMPERATURE 750 500 3.3V HEADROOM (mV) OE INPUT, 400 INPUT CURRENT (µA) N , CP V 400 AMBIENT TEMPERATURE (°C) 300 200 STV INP UT, 3.3V 100 500 250 CPV INPUT, 3.3V 0 CKV, CKVB, AND STVP OUTPUTS 5mA LOAD OECON INPUT, 0.2V -100 -25 25 75 0 -25 125 FIGURE 9. INPUT BIAS CURRENTS vs TEMPERATURE 125 800 POWER DISSIPATION (mW) VON = 40V 1200 VOFF = -20V RCS = 500Ω 1000 4700pF 1000pF 600 400 220pF 200 0 0 75 FIGURE 10. OUTPUT SWING HEADROOM vs TEMPERATURE 1400 800 25 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) POWER DISSIPATION (mW) FF , CPV HIGH 0 -25 125 VCC = 3.3V VON = 20V VOFF = -14V 50 100 150 200 INPUT FREQUENCY (kHz) FIGURE 11. POWER CONSUMPTION vs FREQUENCY AND LOAD 6 VON = 20V VOFF = -14V RCS = 500Ω 600 400 4700pF 1000pF 200 220pF 0 0 50 100 150 200 INPUT FREQUENCY (kHz) FIGURE 12. POWER CONSUMPTION vs FREQUENCY AND LOAD FN6167.2 February 20, 2008 EL5000A Typical Performance Curves (Continued) JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.8 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.6 1.0 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 845mW 0.8 θ JA 0.6 TS =+ SO 14 P1 8° 6 C/ W 0.4 0.2 1.4 1.289W 1.2 θ TS SO P +9 16 7° C/ W JA = 1.0 0.8 0.6 0.4 0.2 0 0 25 75 85 100 50 125 0 150 0 AMBIENT TEMPERATURE (°C) FIGURE 13. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Pin Descriptions PIN NUMBER (16 LD TSSOP) PIN NAME 1 VON Positive supply 2 CKV High voltage output, scan clock out 3 CKVCS 4 NC 5 CKVBCS 6 CKVB High voltage output, scan clock even 7 STVP High voltage output, scan start pulse 8 VOFF Negative supply 9 GND Ground 10 CPV H sync timing, H sync clock 1 11 OE Writing timing, H sync clock 2 12 STV V sync timing, V sync 13 GND Ground, logic return 14 OECON 15 DISH Discharge function input, VOFF discharge 16 VDD Logic power supply 7 PIN FUNCTION Discharge switch input, CKV charge share No connect Discharge switch input, CKVB charge share OE disable input, OE blank FN6167.2 February 20, 2008 EL5000A CKV STV CPV VIDEO SOURCE HIGH VOLTAGE REGISTER COLUMN DRIVER EL5000A OE STVP CKVB C FIGURE 15. EL5000A SYSTEM BLOCK DIAGRAM Application Information General Description The EL5000A is a high performance 70V TFT-LCD row driver. It level shifts TTL level timing signals from the video source into 70VP-P output voltage. Its output is capable of delivering 100mA peak current into 1nF of capacitive load. It also incorporates logic to control the output timings. The logic timing control circuit is powered from 3.3V supply. Figure 15 shows the system block diagram. CL capacitors model the capacitive loading appeared at the inputs of the TFT-LCD panel for the CKV and the CKVB signals. The CL is typically between 1nF and 5nF. In addition to switches SW1, SW2, SW3, and SW4, a fifth switch is added to reduce the power dissipation and shape the output waveform. Figure 17 shows the location of the additional SW5 switch. Input Signals The device performs beside of level transformation also logic operation between the input signals: • STV - Vertical Sync Timing signal, frequency range around 60Hz • CPV - Horizontal Sync Timing signal, frequency range up to 166kHz SW1 SW2 CKV r SW5 CKVB r Rd CL CL SW3 SW4 • OE - Output Enable Write Signal, frequency range up to 166kHz FIGURE 17. BI-DIRECTIONAL SWITCHES Output Signals The output signals, CKV and CKVB are generated by EL5000A internal switches. Figure 16 depicts the simplified schematic of the output stage and interface. In reality, each switch consists of two such switches, one for the positive discharge and one for the negative discharge, see Figure 18. CKV SW1 r SW5 D1 Rd1 D2 SW5 CKVB SW2 Rd2 CKV CKVB CL CL SW3 SW4 FIGURE 16. SIMPLIFIED SCHEMATIC OF OUTPUT STAGE 8 FIGURE 18. BI-DIRECTIONAL SWITCHES Due to the actual solid-state construction of the switches, the capacitors CL does not get discharged entirely. The amount of left over charges depends on the value of the voltages of VON and VOFF on the capacitors. FN6167.2 February 20, 2008 EL5000A Internal Logic Block Diagram Figures 19 and 20 show the internal block diagram. In order to reduce power dissipation, most of the logic circuitry is powered from 3.3V logic supply. The output of the 3.3V logic is level-shifted to drive the output switches. CPVC CPV OE CPVX OECON ECS D STV Q CL CLK OCS Q FIGURE 19. INTERNAL LOGIC BLOCK DIAGRAM CPVX D1 CKV SCAN CLK ODD OCS D2 D3 ECS D4 CKVB SCAN CLK EVEN STV D5 CPVC SW STVP HIGH VOLTAGE STV D6 CSS SW SW CKVBCS CKVCS FIGURE 20. INTERNAL LOGIC BLOCK DIAGRAM AND OUTPUT SWITCHES 9 FN6167.2 February 20, 2008 EL5000A Output Waveforms Figure 22 shows the delay time between the incoming horizontal sync timing pulse CPV and the generated output pulses. Δt is dependent mainly on the value of CL. Figure 23 shows the effect of STV. Figure 21 shows a typical CKV and CKVB output waveforms. The output droop rate depends on the external discharge resistor value and the output capacitor load. CKV CKV CKVB STV CKVB FIGURE 21. CKV AND CKVB OUTPUT WAVEFORMS CPV FIGURE 23. EFFECT OF STV CKV Auxiliary Functions CKVB DISH: It discharges VOFF when the logic power voltage level drops out, when 'DISH' is < -0.6V (VCC system power turns off), VOFF is connected to ground level by 1kΩ. OECON: It provides continuos polarity changes to the TFT-LCD panel during the vertical blanking. CPV FIGURE 22. CPV TO CKV/CKVB DELAY +18V TO +40V VCC HSYNC TIMING 2 CKV 3 CKVCS 6 CKVB 5 CKVBCS R2 5k R R3 5k VOFF GND VSYNC TIMING VON 16 VDD DISCH 14 OECON 12 STV 10 CPV 11 OE GND 15 C3 22µF C2 0.1µF 1 C1 0.1µF C4 1µF STVP C10 8 13 9 R6 ca 20k* R C 7 EL5000 WRITING TIMING C R C C8 0.1µF C9 22µF TFT-LCD 2nF* -9V TO -20V FIGURE 24. TYPICAL APPLICATION CIRCUIT 10 FN6167.2 February 20, 2008 EL5000A Power Dissipation +40V The dissipated power in R3 and R6 could be calculated as follows: 23V We assume that: +17 V • VON = 40V +3.3 V 0V • VOFF = -20V 23V • H sync timing frequency = 60kHz • CL = 5nF -20V The value of VL (the left over voltage) in the capacitors in that case is 23V for the positive discharge and 3.3V for the negative discharge. FIGURE 25. The voltage change across the capacitor is therefore 23V; see Figure 25. The stored energy in the capacitor is shown in Equation 1: 2 2 -9 1/2 × V C = 1/2 × 23 × 5 × 10 = 132μJ (EQ. 1) The energy, which is stored in the capacitor, will be dissipated on the resistor; see Figure 26. The switch will close 2 x 60,000 in every second. The process will be repeated 2 times for the CKV and the CKVB. In 120,000 cycles per second, the power dissipation in R3 and R6 becomes Equation 2: 2 × 1.32 × 10 -6 3 × 60 × 10 = 160mW 11 (EQ. 2) FIGURE 26. For different values of VON, VOFF, CL and H sync timing frequency, the worst case dissipation can be calculated in a similar matter. The value of the R3 and R6 must be selected such that the capacitor CL is discharged via R3 or R6 resistor in one half period of the H sync timing. Figures 13 and 14 show the total power dissipation over a range of possible voltages, operating frequencies and loads. Care should be taken to prevent the power from exceeding the maximum rating of the package, as shown in Figure 13. FN6167.2 February 20, 2008 EL5000A Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A (N/2)+1 N MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 1 (N/2) B 0.20 C B A 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 0.10 M C A B b 0.10 C N LEADS SIDE VIEW NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL “X” 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN6167.2 February 20, 2008