IRFF230 Data Sheet March 1999 5.5A, 200V, 0.400 Ohm, N-Channel Power MOSFET • 5.5A, 200V Formerly developmental type TA17412. Ordering Information IRFF230 PACKAGE TO-205AF 1892.3 Features This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. PART NUMBER File Number • rDS(ON) = 0.400Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol BRAND D IRFF230 NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-205AF SOURCE DRAIN (CASE) GATE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRFF230 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFF230 200 200 5.5 22 ±20 25 0.2 85 -55 to 150 UNITS V V A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. TC = 25oC, Unless Otherwise Specified Electrical Specifications MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS VGS = 0V, ID = 250µA (Figure 10) 200 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V - - 25 µA Zero-Gate Voltage Drain Current On-State Drain Current (Note 2) IDSS ID(ON) Gate to Source Leakage Forward Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time IGSS rDS(ON) - 250 µA 5.5 - - A VGS = ±20V - - ±100 nA VGS = 10V, ID = 3.0A (Figures 8, 9) - 0.25 0.4 Ω 2.5 4.5 - S VDD ≅ 0.5 x Rated BVDSS, ID ≈ 5.5A, RG = 9.1Ω, VGS = 10V, RL = 28.7Ω For VDSS = 160V, RL = 21.4Ω For VDSS = 120V (Figures 17, 18) MOSFET Switching Times are Essentially Independent of Operating Temperature - - 30 ns - - 50 ns - - 50 ns Qg(TOT) Gate to Source Charge - VDS > ID(ON) x rDS(ON)MAX , VGS = 10V (Figure 7) VDS >ID(ON) x rDS(ON)MAX, ID = 3.0A (Figure 12) tf Total Gate Charge (Gate to Source + Gate to Drain) VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC gfs td(OFF) Fall Time VDS = Rated BVDSS, VGS = 0V td(ON) tr Turn-Off Delay Time TEST CONDITIONS Qgs - - 40 ns VGS = 10V, ID = 5.5A, VDS = 0.8 x Rated BVDSS , IG(REF) = 1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature - 19 30 nC - 10 - nC - 9.0 - nC VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - 600 - pF Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS - 250 - pF Reverse-Transfer Capacitance CRSS - 80 - pF - 5.0 - nH - 15 - nH Internal Drain Inductance LD Internal Source Inductance LS Measured from the Drain Modified MOSFET Lead, 5mm (0.2in) from Symbol Showing the Header to Center of Die Internal Device Inductances Measured from the Source Lead, 5mm (0.2in) from Header to Source Bonding Pad D LD G LS S Junction to Case RθJC - - 5.0 oC/W Junction to ambient RθJA - - 175 oC/W 2 IRFF230 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS MIN TYP MAX UNITS - - 5.5 A - - 22 A TJ = 25oC, ISD = 5.5A, VGS = 0V (Figure 13) - - 2.0 V TJ = 150oC, ISD = 5.5A, dISD/dt = 100A/µs TJ = 150oC, ISD = 5.5A, dISD/dt = 100A/µs - 450 - ns - 3.0 - µC Intrinsic Turn-On Time is Negligible, Turn-On Speed is Substantially Controlled by LS + LD - - - - Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier D G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovered Charge QRR Forward Turn-On Time tON NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 20V, start TJ = 25oC, L = 8.9mH, RG = 50Ω, peak IAS = 5.5A (Figures 15, 16). Typical Performance Curves Unless Otherwise Specified 6.0 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 0 50 100 4.8 3.6 2.4 1.2 0 25 150 50 TC, CASE TEMPERATURE (oC) 75 100 125 150 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1.0 0.5 ZθJC , NORMALIZED THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 0.2 PDM 0.1 0.1 t1 0.05 t2 0.02 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 0.01 SINGLE PULSE 10-2 10-5 10-4 10-3 10-2 10-1 T1 , RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 1 10 IRFF230 Typical Performance Curves (Continued) 20 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 10 10µs 100µs 1ms 1.0 10ms TC = 25oC TJ = MAX RATED SINGLE PULSE VGS = 6V 8 VGS = 5V 4 VGS = 4V 0 103 0 10 6 VGS = 6V ID, ON-STATE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 80µs PULSE TEST 8 VGS = 5V 4 2 VGS = 4V 80 60 100 VDS > ID(ON) x rDS(ON) MAX 80µs PULSE TEST 8 6 TJ = 125oC TJ = 25oC TJ = -55oC 4 2 0 0 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 5 FIGURE 6. SATURATION CHARACTERISTICS 2.2 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2µs PULSE TEST VGS = 10V 0.6 0.4 VGS = 20V 0.2 0 0 10 20 30 ID, DRAIN CURRENT (A) 1 2 4 5 3 VGS , GATE TO SOURCE VOLTAGE (V) 6 40 ID = 3A VGS = 10V 1.8 1.4 1.0 0.6 0.2 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) NOTE: Heating effect of 2µs pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4 7 FIGURE 7. TRANSFER CHARACTERISTICS 0.8 ON RESISTANCE (Ω) 40 FIGURE 5. OUTPUT CHARACTERISTICS 10 VGS = 10V VGS = 9V VGS = 8V VGS = 7V 20 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA rDS(ON) , DRAIN TO SOURCE VGS = 7V 12 DC 10 102 VDS , DRAIN TO SOURCE VOLTAGE (V) 1 80µs PULSE TEST 16 100ms 0.1 VGS = 8V VGS = 10V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 100 Unless Otherwise Specified FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 160 IRFF230 Typical Performance Curves Unless Otherwise Specified (Continued) 2000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD ID = 250µA 1.15 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 1.05 0.95 1600 1200 0.85 0.75 0 -40 40 80 800 CISS 400 COSS CRSS 0 160 120 0 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 102 ISD, SOURCE TO DRAIN CURRENT (A) 8 TJ = -55oC TJ = 25oC TJ = 125oC 4 2 TJ = 25oC TJ = 150oC 10 TJ = 150oC TJ = 25oC 1.0 0 0 2 6 4 ID, DRAIN CURRENT (A) 8 0 10 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 20 VGS, GATE TO SOURCE VOLTAGE (V) gfs, TRANSCONDUCTANCE (S) 80µs PULSE TEST 6 50 1 2 3 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE ID = 5.5A 15 VDS = 40V VDS = 100V VDS = 60V 10 5 0 0 8 16 24 32 40 Qg(TOT), TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 4 IRFF230 Test Circuits and Waveforms VDS BVDSS tP VDS L IL VARY tP TO OBTAIN VDD + RG REQUIRED PEAK IAS - VDD DUT tP 0V 0 IL tAV 0.01Ω FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2µF 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 IG(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 6 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRFF230 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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