IRF830 Data Sheet July 1999 4.5A, 500V, 1.500 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17415. Ordering Information PART NUMBER IRF830 PACKAGE TO-220AB File Number 1582.3 Features • 4.5A, 500V • rDS(ON) = 1.500Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol D BRAND IRF830 G NOTE: When ordering, include the entire part number. S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) 4-251 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRF830 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF830 500 500 4.5 3.0 18 ±20 75 0.6 300 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS VGS = 0V, ID = 250µA (Figure 10) 500 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS , ID = 250µA 2.0 - 4.0 V - - 25 µA µA Zero-Gate Voltage Drain Current IDSS TEST CONDITIONS VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC On-State Drain Current (Note 2) Gate to Source Leakage ID(ON) IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge - 250 - - A - - ±100 nA - 1.3 1.5 Ω 4.2 - S - 10 17 ns - 15 23 ns td(OFF) - 33 53 ns tf - 16 23 ns VGS = 10V, ID ≈ 4.5A, VDS = 0.8 x Rated BVDSS Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature. - 22 32 nC - 3.5 - nC - 11 - nC VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - 600 - pF gfs tr Turn-Off Delay Time VGS = ±20V 4.5 2.5 rDS(ON) td(ON) Rise Time VDS > ID(ON) x rDS(ON)MAX , VGS = 10V Qg(TOT) Qgs VGS = 10V, ID = 2.5A (Figures 8, 9) VDS ≥ 10V, ID = 2.7A (Figure 12) VDD = 250V, ID ≈ 4.5A, RG = 12Ω, RL = 54Ω MOSFET Switching Times are Essentially Independent of Operating Temperature. Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS - 100 - pF Reverse-Transfer Capacitance CRSS - 20 - pF - 3.5 - nH - 4.5 - nH - 7.5 - nH - - 1.67 oC/W - - 62.5 oC/W Internal Drain Inductance LD Measured from the Modified MOSFET Contact Screw on Tab to Symbol Showing the Center of Die Internal Devices Measured from the Drain Inductances D Lead, 6mm (0.25in) From Package to Center of Die Internal Source Inductance LS Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA 4-252 Measured from the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad Free Air Operation LD G LS S IRF830 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode D MIN TYP MAX UNITS - - 4.5 A - - 18 A - - 1.6 V 180 350 760 ns 0.96 2.2 4.3 µC G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovered Charge QRR TJ = 25oC, ISD = 4.5A, VGS = 0V (Figure 13) TJ = 25oC, ISD = 4.5A, dISD/dt = 100A/µs TJ = 25oC, ISD = 4.5A, dISD/dt = 100A/µs NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 25mH, RG = 25Ω, peak IAS = 4.5A. Typical Performance Curves Unless Otherwise Specified 5 ID , DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 4 3 2 1 0 0 0 50 100 150 25 50 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 75 100 125 TC , CASE TEMPERATURE (oC) 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 THERMAL IMPEDANCE ZθJC , NORMALIZED TRANSIENT POWER DISSIPATION MULTIPLIER 1.2 0.5 0.2 0.1 PDM 0.1 0.05 0.02 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 0.1 t1 , RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-253 1 10 IRF830 Typical Performance Curves Unless Otherwise Specified (Continued) 6 OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 10 10µs 100µs 1 1ms 10ms 100ms DC TC = 25oC TJ = MAX RATED SINGLE PULSE 0.1 102 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 1 VGS = 5.0V 4 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 3 VGS = 4.5V 2 1 VGS = 4.0V 0 103 0 50 VGS = 10V 4 VGS = 5.5V VGS = 5.0V 3 VGS = 4.5V 2 1 VGS = 4.0V 0 0 2 4 6 8 VDS , DRAIN TO SOURCE VOLTAGE (V) 10 5 4 3 TJ = 125oC TJ = 25oC 2 TJ = -55oC 1 0 0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE ON RESISTANCE (Ω) rDS(ON) , DRAIN TO SOURCE 2.2 8 6 VGS = 10V 4 VGS = 20V 2 0 4 16 8 12 TC , CASE TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4-254 300 1 2 3 4 5 VGS , GATE TO SOURCE VOLTAGE (V) 6 7 FIGURE 7. TRANSFER CHARACTERISTICS PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 0 250 200 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS > ID(ON) x rDS(ON)MAX FIGURE 6. SATURATION CHARACTERISTICS 10 150 FIGURE 5. OUTPUT CHARACTERISTICS IDS(ON), DRAIN TO SOURCE CURRENT (A) ID , DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 100 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 5 VGS = 5.5V VGS = 10V 5 ID , DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 102 20 1.8 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 2.5A, VGS = 10V 1.4 1.0 0.6 0.2 -60 -40 -20 0 20 40 60 80 100 120 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 140 IRF830 Typical Performance Curves 2000 ID = 250µA 1.15 1.05 0.95 0.85 0.75 -40 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGS 1600 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 Unless Otherwise Specified (Continued) 1200 CISS 800 COSS 400 -20 0 20 40 60 80 100 120 140 CRSS 0 160 10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V) 1 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 2 ISD , SOURCE TO DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TJ = -55oC TJ = 25oC 3 TJ = 125oC 2 1 0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 100 5 2 TJ = 150oC 10 5 TJ = 25oC 2 1 0 1 2 3 ID , DRAIN CURRENT (A) 4 0 5 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 1 2 3 VSD , SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS , GATE TO SOURCE VOLTAGE (V) gfs , TRANSCONDUCTANCE (S) 5 4 50 ID = 4.5A 15 VDS = 100V VDS = 250V 10 VDS = 400V 5 0 0 8 16 24 32 40 Qg , GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-255 4 IRF830 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN + RG REQUIRED PEAK IAS - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2µF 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 Ig(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 4-256 Ig(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRF830 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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