INTERSIL EL8188

EL8188
®
Data Sheet
PRELIMINARY
February 22, 2007
Micropower Single Supply Rail-to-Rail
Input-Output Precision Op Amp
The EL8188 is a micropower precision op amp optimized for
single supply operation at 5V and can operate down to 2.4V.
The EL8188 draws minimal supply current while meeting
excellent DC-accuracy, noise, and output drive
specifications. Competing devices seriously degrade these
parameters to achieve rail-to-rail operation and microamp
supply current. Offset current, voltage and current noise,
slew rate, and gain-bandwidth product are all 2X to 10X
better than on previous micropower rail-to-rail op amps.
FN7467.3
Features
• 50µA supply current
• 1mV typ offset voltage
• 2pA input bias current
• 266kHz gain-bandwidth product
• 0.13V/µs slew rate
• Single supply operation down to 2.4V
• Rail-to-rail input and output
• Output sources and sinks 26mA load current
The EL8188 can be operated from one lithium cell or two
Ni-Cd batteries. The input range includes both the positive
and negative rails. The output swings to both rails.
• Pb-free plus anneal available (RoHS compliant)
Ordering Information
• Battery- or solar-powered systems
PART
MARKING
TAPE &
REEL
8178FW
7”
6 Ld SOT-23 MDP0038
(3k pcs)
8178FW
Coming Soon
EL8188FWZ-T7A
(Note)
7”
6 Ld SOT-23 MDP0038
(250 pcs)
EL8188FSZ
(Note)
8178FSZ
97/Tube 8 Ld SO
MDP0027
EL8188FSZ-T7
(Note)
8178FSZ
7”
8 Ld SO
(1k pcs)
MDP0027
PART NUMBER
Coming Soon
EL8188FWZ-T7
(Note)
PACKAGE
(Pb-Free)
PKG.
DWG. #
Applications
• 4mA to 20mA current loops
• Handheld consumer products
• Medical devices
• Thermocouple amplifiers
• Photodiode pre-amps
• pH probe amplifiers
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Pinouts
EL8188
(6 LD SOT-23 - Coming Soon)
TOP VIEW
OUT 1
VS- 2
6 VS+
+ -
IN+ 3
5 ENABLE
4 IN-
EL8188
(8 LD SO)
TOP VIEW
NC 1
IN- 2
IN+ 3
VS- 4
1
8 ENABLE
+
7 VS+
6 OUT
5 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL8188
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage (VS) and Pwr-up Ramp Rate . . . . . . . . 5.5V, 1V/µs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V
Current into IN+, IN-, and ENABLE . . . . . . . . . . . . . . . . . . . . . . 5mA
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V
ESD tolerance, Human Body Model . . . . . . . . . . . . . . . . . . . TBDkV
ESD tolerance, Machine Model . . . . . . . . . . . . . . . . . . . . . . . TBDV
Thermal Resistance
θJA (°C/W)
6 Ld SOT Package . . . . . . . . . . . . . . . . . . . . . . . . .
230
8 Ld SO Package . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Ambient Operating Temperature Range . . . . . . . . -40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = 5V, VS- = 0V, VCM = 0.1V, VO = 1.4V, TA = +25°C unless otherwise specified. Boldface limits apply over
the operating temperature range, -40°C to +125°C
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1
4
mV
VOS
Input Offset Voltage
ΔV OS
-----------------ΔTime
Long Term Input Offset Voltage
Stability
1.2
ΔV OS
---------------ΔT
Input Offset Drift vs Temperature
1.1
2.1
µV/°C
IB
Input Bias Current
2
15
pA
600
pA
SOT
-15
-600
µV/Mo
Input Noise Voltage Peak-to-Peak
f = 0.1Hz to 10Hz
2.8
µVP-P
Input Noise Voltage Density
fO = 1kHz
48
nV/√Hz
iN
Input Noise Current Density
fO = 1kHz
0.15
pA/√Hz
CMIR
Input Voltage Range
Guaranteed by CMRR test
0
CMRR
Common-Mode Rejection Ratio
VCM = 0V to 5V
80
eN
5
V
100
dB
75
PSRR
Power Supply Rejection Ratio
VS = 2.4V to 5V
80
dB
100
dB
80
AVOL
VOUT
Large Signal Voltage Gain
Maximum Output Voltage Swing
VO = 0.5V to 4.5V,
RL = 100kΩ to (VS+ + VS-)/2
100
Slew Rate
GBWP
Gain Bandwidth Product
15
VOL; Output low,
RL = 100kΩ to (VS+ + VS-)/2
3
130
VOH; Output high,
RL = 100kΩ to (VS+ + VS-)/2
4.994
VOH; Output high,
RL = 1kΩ to (VS+ + VS-)/2
4.750
fO = 100kHz
V/mV
V/mV
VO = 0.5V to 4.5V,
RL = 1kΩ to (VS+ + VS-)/2
V/mV
8
mV
10
mV
200
mV
300
mV
4.997
V
4.992
V
4.867
V
4.7
0.05
2
400
100
VOL; Output low,
RL = 1kΩ to (VS+ + VS-)/2
SR
dB
V
0.13
266
0.25
V/µs
kHz
FN7467.3
February 22, 2007
EL8188
Electrical Specifications
PARAMETER
IS, ON
VS+ = 5V, VS- = 0V, VCM = 0.1V, VO = 1.4V, TA = +25°C unless otherwise specified. Boldface limits apply over
the operating temperature range, -40°C to +125°C (Continued)
DESCRIPTION
TEST CONDITIONS
Supply Current, Enabled
MIN
TYP
MAX
UNIT
35
50
75
µA
90
µA
10
µA
10
µA
30
IS, OFF
ISC+
Supply Current, Disabled
Short Circuit Output Current
3
RL = 10Ω to opposite supply
23
31
mA
18
ISC-
Short Circuit Output Current
RL = 10Ω to opposite supply
20
mA
26
mA
15
VS
Minimum Supply Voltage
VINH
Enable Pin High Level
VINL
Enable Pin Low Level
IENH
Enable Pin Input Current
mA
2.2
Enable Pin Input Current
VEN = 5V
0.25
VEN = 0V
-0.5
-0.5
3
V
2.4
V
2
V
0.7
0.25
IENL
2.4
0
0.8
V
2
µA
2.5
µA
+0.5
µA
+0.5
µA
FN7467.3
February 22, 2007
EL8188
Typical Performance Curves
VS = ±2.5V, TA = +25°C, Unless Otherwise Specified
1
80
RL ≥ 10kΩ
VOUT = 0.2VP-P
GAIN = 1k
70
60
0
RL ≥ 10kΩ
VOUT = 0.2VP-P
GAIN = 500
GAIN (dB)
GAIN (dB)
50
VS = ±1.25
-1
VS = ±2.5V
GAIN = 200
40
GAIN = 100
GAIN = 10
30
GAIN = 5
20
10
-2
GAIN = 2
0
VS = ±1.0V
-3
1k
10k
-10
100k
GAIN = 1
-20
1M
1
10
100
FREQUENCY (Hz)
100k 1M
10M
FIGURE 2. FREQUENCY RESPONSE at VARIOUS CLOSED
LOOP GAINS
200
INPUT OFFSET VOLTAGE (μV)
60
SUPPLY CURRENT µA)
10k
FREQUENCY (Hz)
FIGURE 1. UNITY GAIN FREQUENCY RESPONSE at
VARIOUS SUPPLY VOLTAGES
50
40
30
20
10
0
2
2.5
3
4
3.5
4.5
5
AV = -1
VCM = VDD/2
100
0
-100
-200
-0.5
5.5
0.5
SUPPLY VOLTAGE (V)
150
50
-50
-150
0.5
1.5
2.5
3.5
4.5
5.5
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 5. INPUT OFFSET VOLTAGE vs COMMON-MODE
INPUT VOLTAGE
4
2.5
3.5
4.5
5.5
FIGURE 4. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE
INPUT BIAS, OFFSET CURRENT (fA)
250
-250
-0.5
1.5
OUTPUT VOLTAGE (V)
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
INPUT OFFSET VOLTAGE (µV)
1k
20
IOS
10
IB0
-10
-20
-0.5
IB+
0.5
1.5
2.5
3.5
5.5
4.5
COMMON-MODE INPUT VOLTAGE (V)
FIGURE 6. INPUT BIAS, OFFSET CURRENT vs COMMONMODE INPUT VOLTAGE
FN7467.3
February 22, 2007
EL8188
Typical Performance Curves
(Continued) VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued)
100
100
90
80
80
0
60
45
20
135
GAIN
PHASE
40
135
30
20
0
-10
-20
10
1k
100
10k
100k
10
1M
100
FIGURE 7. OPEN LOOP GAIN AND PHASE vs FREQUENCY
(RL = 1kΩ)
10
0
-10
-20
-20
-30
-30
PSRR (dB)
CMRR (dB)
-10
-40
100k
1M
-50
-60
ΔVS = 1VP-P
RL = 100kΩ
AV = +1
-PSRR
-40
-50
+PSRR
-60
-70
-70
-80
-80
-90
-90
-100
10
100
1k
10k
100k
-100
10
1M
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 10. PSRR vs FREQUENCY
FIGURE 9. CMRR vs FREQUENCY
VOLTAGE
1
10
CURRENT
1
1
10
100
1k
10k
0.1
100k
VOLTAGE NOISE (500nV/DIV)
10
100
CURRENT NOISE (pA/√Hz)
100
1000
VOLTAGE NOISE (nV/√Hz)
10k
FIGURE 8. OPEN LOOP GAIN AND PHASE vs FREQUENCY
(RL = 100kΩ)
ΔVCM = 1VP-P
RL = 100kΩ
AV = +1
0
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
10
180
GAIN
10
180
0
90
50
PHASE SHIFT (°)
90
40
60
GAIN (dB)
PHASE
PHASE SHIFT (°)
GAIN (dB)
70
2.8µVP-P
TIME (1s/DIV)
FREQUENCY (Hz)
FIGURE 11. INPUT VOLTAGE AND CURRENT NOISE vs
FREQUENCY
5
FIGURE 12. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
FN7467.3
February 22, 2007
EL8188
Typical Performance Curves
(Continued) VS = ±2.5V, TA = +25°C, Unless Otherwise Specified (Continued)
400
10 SAMPLES
300
100
200
50
VOS (µV)
INPUT OFFSET VOLTAGE (µV)
150
0
100
0
-100
-50
-200
-100
35 SOIC SAMPLES
TYPICAL = 1.1µV/C
-300
-150
0
10
20
30
40
50
60
70
80
90
-400
-60
100
-40
-20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 14. EL8188 SOIC VOS vs TEMPERATURE (VS = 5V)
FIGURE 13. VOS vs TEMPERATURE
800
600
35 6 LD SOT-23 SAMPLES
TYPICAL = 1.9µV/C
VOS (µV)
400
200
0
-200
-400
-600
-800
-60
-40
-20
0
20
40
60
80
100 120
TEMPERATURE (°C)
FIGURE 15. EL8188 SOT VOS vs TEMPERATURE (VS = 5V)
20
18
n = 10
10
5
MEDIAN
0
-5
-10
-15
500
1000
1500
HOURS
FIGURE 16. VOS DRIFT SOT-23 vs TIME
6
MAX
8
MEDIAN
3
-2
-7
MIN
0
n = 10
13
MAX
VOS DRIFT (µV)
VOS DRIFT (µV)
15
1900
-12
MIN
0
500
1000
1500
1900
HOURS
FIGURE 17. VOS DRIFT SOIC vs TIME
FN7467.3
February 22, 2007
EL8188
Pin Descriptions
SO PIN
NUMBER
SOT-23 PIN
NUMBER
PIN NAME
1
EQUIVALENT
CIRCUIT
NC
DESCRIPTION
No internal connection
2
4
IN-
Circuit 1
Amplifier’s inverting input
3
3
IN+
Circuit 1
Amplifier’s non-inverting input
4
2
VS-
Circuit 4
Negative power supply
5
NC
No internal connection
6
1
OUT
Circuit 3
Amplifier’s output
7
6
VS+
Circuit 4
Positive power supply
8
5
ENABLE
Circuit 2
Amplifier’s enable pin with internal pull-down; Logic “1” selects the disabled state;
Logic “0” selects the enabled state.
VS+
VS+
IN-
IN+
CAPACITIVELY
COUPLED
ESD CLAMP
VS-
VS-
CIRCUIT 2
Application Information
Introduction
The EL8188 is a rail-to-rail input and output (RRIO), micropower, precision, single supply op amp with an enable
feature. This amplifier is designed to operate from single
supply (2.4V to 5.0V) or dual supply (±1.2V to ±2.5V) while
drawing only 50µA of supply current.The device achieves
rail-to-rail input and output operation while eliminating the
drawbacks of many conventional RRIO op amps.
Rail-to-Rail Input
The PFET input stage of the EL8188 has an input commonmode voltage range that includes the negative and positive
supplies without introducing offset errors or degrading
performance like some existing rail-to-rail input op amps.
Many rail-to-rail input stages use two differential input pairs:
a long-tail PNP (or PFET) and an NPN (or NFET). Severe
penalties result from using this topology. As the input signal
moves from one supply rail to the other, the op amp switches
from one input pair to the other causing drastic changes in
input offset voltage and an undesired change in the input
offset current’s magnitude and polarity.
The EL8188 achieves rail-to-rail input performance without
sacrificing important precision specifications and without
degrading distortion performance. The EL8188's input offset
voltage exhibits a smooth behavior throughout the entire
common-mode input range.
7
VS+
OUT
ENABLE
VS-
CIRCUIT 1
VS+
VSCIRCUIT 3
CIRCUIT 4
Rail-to-Rail Output
A pair of complementary MOSFET devices achieves rail-to-rail
output swing. The NMOS sinks current to swing the output in
the negative direction, while the PMOS sources current to
swing the output in the positive direction. The EL8188 with a
100kΩ load swings to within 3mV of the supply rails.
Enable/Disable Feature
The EL8188 features an active low ENABLE pin that when
pulled up to at least 2V disables the output, and drops the
already low ICC to a 3µA trickle. The ENABLE pin has an
internal pull down, so an undriven pin pulls to the negative
rail, thereby enabling the op amp by default.
The high impedance output during disable allows for
connecting multiple EL8188s together to implement a Mux
Amp. The outputs are connected together and activating the
appropriate ENABLE pin selects the desired channel. If
utilizing non-unity gain op amp configurations, then the
loading effects of the disabled amplifiers’ feedback networks
must be considered when evaluating the active amplifier’s
performance in Mux Amp configurations.
Note that feedthrough from the IN+ to IN- pins occurs on any
Mux Amp disabled channel where the input differential
voltage exceeds 0.5V (e.g., active channel VOUT = 1V, while
disabled channel VIN = GND), so the mux implementation is
best suited for small signal applications. If large signals are
required, use series IN+ resistors, or large value RFs, to
keep the feedthrough current low enough to minimize the
impact on the active channel. See the “Usage Implications”
on page 8 for more details.
FN7467.3
February 22, 2007
EL8188
IN+ and IN- Input Protection
In addition to ESD protection diodes to each supply rail, the
EL8188 has additional back-to-back protection diodes across
the differential input terminals (see “Circuit 1” on page 7).
Obviously, one of these diodes conducts if the magnitude of
the differential input voltage ever exceeds the diode’s VF.
the safe operating area. These parameters are related as
follows:
T JMAX = T MAX + ( θ JA × PD MAX )
(EQ. 1)
where PDMAX is calculated using:
V OUTMAX
PD MAX = V S × I SMAX + ( V S - V OUTMAX ) × ---------------------------R
Usage Implications
If the input differential voltage is expected to exceed 0.5V, an
external current limiting resistor must be used to ensure the
input current never exceeds 5mA. For noninverting unity gain
applications the current limiting can be via a series IN+ resistor,
or via a feedback resistor of appropriate value. For other gain
configurations, the series IN+ resistor is the best choice, unless
the feedback (RF) and gain setting (RG) resistors are both
sufficiently large to limit the input current to 5mA.
Large differential input voltages can arise from several
sources:
1) During open loop (comparator) operation. Used this way,
the IN+ and IN- voltages don’t track, so differentials arise.
2) When the amplifier is disabled but an input signal is still
present. An RL or RG to GND keeps the IN- at GND, while
the varying IN+ signal creates a differential voltage. Mux
Amp applications are similar, except that the active channel
VOUT determines the voltage on the IN- terminal.
3) When the slew rate of the input pulse is considerably
faster than the op amp’s slew rate. If the VOUT can’t keep up
with the IN+ signal, a differential voltage results, and visible
distortion occurs on the input and output signals. To avoid
this issue, keep the input slew rate below 0.2V/µs, or use
appropriate current limiting resistors.
Large (>2V) differential input voltages can also cause an
increase in disabled ICC.
ENABLE Input Protection
The ENABLE input has internal ESD protection diodes to both
the positive and negative supply rails, limiting the input
voltage range to within one diode beyond the supply rails (see
“Circuit 2” on page 7). If the input voltage is expected to
exceed VS+ or VS-, then an external series resistor should be
added to limit the current to 5mA.
L
(EQ. 2)
where:
• TMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of the amplifier
• VS = Supply voltage
• IMAX = Maximum supply current of the amplifier
• VOUTMAX = Maximum output voltage swing of the
application
• RL = Load resistance
Proper Layout Maximizes Precision
To achieve the optimum levels of high input impedance (i.e.,
low input currents) and low offset voltage, care should be
taken in the circuit board layout. The PC board surface must
remain clean and free of moisture to avoid leakage currents
between adjacent traces. Surface coating of the circuit board
will reduce surface moisture and provide a humidity barrier,
reducing parasitic resistance on the board. When input
leakage current is a paramount concern, the use of guard
rings around the amplifier inputs will further reduce leakage
currents. Figure 18 shows a guard ring example for a unity
gain amplifier that uses the low impedance amplifier output
at the same voltage as the high impedance input to eliminate
surface leakage. The guard ring does not need to be a
specific width, but it should form a continuous loop around
both inputs. For further reduction of leakage currents, mount
components to the PC board using Teflon standoffs.
HIGH IMPEDANCE INPUT
V+
IN
Output Current Limiting
The EL8188 has no internal current-limiting circuitry. If the
output is shorted, it is possible to exceed the “Absolute
Maximum Rating” for “operating junction temperature”,
potentially resulting in the destruction of the device.
Power Dissipation
FIGURE 18. GUARD RING EXAMPLE FOR UNITY GAIN
AMPLIFIER
It is possible to exceed the +150°C maximum junction
temperature (TJMAX) under certain load and power-supply
conditions. It is therefore important to calculate TJMAX for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to remain in
8
FN7467.3
February 22, 2007
EL8188
Typical Applications
GENERAL
PURPOSE
COMBINATION
pH PROBE
VS+
+
EL8188
VS-
R4
100kΩ
+
3V
COAX
R3
10kΩ
R2
10kΩ
K TYPE
THERMOCOUPLE
VS+
+
EL8188
VS-
410µV/°C
+
5V
FIGURE 19. pH PROBE AMPLIFIER
A general-purpose combination pH probe has extremely
high output impedance typically in the range of 10GΩ to
12GΩ. Low loss and expensive Teflon cables are often used
to connect the pH probe to the meter electronics. Figure 19
details a low-cost alternative solution using the EL8188 and
a low-cost coax cable. The EL8188 PMOS high impedance
input senses the pH probe output signal and buffers it to
drive the coax cable. Its rail-to-rail input nature also
eliminates the need for a bias resistor network required by
other amplifiers in the same application.
9
R1
100kΩ
FIGURE 20. THERMOCOUPLE AMPLIFIER
Thermocouples are the most popular temperature sensing
devices because of their low cost, interchangeability, and
ability to measure a wide range of temperatures. In
Figure 20, the EL8188 converts the differential thermocouple
voltage into single-ended signal with 10X gain. The
EL8188's rail-to-rail input characteristic allows the
thermocouple to be biased at ground and permits the
op amp to operate from a single 5V supply.
FN7467.3
February 22, 2007
EL8188
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M C A B
e
H
C
A2
GAUGE
PLANE
SEATING
PLANE
A1
0.004 C
0.010 M C A B
L
b
0.010
4° ±4°
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SYMBOL
SO-14
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
TOLERANCE
NOTES
A
0.068
0.068
0.068
0.104
0.104
0.104
0.104
MAX
-
A1
0.006
0.006
0.006
0.007
0.007
0.007
0.007
±0.003
-
A2
0.057
0.057
0.057
0.092
0.092
0.092
0.092
±0.002
-
b
0.017
0.017
0.017
0.017
0.017
0.017
0.017
±0.003
-
c
0.009
0.009
0.009
0.011
0.011
0.011
0.011
±0.001
-
D
0.193
0.341
0.390
0.406
0.504
0.606
0.704
±0.004
1, 3
E
0.236
0.236
0.236
0.406
0.406
0.406
0.406
±0.008
-
E1
0.154
0.154
0.154
0.295
0.295
0.295
0.295
±0.004
2, 3
e
0.050
0.050
0.050
0.050
0.050
0.050
0.050
Basic
-
L
0.025
0.025
0.025
0.030
0.030
0.030
0.030
±0.009
-
L1
0.041
0.041
0.041
0.056
0.056
0.056
0.056
Basic
-
h
0.013
0.013
0.013
0.020
0.020
0.020
0.020
Reference
-
16
20
24
28
Reference
-
N
SO-8
SO16
(0.150”)
8
14
16
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
10
FN7467.3
February 22, 2007
EL8188
SOT-23 Package Family
MDP0038
e1
D
SOT-23 PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
E1
2
E
3
0.15 C D
1
2X
2
3
0.20 C
5
2X
e
0.20 M C A-B D
B
b
NX
0.15 C A-B
1
3
SOT23-5
SOT23-6
TOLERANCE
A
1.45
1.45
MAX
A1
0.10
0.10
±0.05
A2
1.14
1.14
±0.15
b
0.40
0.40
±0.05
c
0.14
0.14
±0.06
D
2.90
2.90
Basic
E
2.80
2.80
Basic
E1
1.60
1.60
Basic
e
0.95
0.95
Basic
e1
1.90
1.90
Basic
L
0.45
0.45
±0.10
L1
0.60
0.60
Reference
N
5
6
Reference
D
2X
Rev. F 2/07
NOTES:
C
A2
2. Plastic interlead protrusions of 0.25mm maximum per side are not
included.
SEATING
PLANE
A1
0.10 C
1. Plastic or metal protrusions of 0.25mm maximum per side are not
included.
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
NX
5. Index area - Pin #1 I.D. will be located within the indicated zone
(SOT23-6 only).
(L1)
6. SOT23-5 version has no center lead (shown as a dashed line).
H
A
GAUGE
PLANE
c
L
0.25
0° +3°
-0°
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11
FN7467.3
February 22, 2007